Microsemi UG0826 PolarFire MIPI CSI-2 Transmitter User Guide
- June 9, 2024
- Microsemi
Table of Contents
UG0826 Polar Fire MIPI CSI-2 Transmitter
User Guide
UG0826
User Guide
Polar Fire MIPI CSI-2 Transmitter
UG0826 Polar Fire MIPI CSI-2 Transmitter
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Revision History
The revision history describes the changes that were implemented in the
document. The changes are listed by revision, starting with the current
publication.
1.1 Revision 6.0
The following is a summary of changes made in this revision.
- Added support of 8-lanes configuration for all the supported data types.
- Replaced Figure 13, page 10.
1.2 Revision 5.0
- MIPI CSI2 Transmitter IP is updated with several features as follows:
- Compile Time Configuration
- Run Time Configuration
- Support of 4 pixels per clock
- Added support for Data types like Raw12, Raw14, Raw16 and RGB-888 for 1, 2, and 4 lanes
- Replaced Figure 8, page 7 and Figure 18, page 13.
- Added following sections:
- Key Features, page 2, Supported Families, page 2, MIPI CSI-2 Transmitter IP Configuration, page 2, Inputs and Outputs, page 5, Hardware Implementation for Compile Time, page 6, Hardware Implementation for Run Time, page 9, and Short Packet, page 12.
- License, page 14, Installation Instructions, page 15, and Resource Utilization, page 16.
1.3 Revision 4.0
Revision 4.0 was published in June 2019. In this revision, the document was
updated for Libero SoC Polar Fire v12.1.
1.4 Revision 3.0
Revision 3.0 was published in October 2018. In this revision, the document was
updated for Libero SoC Polar Fire v2.3.
1.5 Revision 2.0
Revision 2.0 was published in September 2018. In this revision, RAW10 data
type support is added to the IP, through out the document.
1.6 Revision 1.0
The first publication of this document.
Introduction
MIPI CSI-2 is a standard specification defined by Mobile Industry Processor
Interface (MIPI) Alliance.
The Camera Serial Interface 2 (CSI-2) specification defines an interface
between a peripheral device (camera) and a host processor (baseband,
application engine). This user guide describes the MIPI CSI-2 transmitter,
which encodes the pixel data compliant to MIPI CSI-2 standard. The IP Core
supports multi-lane (1, 2, 4, and 8 lanes) for RAW8, RAW10, RAW12, RAW14,
RAW16, and RGB-888 data types.
MIPI CSI-2 transmitter operates in two modes—high-speed mode and low-power
mode. In high-speed mode, MIPI CSI-2 supports the transport of image data
using short and long packets. Short packets provide frame synchronization and
line synchronization information. Long packet provides the pixel information.
The sequence of transmitted packets is:
- Frame start (short packet)
- Few image data packets (long packets)
- Frame End (short packet)
One long packet is equivalent to one image data line. The following figure shows the video data stream.
Note:
FS: Frame Start Packet (short packet)
Image: Pixel data of image embedded in Long Packet
FE: Frame End Packet (short packet)
2.1 Key Features
- Supports Raw8, Raw10, RAW12, RAW14, RAW16, and RGB-888 data types for 1, 2, 4, and 8 lanes
- Supports 4 pixels per input clock
- Supports configuration of IP for Data type and MIPI Lanes at Compile time and Run Tim
2.2 Supported Families
- Polar Fire® SoC
- Polar Fire®
2.3 MIPI CSI-2 Transmitter IP Configuration
MIPI CSI-2 Transmitter can be configured in two modes:
- Change of Data type and Number of MIPI Lanes at Compile time
At compile time user can configure Data type, number of MIPI Lanes, Byte
Frequency in MHz, and Horizontal Resolution.
Note: If the value of byte frequency has a decimal value, then consider
its floor value to configure the byte frequency. For example, if the byte
frequency has a decimal value of 148.2 MHz or 148.6 MHz, then configure with
the floor value of 148 MHz in the IP configurator.
- Change of Data type and Number of MIPI Lanes at Run time
Data type and several MIPI Lanes can be changed dynamically by Input ports at the Run time. Horizontal Resolution can be changed at the Compile time.
Hardware Implementation
3.1 Architecture of MIPI CSI-2 Transmitter
The following figure shows the MIPI CSI2 Transmitter solution that contains
the MIPI CSI2 Tx IP. This IP is used in conjunction with the Polarize MIPI IOD
generic interface block and PLL. The figure shows the pin connections from
the MIPI CSI2 Tx IP to the Polarize IOG. A PLL is required to generate the
TxByteClkHs_i clock (Byte clock). The input clock to the PLL is the Pixel
clock. The PLL is configured to produce the TxByteClkHs_i clock, the MIPI bit
clock and 90° phase shifted Bit_clock_90, whose frequency is based on the
pixel clock, and the number of lanes used.
An external resistor network as shown in following figure is needed to
accommodate low power (LP) and high-speed (HS) mode transitioning on the same
signal pairs and to set the voltage swing to 200 mV during HS clock and data
transfers.
3.2 Inputs and Outputs
The following table lists the input and output ports of the MIPI CSI-2 Tx
configuration parameters.
Table 1 • Inputs and Outputs Ports of MIPI CSI-2 Transmitter
Signal Name| Direction| Width| Port Valid under|
Description
---|---|---|---|---
RESET_n_i| Input| 1| | Active Low Asynchronous reset signal to design.
pixel_clock_i| Input| 1| | Input clock with which incoming pixels are sampled
TxByteClkHs_i| Input| 1| | Tx Byte Clock (gearing ratio of 4). This clock must
be configured such that the pixels sent on the MIPI CSI2 Interface are sampled
according to it.
frame_valid_i| Input| 1| | Asserts High for every valid frame
line_valid_i| Input| 1| | Asserts High for every valid packet
data_in_0_i| Input| [31:0]| No_of_Pixels = 1 or 4| Input Pixel data
datain(1-3)_i| Input| [31:0]| No_of_Pixels = 4| Input Pixel data when there
are 4 pixels per clock
Data width| Input| [7:0]| Run Time| Supports for RAW8, RAW10, RAW12, RAW14,
RAW16, and RGB-888 data types.
Lane width| Input| [3:0]| Run Time| Supports for 1, 2, 4, and 8 lanes
timing_reg_i| Input| [11:0]| Run Time| D-PHY timing values under Run time
Configuration.
11:8 – Used for address detection 7:6 – Reserved
5:0 – Timing values in no of byte clocks
No_of_Pixels_i| Input| [2:0]| Run Time| It is configured either 1 pixel per
clock or 4 pixels per clock
L(0 – 3)_LP_DATA| Output| 1| | Low Power Data (P side)
L(0 – 3)_LP_DATA_N| Output| 1| | Low Power Data (N side)
LP_CLK| Output| 1| | Low Power Clock (P side)
LP_CLK_N| Output| 1| | Low Power Clock (N side)
L(0 – 3)_TXD_DATA| Output| [7:0]| | Lane 0 to Lane 3 Transmit bytes
HS_CLK_SEL| Output| 1| | High Speed mode clock select
HS_DATA_SEL| Output| 1| | High Speed mode data select
3.3 Configuration Parameters
Table 2 • Configuration Parameters
Parameter Name| Configurator Prompt| Parameter Valid
under| Description
---|---|---|---
DATA WIDTH| Data Type| Compile Time| Input pixel data-width. Supports for
RAW8, RAW10, RAW12, RAW14, RAW16, and RGB-888
g_LANE_WIDTH| No of MIPI Lanes| Compile Time| Supports for 1, 2, 4, and 8
lanes
g_HORIZONTAL_RESOLUTION| Horizontal Resolution| Compile Time / Run Time|
Active horizontal resolution
g_TX_BYTE_FREQ| Byte Frequency in MHz| Compile Time| Byte Frequency in MHz
derived by calculation. Refer PLL, page 8.
g_EXECUTION_TYPE| Data type and Lane Configuration| | Can be configured either
in Compile Time or Run Time
g_NO_OF_PIXELS| NO_OF_PIXELS| Compile Time| The following options are
available: 1 – One pixel per clock 4 – Four pixels per clock
3.4 Hardware Implementation for Compile Time
The following figure shows the block diagram of MIPI CSI-2 Transmitter in
Compile Mode.
3.4.1 Design Description for Compile Time
This section describes the different internal modules of the MIPI CSI-2
transmitter core in compile time mode.
3.4.1.1 Pixel to Byte Conversion
This module converts the incoming pixel data to bytes based on the configured
IP’s number of lanes. The user is expected to transmit the pixels along with
the control signals line_valid_i and frame_valid_i. It uses an internal clock
crossing FIFO to convert the incoming data from pixel clock to byte clock
domain.
It also generates the byte enable signal, which indicates the valid byte data.
3.4.1.2 Packet Formatter
This module consists of two blocks – Header insertion and lane distribution
block. On detecting the control signals (frame_valid_i), it transmits the
frame start short packet, then long packet with the header inserted and the
data from the pixel to byte conversion module. When vertical resolution number
of packets are generated, frame end short packet is generated. It also
calculates the Error Correction Code (ECC) and appends it to the packet
header.
3.4.1.3 PLL
Pixel_clock_i is the input clock with which incoming pixels are sampled. A PLL
is used to generate the Byte clock (TxByteClkHs_i) and bit clocks used by the
MIPI DPHY block (Polar Fire IOD). TxByteClkHs_i must be configured such that
the output MIPI CSI2 compliant packets sent on the interface are sampled. The
following equations show the relation between Pixel_clock_i and TxByteClkHs_i
depending on the number of lanes configured. TxByteClkHs_i = (Pixel_clock_i ×
Bits per pixel) / (Number of lanes × 8) MIPI bit clock = 4 × TxByteClkHs_i
Two serial MIPI bit clocks are required—0° and 90° phase shifted.
MIPI CSI-2 TX IP supports RAW8, RAW10, RAW12, RAW14, RAW16, and RGB-888 data
types. For RAW8 data type, one 8-bit pixel is transmitted per clock, and for
RAW10 data type, one 10-bit pixel is transmitted per clock.
3.4.1.4 Low Power/High-Speed
When the MIPI packet enable is asserted, transition to high-speed mode follows
the following sequence:
LP-11, LP-01, LP-00, HS0/1. It indicates the HS request path and following the
timing based on MIPI DPHY Specification version 1.1.
LP request, Escape mode and Turn around modes are not supported.
3.4.1.5 D-PHY TX
This module uses Polar Fire IOD generic blocks to convert Byte data to serial
data. A gearing ratio of four is used to convert the parallel data to serial
data. It generates both HS and LP signals (for both clock and data). It also
switches between HS and LP modes using the HS_CLK_SEL and HS_DATA_SEL signals.
3.4.1.6 CRC Calculator
This module uses the bytes generated from the pixel to byte conversion module
and calculates the 16-bit CRC for the generated bytes. This 16-bit CRC is sent
to the packet formatter, which appends the value at the end of the long
packet.
The checksum is realized as 16-bit CRC based on the generator polynomial:
X1612 5 0 +X +X +X 
3.5 Hardware Implementation
for Run Time
The following figure shows the block diagram of MIPI CSI-2 Transmitter in
Dynamic Mode.
3.5.1 Design Description for Run Time
This section describes the different internal modules of the MIPI CSI-2
transmitter core in Run time mode in addition to compile time modules.
3.5.1.1 Dynamic PLL
A PLL with DRI port is used to generate the HS_IO_clock, HS_IO_clock_90, and
TX byte by dynamically configuring the PLL Registers through DRI (Dynamic
Reconfiguration Interface). The base address of PLL are as follows:
- Base Adder for PLL_SE_0 is 0x8010000
- Base Adder for PLL_SE_1 is 0x8020000
- Base Adder for PLL_NE_0 is 0x8040000
- Base Adder for PLL_NE_1 is 0x8080000
- Base Adder for PLL_NW_0 is 0x8100000
- Base Adder for PLL_NW_1 is 0x8200000
- Base Adder for PLL_SW_0 is 0x8400000
- Base Adder for PLL_SW_1 is 0x8800000
The following are the set of PLL registers that need to be configured to achieve dynamic clocking:
- RF DIV
- FB DIV
- Post Div clock 0_1
- Post Div clock 2_3
- Phase
The PLL is configured from Core-ABC IP for RAW8, RAW10, RAW12, RAW14, RAW16,
and RGB-888 data types for 1, 2, 4, and 8 lanes.
Note: For more information about PLL register configuration, refer to
Polar Fire-device-register-map.
3.5.1.2 Input Decoder
This module is used to generate the inputs for Core-ABC IP and MIPI CSI2
Transmitter IP. Depending on the values of input switches of the input
decoder, this module will generate the output values for Core ABC IP in a
one-hot encoding manner, whereas Data_width_O and Lane width_O outputs for
MIPI CSI2 Transmitter IP.
3.5.1.3 Core-ABC
Core-ABC is a light weight soft processor that can be used to program PLL
registers, Input values to PF_DRI and MIPI CSI2 TX IP for various data types
and lanes.
D-PHY timing values in dynamic mode have to be configured from Core-ABC. The
following are the equations to calculate timing values.
G_TX_BYTE_FREQ has been calculated from the equation, which is shown in PLL,
page 8. Sample Core-ABC program is provided as follows for 1 Lane
RAW8.
3.5.1.4 PF_DRI
This module is used to convert APB transactions from Core-ABC into Dynamic
Reconfiguration Interface (DRI) transactions. These transactions are fed into
Dynamic PLL by DRI.
3.6 Timing Diagrams
3.6.1 Short Packet
The following figure shows the timing waveform of the short packet for 1 Lane
RAW8 format.
3.6.2 Long Packet
The following figure shows the timing waveform of the long packet for 1 Lane
RAW8 format.
License
The core is license locked for clear text RTL. The core supports the generation of Encrypted RTL for the Verilog version of the core with no license.
Installation Instructions
The core must be installed into Libero software. It is done automatically
through the Catalog update function in Libero, or the CPZ file can be manually
added using the Add Core catalog feature. Once the CPZ file is installed in
Libero, the core can be configured, generated, and instantiated within Smart
Design for inclusion in the Libero project.
For further instructions on core installation, licensing, and general use,
refer to Libero SoC Online Help.
Resource Utilization
The following table shows the resource utilization of a sample MIPI CSI-2 Transmitter Core implemented in a Polar Fire FPGA (MPF300TS-1FCG1152I package) for 4 Lane RAW8 configuration in compile time mode.
Table 3 • Resource Utilization of the MIPI CSI-2 Transmitter in compile time mode
| Element | Usage |
|---|---|
| DFFs | 906 |
| 4-input LUTs | 957 |
| LSRAM | 11 |
| Math Blocks | 1 |
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References
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