Microsemi UG0935 DisplayPort IP User Guide

Microsemi UG0935 DisplayPort IP User Guide

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1 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

1.1 Revision 2.0

Removed the reference design demo information.

 1.2 Revision 1.0

The first publication of this document.

Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0

2 Introduction

2.1 Overview

DisplayPort IP is targeted for the PolarFire FPGA application and includes DisplayPort Tx IP and DisplayPort Rx IP. These two IP implement part of the DisplayPort 1.4 Link Layer function.

2.2  Key Features

The key features of DisplayPort Tx and Rx IP are listed as follows:

• Support 1, 2, or 4 lanes.
• Support 8 bpc RGB/YCbCr 4:4:4 (24 bits per pixel).
• Support up to 8.1 Gbps per lane.
• Support DisplayPort 1.4 protocol.
• Only support a single video stream or SST mode, and the MST mode is not supported.
• Audio transmission is not supported.

2.3 Supported Families

• PolarFire® SoC
• PolarFire®
• RTG4TM
• IGLOO®2
• SmartFusion®2

2.4 License

DisplayPort IP clear RTL is license locked and the obfuscated RTL available for free.

2.4.1 Obfuscated

Complete RTL code is provided for the core, allowing the core to be instantiated with the Smart Design tool. Simulation, synthesis, and layout can be performed within Libero® System-on-Chip (SoC). The RTL code for the core is obfuscated.

2.4.2 RTL

Complete RTL source code is provided for the core.

Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0

2.5 DisplayPort Tx IP Architecture

The following figure shows the DisplayPort Tx IP implementation.

As shown in the preceding figure, DisplayPort Tx IP includes the Pixel Steering module, Lane transmitter module, Scrambler module, and AUX_CH module.

Pixel Steering assigns input pixels to DisplayPort lanes. The lane transmitter module generates a video data stream with blank data or training data. Scrambler scrambles the lane transmission data. AUX_CH module transmits the AUX Request command to the DisplayPort Sink device or receives AUX Reply from the DisplayPort Sink device.

2.6 DisplayPort Rx IP Architecture

The following figure shows the DisplayPort Rx IP implementation.

DisplayPort Rx IP includes the Descrambler module, Lane receiver module, Video Stream Receiver module, and AUX_CH module. Descrambler de-scrambles the input lane data. Lane receiver demultiplexes all kinds of data on each lane. The Video Stream Receiver gets video pixels from the lane receiver, it recovers the video stream signal. AUX_CH module receives the AUX Request command from DisplayPort Source device and transmits AUX Reply to DisplayPort Source device.

2.7 Resource Utilization

The following table lists the resource utilization of PolarFire FPGA family in DisplayPort IP (configured for 24 bits per pixel and four parallel pixels on the interface).

3 Functional Description

3.1 HPD

DisplayPort Tx IP detects Hot Plug Detect (HPD) assertion, de-assertion, and HPD interrupt event. It reports the HPD event through an interrupt. After HPD assertion, which means a DisplayPort monitor is connected, DisplayPort Source application software should start the training procedure.
DisplayPort Rx IP outputs HPD signal according to DisplayPort Sink application software settings. After DisplayPort Rx IP is ready, DisplayPort Sink application software should set the HPD signal to 1. When it expects the DisplayPort Source device to re-read Sink device status or re-training, DisplayPort Sink application software should set an HPD to generate the HPD interrupt signal.

3.2 AUX Channel

DisplayPort Source and Sink device communicate through an AUX Channel. Source device sending request transaction to the Sink device and the Sink device sending Reply transaction to Source Device.
DisplayPort Tx and Rx IP implements the AUX transaction transmitter and receiver. For AUX transaction transmitter, DisplayPort Source or Sink application software provides all AUX transaction content bytes, DisplayPort Tx and Rx IP generate the transaction bitstream. For the AUX transaction receiver, DisplayPort Tx and Rx IP receive the transaction and extract all bytes to DisplayPort application software.
The Link Policy Maker and Stream Policy Maker should be implemented in the DisplayPort application software.

3.3 Video Stream Transmission

DisplayPort Tx and Rx IP supports 8 bpc RGB/YCbCr 4:4:4, and only supports a single video stream.
After training is done and the video stream is ready, DisplayPort Tx IP and RX IP start to transmit video stream.

DisplayPort Source application software should configure the video stream attribute MSA and enable DisplayPort Tx IP video transmission. The VSC packet is not supported. DisplayPort Tx and Rx IP are using MISC0 and MISC1 in MSA for Pixel Encoding/Colorimetry Format Indication.

After training, DisplayPort Rx IP should be enabled for video receive. DisplayPort Rx IP gets the received MSA and sets the recovery video format parameter to let DisplayPort Rx IP output the correct video stream signal.

DisplayPort Tx and Rx IP support synchronous video clock mode and asynchronous video clock mode. For synchronous video clock mode, Mvid and Nvid are fixed value in MSA, DisplayPort Source application software should set Mvid and Nvid. For asynchronous video clock mode, Nvid is fixed and configured by software. The user needs to generate Mvid and send Mvid to DisplayPort Tx IP.

DisplayPort Rx IP does not include a video clock recovery function. The user should recovery the video clock outside DisplayPort Rx IP or use a fixed high enough frequency clock to output video stream data.

4 Typical Application

4.1 DisplayPort Tx IP Application

The following figure shows the typical DisplayPort Tx IP application.

As shown in the preceding figure, the RGB input module interface gets a video stream signal. The Image Processing module processes the video stream according to system requirements. It outputs the video stream to DisplayPort Tx IP. DisplayPort Tx IP outputs four lanes data to the 8B10B encoder. After 10B encoding, lanes’ data are transmitted through Transceiver lanes.
Before video stream transmission, the DisplayPort Source application software which is running on RISC-V, controls DisplayPort Tx IP to finish training work with the attached DisplayPort Sink device. To do training and Link Policy Maker, all transactions are transmitted on the AUX Channel.

4.2 DisplayPort Rx IP Application

The following figure shows the typical DisplayPort Rx IP application.

As shown in the preceding figure, the transceiver block receives four lanes data. There are four asynchronous FIFO to synchronize all lanes data into one clock domain. These four lanes data are decoded to 8B code in 8B10B decoder modules. DisplayPort Rx IP gets lanes’ 8B data and output video stream data; it also works with RISC-V software to finish the training and Link Policy Maker. The recovered video stream data is processed in the Image Processing module and generates output on the RGB output interface.

Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0

5 DisplayPort Tx IP Interface Signal

5.1 Interface

The following table shows the input and output ports for DisplayPort Tx IP.

5.2 Configuration Parameters

The configuration parameter for CoaXPress Host IP is listed in the following table.

5.3 Key Interface Description

5.3.1 Input Video Stream Interface Signal

The following figure shows the timing diagram of the input video stream signal interface.

As shown in the preceding figure, hsync_i is asserted for several cycles before each line. If there are n lines in a video frame, there are n hsync_i asserted. Before the first line and the first asserted hsync_i, vsync_i should be asserted for several cycles.
For four parallel pixels input case, pixel_val_i should be 4’b1111 when input pixel data is available and 4’b0000 when input pixel data is not available. For two parallel pixels input case, pixel_val_i should be 2’b11 when input pixel data is available and 2’b00 when pixel data is not available. For the one pixel input case, pixel_val_i should be 1’b1 when input pixel data is available and 1’b0 when pixel data is not available.

6 DisplayPort Rx IP Interface Signal

6.1 Interface

The following table shows the input and output ports for DisplayPort Rx IP.

6.2 Configuration Parameters

6.3 Key Interface Description

6.3.1 Output Video Stream Interface Signal

The following figure shows the timing diagram of the output video stream signal interface.

As shown in the preceding figure, hsync_o is asserted for several cycles before each line. If there are n lines in a video frame, there are n hsync_o asserted. Before the first line and the first asserted hsync_o, vsync_o is asserted for several cycles. The position and width of VSYNC and HSYNC are configured by software.

7 DisplayPort Tx IP Configuration

7.1 HPD Detection

DisplayPort Tx IP detects the input HPD signal to check the status of the attached DisplayPort Sink device. The HPD event includes three types.

• HPD assertion, it means DisplayPort Sink device is connected.
• HPD de-assertion, it means DisplayPort Sink device is disconnected.
• HPD interrupt, it means the DisplayPort Sink device’s status has changed.

When the HPD event is detected and interrupt is enabled, DisplayPort Tx IP could output a pulse on the int_o port and indicates the interrupt type on interrupt register 0x0188.

7.2 Transmit AUX Request Transaction

To transmit a Native Writing AUX Request transaction, DisplayPort Tx application software should do the following steps:

1. Write all the writing bytes into register 0x010C, write one byte for each writing operation.
2. Write the DPCD address into register 0x0104.
3. Write (WritingBytesNum-1) into register 0x0108.
4. Write ((WritingBytesNum << 16) | (0x00000001 << 8) | 0x00000008) into registers 0x0100.

To transmit a Native Reading AUX Request transaction, DisplayPort Tx application software should do the following steps:

1. Write the DPCD address into register 0x0104.
2. Write (ReadingBytesNum-1) into register 0x0108.
3. Write ((0x00000000<<16) | (0x00000001<<8) | 0x00000009) into registers 0x0100.

To transmit an I2C-Over-AUX Writing Request transaction, DisplayPort Tx application software should do the following steps:

1. Write all the writing bytes into register 0x010C, write one byte for each writing operation.
2. Write the DPCD address into register 0x0104.
3. Write (WritingBytesNum-1) into register 0x0108.
4. Write ((WritingBytesNum << 16) | (0x00000001 << 8) | (MOT<<2) | 0x00000000) into registers 0x0100.

To transmit an I2C-Over-AUX Reading Request transaction, DisplayPort Tx application software should do the following steps:

1. Write the DPCD reading address into register 0x0104.
2. Write (ReadingBytesNum-1) into register 0x0108.
3. Write ((0x00000000<<16) | (0x00000001<<8) | (MOT<<2) | 0x00000001) into registers into 0x0100.

7.3 Receive AUX Reply Transaction

After sending an AUX Request transaction to the DisplayPort Sink device, DisplayPort Source application software should wait for the AUX Reply transaction. When the AUX Reply is arrived and interrupt is enabled, DisplayPort Tx IP could output an interrupt signal and record this event in the interrupt register.
To read the received AUX Reply transaction from DisplayPort Tx IP, software should do the following steps:

1. Read register 0x012C to know AUX Reply transaction length AuxReplyByteNum.
2. Read register 0x0124 AuxReplyByteNum times to get all the AUX Reply Transaction bytes.
3. Software checks the Reply type by checking the first reading transaction byte bit [7:4], it could be AUX ACK, NACK, or AUX DEFER. Bit [3:0] is reserved. 4. If AuxReplyByteNum > 1, the followed bytes are reading data from the DPCD registers.

7.4 DisplayPort Lanes Training

At the first training stage, DisplayPort Tx IP should output TPS1 to get the attached DisplayPort Sink device to get LANEx_CR_DONE. The software should configure the following steps to enable TPS1 transmission:

1. Write enabled lane number into register 0x0004, it could be enabled 4 lanes, 2 lanes, or 1 lane.
2. Write 0x01 into register 0x0018 to enable TPS1.
3. Write 0x00 into register 0x0010 to disable scrambler.

At second training stage, according to the DisplayPort Sink device feature, DisplayPort Tx IP should output TPS2/TPS3/TPS4 to get the attached DisplayPort Sink device to get LANEx_EQ_DONE, LANEx_SYMBOL_LOCKED, and INTERLANE_ALIGN_DONE. The software should configure the following steps to enable TPS2/TPS3/TPS4 transmissions:

1. Write enabled lane number into register 0x0004. It could be enabled 4 lanes, 2 lanes, or 1 lane.
2. To transmit TPS2, write 0x02 into register 0x0018 to enable TPS2. For TPS3, writing 0x03. For TPS4, writing 0x04.
3. For TPS2 and TPS3, write 0x00 into register 0x0010 to disable scrambler. For TPS4, write 0x01 to enable scrambler.

In the training procedure, before sending the TPS pattern, DisplayPort Source application software might need to configure Transceiver SI settings and the Transceiver rate. The Transceiver is not part of this IP, and the Transceiver settings configuration guide is not included in this user guide.

7.5 Video Stream Transmission

After training is completed, DisplayPort Tx IP can transmit the video stream to the sink device. To enable video transmission, software should do the following configuration:

1. Enable scrambler, write 0x01 into register 0x0010.
2. Configure MSA, configure registers from address 0x00C0 to address 0x00EC.
3. Enable video transmission, write 0x01 into register 0x0000.

7.6 Register Definition

The following table shows the internal registers defined in DisplayPort Tx IP.

8 DisplayPort Rx IP Configuration

8.1 HPD

When the DisplayPort Sink device is ready and connected to the DisplayPort Source device, DisplayPort Sink application software should assert the HPD signal to 1 by writing 0x01 into register 0x0140.
DisplayPort Sink application software should monitor the status of the sink device. If the sink device needs a source device to read the DPCD registers, sink device software should send an HPD interrupt by writing 0x01 into register 0x0144, then write 0x00 into 0x0144.

8.2 Receive AUX Request Transaction

When DisplayPort Rx IP received an AUX Request transaction and interrupt is enabled, the software should receive the NewAuxReply event interrupt. The software should do the following steps to read the received AUX Request transaction from DisplayPort IP:

1. Read register 0x012C to know the length (RequestBytesNum) of the received AUX transaction.
2. Read register 0x0124 RequestBytesNum times to get all the bytes of the received AUX transaction.
3. AUX Request transaction COMM[3:0] is the first reading byte bit [7:4].
4. DPCD address is ((FirstByte[3:0]<<16) | (SecondByte[7:0]<<8) | (ThirdByte[7:0])).
5. AUX Request Length field is FourthByte[7:0].
6. For DPCD writing Request transaction, all the bytes after the length field are writing data.

8.3 Transmit AUX Reply Transaction

After received an AUX Request transaction, the software should configure DisplayPort Rx IP to transmit an AUX Reply transaction as soon as possible. The software is responsible to determine all the Reply transaction bytes, which includs the Reply type.
To transmit an AUX Reply, software should do the following steps:

1. If AUX Reply transaction including DPCD reading data, write all the read data into register 0x010C byte by byte. If no DPCD reading data to be transmitted, skip this step.
2. Determine how many DPCD reading bytes (AuxReadBytesNum). If no DPCD reading bytes, AuxReadBytesNum is 0.
3. Determine the AUX Reply type (ReplyComm).
4. Write ((AuxReadBytesNum<<16) | ReplyComm) into register 0x0100.

8.4 DisplayPort Lanes Training

At the first training stage, the DisplayPort Source device transmits TPS1 to make the attached DisplayPort Sink device to get LANEx_CR_DONE.

At the second training stage, the DisplayPort Source device transmits TPS2/TPS3/TPS4 to get the attached DisplayPort Sink device to get LANEx_EQ_DONE, LANEx_SYMBOL_LOCKED, and INTERLANE_ALIGN_DONE.

This LANEx_CR_DONE means FPGA Transceiver CDR is locked. Since, FPGA Transceiver is not part of DisplayPort Rx IP, LANEx_CR_DONE.

LANEx_SYMBOL_LOCKED means 8B10B decoder decodes 8B bytes correctly. Since the 8B10B decoder is not part of DisplayPort Rx IP, LANEx_SYMBOL_LOCKED.

Before the training procedure, DisplayPort Sink application software should let the source device know that DisplayPort Rx IP supports TPS3 and TPS4.

When the source device is sending TPS3/TPS4 (Source device writes DPCD_0x0102 to indicates TPS3/TPS4 transmission), software should do the following steps to check if training is done:

1. Write enabled lanes number into register 0x0000.

2. Write 0x00 into register 0x0014 to disable descrambler for TPS3. Write 0x01 to enable descrambler for TPS4.

3. Waiting until Source device reading DPCD_0x0202 and DPCD_0x0203 DPCD registers.

4. Read register 0x0038 to know if DisplayPort Rx IP lanes received TPS3. Set LANEx_EQ_DONE to
   1 when received TPS3.

5. Read register 0x0018 to know if all lanes are aligned. Set INTERLANE _ALIGN_DONE to 1 if all lanes are aligned.

In the training procedure, the software might need to configure Transceiver SI settings and Transceiver lane rate.

8.5 Video Stream Receiver

After training is completed, DisplayPort Rx IP should enable the video stream receiver. To enable the video receiver, the software should do the following configuration:

1. Write 0x01 into register 0x0014 to enable descrambler.
2. Write 0x01 into register 0x0010 to enable video stream receiver.
3. Reading MSA from register 0x0048 to register 0x006C until getting meaningfully MSA values.
4. Write FrameLinesNumber into register 0x00C0. Write LinePixelsNumber into register 0x00D8. For example, we know it is 1920×1080 video stream from MSA, then write 1080 into register 0x00C0 and write 1920 into register 0x00D8.
5. Read register 0x01D4 to check if the recovered video stream frame has expected HWidth and expected VHeight.
6. Read register 0x01F0 to clear and discard the reading value since this register records the status from the last reading.
7. Waiting for about 1 second or several seconds, Read register 0x01F0 again. Checking bit [5] to check if the recovered video stream HWidth is locked. 1 means unlocked and 0 means locked. Checking bit [21] to check if recovered the video stream VHeight is locked. 1 means unlocked and 0 means locked.

8.6 Register Definition

The following table shows the internal registers defined in DisplayPort Rx IP.

References

• Microsemi | Semiconductor & System Solutions | Power Matters

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