NXP S32G-VNP-GLDBOX3 Board User Guide

NXP S32G-VNP-GLDBOX3 Board

Get To Know S32G-VNP-GLDBOX3

S32G-VNP-GLDBOX3 Board Overview
The S32G-VNP-GLDBOX3 is a compact, highly-optimized and integrated reference design board featuring the S32G399A Vehicle Network Processor. This board provides reference for various typical automotive applications such as:

• Service-oriented gateway
• High-performance central compute unit
• Safety checker for ADAS and autonomous driving
• Black-box for vehicle data logging
• Automotive access point

Figure 1.1 shows the board overview of S32G-VNP-GLDBOX3.

S32G-VNP-GLDBOX3 Block Diagram
Figure 1.2 shows the block diagram of S32G-VNP-GLDBOX3.

S32G-VNP-GLDBOX3 Hardware Resources
The resources of S32G-VNP-GLDBOX3 are listed as below:

• Processor

  • 8x Arm Cortex-A53 cores (with optional cluster lockstep)
  • 4x dual-core lockstep Arm Cortex-M7 cores
  • Hardware Security Engine (HSE)
  • CAN, LIN and FlexRay offload with Low Latency Communications Engine (LLCE)
  • Gigabit Ethernet Packet Forwarding Engine (PFE)
  • 20 MB Embedded System RAM with ECC
  • 32KB Standby RAM with ECC

• External Storage

  • 1x on-board NOR Flash memory (64MB)
  • 1x SD card slot
  • 1x on-board eMMC (32GB)
  • 1x on-board LPDDR4 (4GB)

• Ethernet—12ports

  • 1x 100BASE-TX
  • 6x 100BASE-T1
  • 4x 1000BASE-T
  • 1x 1G/2.5GBASE-T

• PCIe

  • 1x M.2 M-key slot*
  • 1x M.2 E-key slot*
  • 1x PCIe x1 socket

• LIN

  • 4x LLCE LIN
  • 1x LINFlexD

• CAN/CAN FD

  • 16x LLCE CAN/CAN FD
  • 2x FlexCAN /CAN FD

• FlexRay
  1x LLCE FlexRay

• USB
  1x USB 2.0 I/F Host/Device mode

• Scalable interface

  • 1x DSPI
  • 5x ADC
  •  1x I2C
  • 1x WKUP

• RTC
  Support on-board external RTC

• Debug

  • 1x 20-pin JTAG for S32G
  • 1x 10-pin JTAG for SJA1110A
  • 1x Aurora Trace
  • 2x UART

Hardware Package Overview

This section describes hardware package of S32G-VNP-GLDBOX3. Hardware and accessories are shown in the figure 2.1.

Hardware Connection Instruction
To connect any cables to S32G-VNP-GLDBOX3, follow the instructions shown in figure 2.2.

S32G-VNP-GLDBOX3 Switch Setting

Switch description
The table below describes the DIP switches of S32G-VNP-GLDBOX3

Table 3.1. DIP switches

OFF : Connects the S32G399A’s uSDHC interface to eMMC chip.

SW4[1:8]| Setting of RCON PIN [0:7] value
SW5[1:8]| Setting of RCON PIN [8:15] value
SW6[1:8]| Setting of RCON PIN [16:23] value
SW7[1:8]| Setting of RCON PIN [24:31] value
SW8[1]| Please refer to chapter3.8 SerDes Interface of S32G-VNP-GLDBOX3 Reference Manual
SW9[1]| 1-OFF, 2-OFF : BOOTMOD1 value: 0

1-ON, 2-OFF : BOOTMOD1 value: 1

1-OFF,2-ON : BOOTMOD1 value: RESET_B

1-ON, 2-ON : BOOTMOD1 value: INV_RESET_B

SW9[2]
SW10[1]| 1-OFF, 2-OFF : BOOTMOD0 value: 0

1-ON, 2-OFF : BOOTMOD0 value: 1

1-OFF,2-ON : BOOTMOD0 value: RESET_B

1-ON, 2-ON : BOOTMOD0 value: INV_RESET_B

SW10[2]
SW11[1]| ON : Connects GPIO6,GPIO7,GPIO95 to U128(RGB LED)

OFF : Connects GPIO6,GPIO7,GPIO95 to J5 connector

SW17[1]| Please refer to chapter3.8 SerDes Interface of S32G-VNP-GLDBOX3 Reference Manual
SW17[2]| Please refer to chapter3.8 SerDes Interface of S32G-VNP-GLDBOX3 Reference Manual
SW17[3]| Please refer to chapter3.8 SerDes Interface of S32G-VNP-GLDBOX3 Reference Manual
SW17[4]| Please refer to chapter3.8 SerDes Interface of S32G-VNP-GLDBOX3 Reference Manual

Default Switch Setting
Figure 3.1 shows the default switch setting of S32G-VNP-GLDBOX3 when out of box.

Switch Setting for Power Selection
Figure 3.2 shows the switch setting for power selection.

Switch Setting for SD card Boot
Figure 3.3 shows the switch setting for SD card boot.

Switch Setting for eMMC Boot
Figure 3.4 shows the switch setting for eMMC boot.

Switch Setting for NOR Flash Boot
Figure 3.5 shows the switch setting for NOR Flash boot.

Switch Setting for Serial Boot
Figure 3.6 shows the switch setting for serial boot.

Connectors Overview

Figure 4.1 shows important connectors of S32G-VNP-GLDBOX3.

Table 4.1 shows connectors of the S32G-VNP-GLDBOX3 and their corresponding signals.
Table 4.1 Connectors of S32G-VNP-GLDBOX3

Power In
J6| LLCE CAN, FlexCAN, LLCE FlexRay
J44| 10-pin JTAG for SJA1110
J47| M.2 M-key Slot
J48| 20-pin JTAG for S32G
J50| Power for Fan
J53| 100BASE-T1(SJA1110A Port5, 6, 7, 8, 9, 10)
J56| M.2 E-key Slot
J57| Aurora Trace
J176| 12V Power Jack
J184| 1-2 shorted(Default): VR5510 in debug mode(VR5510 Watchdog will be disabled)
J185| 1-2 Open(Default) : Disconnect the FS0B signal to the functional safety management circuit.

J186

| 1-2 Open, 3-4 Shorted: USB PHY Rvbus resistor value is 22Kohm. 1-2 Shorted, 3-4 Open: USB PHY Rvbus resistor value is 1Kohm.

Others: reserved

J189

| 1-2 Open, 3-4 Shorted: SJA1110 performs NVM boot, uses SPI Flash.

1-2 Shorted, 3-4 Shorted: SJA1110 performs SDL boot.

Others: reserved

P1| PCIe X1 Socket
P2A(bottom)| 1000BASE-T (SJA1110A Port2)
P2B(top)| 1000BASE-T (SJA1110A Port3)
P3A(bottom)| 1000BASE-T (GMAC0)1
P3B(top)| 1000BASE-T (PFE_MAC2)1
P4| 100BASE-TX (SJA1110A Port1)1
P5| 1G /2.5G BASE-T (PFE_MAC1)1

1: In S32G-VNP-GLDBOX3, GMAC0, PFE_MAC0, PFE_MAC1 and PFE_MAC2 could all be routed to SJA1110A. Please refer to S32G-VNP-GLDBOX3 Reference Manual to get the detailed connection.

Specific Connector Instruction
Figure 4.2 shows connector definition for the LLCE CAN, FlexCAN, LLCE FlexRay, ADC, LINFlexD
and LLCE LIN, DSPI, I2C, 3V3/5V/12V power out, 12V power in signals.

Figure 4.3 shows Ethernet connectors.

S32G-VNP-GLDBOX3 Set Up

Following steps show how to run Linux BSP on CortexA53 core:

1. Download and install the terminal emulator, if not installed already. About the terminal tool, you can choose any one which is familiar to you, such as Tera Term, Putty and so on.

2.  Download and install the FT232R USB-to-UART driver, if not installed already. Go to FT232R USB-to-UART driver link .Scroll down and select the newest version. Follow the installation guides

3. Set S32G-VNP-GLDBOX3 in SD card boot mode(refer to the Figure 3.3).

4. Plug in the SD card in J3 slot. The SD card has pre-loaded Linux BSP image which runs on Corte-A53 cores.

5. Connect the UART0 port(J2) of board to PC through micro USB cable. Then open serial terminal and configure COM port in PC. Select the corresponding COM port which can be found in “Device Manager” of your PC and set 115200 as the baud rate. The configuration example is shown in the figure 5.1.

6. Connect power supply though J176 port described in Table 4.1. Turn on the power switch(refer to figure 3.2), the running logs will appear in the console as shown in Figure 5.2.

When the PC terminal emulator outputs log as shown in the Figure 5.2, it means that the Linux BSP runs successfully on S32G-VNP-GLDBOX3. User can enter “root” to log in system.

Appendix A

• Documents
  • S32G3 Data Sheet
  • S32G3 Reference Manual
  • S32G-VNP-GLDBOX3 Reference Manual
• Useful links
  • S32 Design Studio
  • S32 Debug Probe
• Support https://community.nxp.com/
• Enablement Tools
  • IDE: S32 Design Studio, Yocto , EB tresosTM
  • Software: Linux BSP, FreeRTOSTM , Real-Time Drivers(RTD)
  • Compiler: Green Hills, gcc
  • Debugger: Lauterbach, S32G Debug Probe

Disclaimer

• Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.
• NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals”, must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the rights of others.
• While NXP has implemented advanced security features, all products may be subject to unidentified vulnerabilities. Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer’s applications and products, and NXP accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products.
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References

• Power.org
• Home - NXP Community
• D2XX Drivers - FTDI
• S32 Debug Probe | NXP Semiconductors
• S32 Design Studio | NXP Semiconductors

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