intel Triple-Speed Ethernet Agilex FPGA IP Design Example User Guide

: June 9, 2024
: Intel

Table of Contents

intel Triple-Speed Ethernet Agilex FPGA IP Design Example
Quick Start Guide
Directory Structure
Generating the Design Example
Design Example Parameters
**Simulating the Triple-Speed Ethernet Intel FPGA IP Design Example
Functional Description
Design Components
Simulation
Testbench
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intel Triple-Speed Ethernet Agilex FPGA IP Design Example

intel Triple-Speed Ethernet Agilex FPGA IP Design
Example

Quick Start Guide

The Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex™ provides the capability of generating design examples for selected configurations, which allows you to:

Compile the design to get an estimate of the IP area usage and timing.
Simulate the design to verify the IP functionality through simulation.
Test the design on the hardware using the Intel Agilex I-Series Transceiver-SoC Development Kit.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Note : Hardware support is currently not available in the Intel Quartus® Prime Pro Edition Software version 22.3.

Development Stages for the Design Example

Note : In Intel Quartus Prime Pro Edition Software version 22.3, a patch is required to avoid simulation failure on the design example. For more information, refer to the KDB link: Why does simulation fail for the Triple- Speed Ethernet Intel FPGA IP Multiport Design Example?.

Related Information
Why does simulation fail for the Triple-Speed Ethernet Intel® FPGA IP Multiport Design Example?.

Directory Structure

The Triple-Speed Ethernet Intel FPGA IP design example file directories contain the following generated files for the 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA

The hardware configuration and test files (the hardware design example) are located in /hardware_test_design.
The simulation files (testbench for simulation only) are located in /example_testbench.
The compilation-only design example is located in / compilation_test_design.
The compilation test and hardware test designs use files in /ex_tse/common.

Directory Structure for the Design Example

Table 1. Triple-Speed Ethernet Intel FPGA IP Testbench File Description

Directory/File	Description

Testbench and Simulation Files

/example_testbench/ basic_avl_tb_top_mac_pcs.sv| Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. **Testbench Scripts** /example_testbench/ run_vsim_mac_pcs.sh| The ModelSim script to run the testbench. ** _continued…_** **Directory/File**| **Description** ---|--- /example_testbench/ run_vcs_mac_pcs.sh| The Synopsys* VCS script to run the testbench. /example_testbench/ run_vcsmx_mac_pcs.sh| The Synopsys VCS MX script (combined Verilog HDL and System Verilog with VHDL) to run the testbench /example_testbench/ run_xcelium_mac_pcs.sh| The Xcelium* script to run the testbench.

Table 2. Triple-Speed Ethernet Intel FPGA IP Hardware Design Example File Description

Directory/File	Description
/hardware_test_design/ altera_eth_tse_hw.qpf	Intel

Quartus Prime project file.

/hardware_test_design/ altera_eth_tse_hw.qsf| Intel Quartus Prime project settings file. /hardware_test_design/ altera_eth_tse_hw.sdc| Synopsys Design Constraints files. You can copy and modify these files for your own Intel Stratix® 10 design. /hardware_test_design/ altera_eth_tse_hw.v| Top-level Verilog HDL design example file. /hardware_test_design/ common/| Hardware design example support files.

Generating the Design Example

Procedure to Generate Design Example

Example Design Tab in the Triple-Speed Ethernet Intel FPGA IP Parameter Editor

Follow these steps to generate the hardware design example and testbench:

In the Intel Quartus Prime Pro Edition software, click File ➤ New Project Wizard to create a new Quartus Prime project, or File ➤ Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
Select Intel Agilex device family and select a device that has LVDS.
Click Finish to close the wizard.
In the IP Catalog, locate and select Interface Protocol ➤ Ethernet ➤ 1G Multirate
Ethernet ➤ Triple-Speed Ethernet Intel FPGA IP. The New IP Variation window appears.
Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named .ip.
Click OK. The parameter editors appears.
To generate a design example, select a design example preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design. The parameter editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab.
For Example Design Files, select the Simulation option to generate the testbench, or the Synthesis option to generate the hardware design example.
Note: You must select at least one of the options to generate the design example.
On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL.
Under Target Development Kit, select the Agilex I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VR0) or select None
Click the Example Design: “example_design” button. The Select Example Design Directory window appears.
If you want to modify the design example directory path or name from the defaults displayed (eth_tse_0_example_design), browse to the new path and type the new design example directory name ().
Click OK.

Design Example Parameters

Parameters in the Example Design Tab

Parameter	Description
Select Design	Available example designs for the IP parameter settings.
Example Design Files	The files to generate for the different

development phase.

• Simulation—generates the necessary files for simulating the example design.

• Synthesis—generates the synthesis files. Use these files to compile the design in the Intel Quartus Prime Pro Edition software for hardware testing and perform static timing analysis.

Generate File Format| The format of the RTL files for simulation—Verilog or VHDL.
Select Board| Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is not available, there is no supported board for the options that you select.

Agilex I-Series Transceiver-SoC Development Kit : This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel FPGA IP development kit. If your board revision has a different device grade, you can change the target device.

None : This option excludes the hardware aspects for the design example.

**Simulating the Triple-Speed Ethernet Intel FPGA IP Design Example

Testbench**

Procedure to Simulate Example Testbench

Follow these steps to simulate the testbench:

Change to the testbench simulation directory / example_testbench.
Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.

Steps to Simulate the Testbench

Simulator	Instructions
ModelSim*	In the command line, type vsim -do run_vsim_mac_pcs.do. If you

prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim_mac_pcs.do.
Synopsys VCS*/ VCS MX| In the command line, type sh run_vcs_mac_pcs.sh or sh run_vcsmx_mac_pcs.sh.
Xcelium| In the command line, type sh run_xcelium_mac_pcs.sh.

Analyze the results. The successful testbench sends ten packets, receives the same number of packets, and displays the following message

Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel Agilex device, follow these steps:

Ensure hardware design example generation is complete.
In the Intel Quartus Prime Pro Edition software, open the Intel Quartus Prime project /hardware_test_design/ altera_eth_tse_hw.qpf.
On the Processing menu, click Start Compilation.
After a successful compilation, a.sof file is available in /hardwarde_test_design directory

10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA

This design example demonstrates an Ethernet solution for Intel Agilex devices using the Triple-Speed Ethernet IP. You can generate the design from the Example Design tab of the Triple-Speed Ethernet IP parameter editor. To generate the design example, you must first set the parameter values for the IP variation you intend to generate in your end product. Generating the design example creates a copy of the IP. The testbench and hardware design example use the copy of the IP as the device under test (DUT). If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP variation that you intend.

Features

Generates the design example for Triple-Speed Ethernet Multiport Ethernet MAC without Internal FIFO and PCS with LVDS I/O using multi-channel shared FIFO.
Generates traffic at the transmit path and validates received data through the transceiver LVDS I/O external loopback.
Tx and RX serial external loopback mode through LVDS I/O.
Supports only external loopback.
Supports only four ports.

Hardware and Software Requirements

Intel uses the following hardware and software to test the design example in a Linux system:
Intel Quartus Prime Pro Edition software
ModelSim, VCS, VCS MX, and Xcelium simulators

Functional Description

intel Triple-Speed Ethernet Agilex FPGA IP Design
Example - 6

Design Components

Component	Description
Triple-Speed Ethernet Intel FPGA IP	The Triple-Speed Ethernet Intel FPGA IP

(altera_eth_tse) is instantiated with the following configuration:

• Core Configurations:

— Core Variation : 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS

— Use internal FIFO : Not selected

— Number of ports : 4

— Transceiver type : LVDS I/O

• MAC Options:

— Enable MAC 10/100 half duplex support : Selected

— Enable local loopback on MII/GMII : Selected

— Enable supplemental MAC unicast addresses : Not selected

— Include statistics counters : Selected

— Enable 64-bit statistics byte counters : Not selected

— Include multicast hashtable : Not selected

— Align packet headers to 32-bit boundary : Not selected

— Enable full-duplex flow control : Selected

— Enable VLAN detection : Not selected

— Enable magic packet detection : Selected

— Include MDIO module (MDC/MDIO) : Selected

— Host clock divisor : 50

• Timestamp Options:

— Enable timestamping : Not selected

• PCS/Transceiver Options:

— Enable SGMII bridge : Selected

Client Logic| Generates and monitors packets sent or received through the IP.
Ethernet Traffic Controller| Controlled via Avalon® memory-mapped interface.
JTAG to Avalon memory- mapped interface Address Decoder| Convert JTAG Signals for Avalon memory-mapped interface.

Clock and Reset Signals