intel AN 805 Hierarchical Partial Reconfiguration of a Design on Arria 10 SoC Development Board User Guide

intel AN 805 Hierarchical Partial Reconfiguration of a Design on Arria 10

SoC Development Board

Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC

Development Board

This application note demonstrates transforming a simple design into a hierarchically partially reconfigurable design, and implementing the design on the Intel® Arria® 10 SoC development board. Hierarchical partial reconfiguration (HPR) is a special type of partial reconfiguration (PR), where you contain a PR region within another PR region. You can create multiple personas for both the child and parent partitions. You nest the child partitions within their parent partitions. Reconfiguring a child partition does not impact operation in the parent or static regions. Reconfiguring a parent partition does not impact the operation in the static region, but replaces the child partitions of the parent region with default child partition personas. This methodology is effective in systems where multiple functions time-share the same FPGA device resources.
Partial reconfiguration provides the following advancements to a flat design:

• Allows run-time design reconfiguration

• Increases scalability of the design

• Reduces system downtime

• Supports dynamic time-multiplexing functions in the design

• Lowers cost and power consumption through efficient use of board space

• Note:
  

• Implementation of this reference design requires basic familiarity with the Intel Quartus® Prime FPGA implementation flow and knowledge of the primary Intel Quartus Prime project files.

Related Information

• Intel Arria 10 SoC Development Kit User Guide
• Partial Reconfiguration Concepts
• Partial Reconfiguration Design Flow
• Partial Reconfiguration Design Recommendations
• Partial Reconfiguration Design Considerations

Reference Design Requirements

This reference design requires the following:

• Intel Quartus Prime Pro Edition software version 17.1 for the design implementation.
• Intel Arria 10 SoC development kit for the FPGA implementation.

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

• Other names and brands may be claimed as the property of others.

Reference Design Overview

• This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
  Figure 1. Flat Reference Design without PR Partitioning

Reference Design Files

The partial reconfiguration tutorial is available in the following location: https://github.com/intel/fpga-partial-reconfig
To download the tutorial:

1. Click Clone or download.
2. Click Download ZIP. Unzip the FPGA-partial-config-master.zip file.
3. Navigate to the tutorials/a10_soc_devkit_blinking_led_hpr sub-folder to access the reference design.

The flat folder consists of the following files:

Table 1. Reference Design Files

This module instantiates the blinking_led sub-partition and the top_counter module.
top_counter.sv| Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module.
blinking_led.sdc| Defines the timing constraints for the project.
continued…
File Name| Description
---|---
blinking_led.SV| In this tutorial, you convert this module into a parent PR partition. The module receives the registered output of the top_counter module, which controls LED[2] and LED[3].
blinking_led.qpf| Intel Quartus Prime project file containing the list of all the revisions in the project.
blinking_led.qsf| Intel Quartus Prime settings file containing the assignments and settings for the project.

Note: The hpr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.

Figure 2. Reference Design Files

Reference Design Walkthrough

The following steps describe the application of partial reconfiguration to a flat design. The tutorial uses the Intel Quartus Prime Pro Edition software for the Intel Arria 10 SoC development board:

• Step 1: Getting Started on page 6
• Step 2: Create a Child Level Sub-module on page 6
• Step 3: Creating Design Partitions on page 7
• Step 4: Allocating Placement and Routing Region for PR Partitions on page 9
• Step 5: Adding the Intel Arria 10 Partial Reconfiguration Controller IP Core on page 10
• Step 6: Defining Personas on page 13
• Step 7: Creating Revisions on page 15
• Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script on page 20
• Step 9: Running the Hierarchical Partial Reconfiguration Flow Script on page 21
• Step 10: Programming the Board on page 22

Step 1: Getting Started

To copy the reference design files to your working environment and compile the blinking_led flat design:

• Create a directory in your working environment, a10_soc_devkit_blinking_led_hpr.
• Copy the downloaded tutorials/a10_soc_devkit_blinking_led_hpr/flat sub-folder to the directory, a10_soc_devkit_blinking_led_hpr.
• In the Intel Quartus Prime Pro Edition software, click File ➤ Open Project and select blinking_led.qpf.
• To compile the flat design, click Processing ➤ Start Compilation.

Step 2: Creating a Child Level Sub-module

To convert this flat design into a hierarchical PR design, you must create a child sub-module (blinking_led_child. SV) that is nested within the parent sub-module (blinking_led.sv).

1. Create a new design file, blinking_led_child.sv, and add the following lines of code to this file: timescale 1 ps / 1 ps `default_nettype none module blinking_led_child ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs
2. Modify the blinking_led.sv file to connect the led_two_on to bit 23 of the counter from the static region, and instantiate the blinking_led_child module. After modifications, your blinking_led.sv file must appear as follows:
3. On modifying all the design files, recompile the project by clicking Processing ➤ Start Compilation

Step 3: Creating Design Partitions

You must create design partitions for each PR region that you want to partially reconfigure. You can create any number of independent partitions or PR regions in your design. This tutorial creates two design partitions for the u_blinking_led_child and u_blinking_led instances.
To create design partitions for hierarchical partial reconfiguration:

1. Right-click the u_blinking_led_child instance in the Project Navigator and click Design Partition ➤ Set as Design Partition. A design partition icon appears next to each instance that is set as a partition.

Figure 3. Creating Design Partitions from Project Navigator

1. To define the partition Type, right-click the u_blinking_led_child instance in the Hierarchy tab, click Design Partition ➤ Reconfigurable. You can only define the partition Type after setting the instance as a partition. The design partition appears on the Assignments View tab of the Design Partitions Window.

Figure 4. Design Partitions Window

1. Edit the partition name in the Design Partitions Window by double-clicking the name. For this reference design, rename the partition name to pr_partition.
   Note: When you create a partition, the Intel Quartus Prime software automatically generates a partition name, based on the instance name and hierarchy path. This default partition name can vary with each instance.

2. Repeat steps 1 and 2 to assign reconfigurable design partitions to the u_blinking_led instance. Rename this partition to pr_parent_partition.
   Verify that the blinking_led.qsf contains the following assignments, corresponding to your reconfigurable design partitions:

Related Information

Create Design Partitions for Partial Reconfiguration

Step 4: Allocating Placement and Routing Region for PR Partitions

When you create the base revision, the PR design flow uses your PR partition region allocation to place the corresponding persona core in the reserved region. To locate and assign the PR region in the device floorplan for your base revision:

1. Right-click the u_blinking_led_child instance in the Project Navigator and click Logic Lock Region ➤ Create New Logic Lock Region. The region appears on the Logic Lock Regions Window.

2. Your placement region must enclose the blinking_led_child logic. Select the placement region by locating the node in Chip Planner. Right-click the u_blinking_led_child region name in the Project Navigator and click Locate Node ➤ Locate in Chip Planner.
   Figure 5. Chip Planner Node Location for blinking_led

3. In the Logic Lock Regions window, specify the placement region coordinates in the Origin column. The origin corresponds to the lower-left corner of the region. For example, to set a placement region with (X1 Y1) coordinates as (69 10), specify the Origin as X69_Y10. The Intel Quartus Prime software automatically calculates the (X2 Y2) coordinates (top-right) for the placement region, based on the height and width you specify.
   Note: This tutorial uses the (X1 Y1) coordinates – (69 10), and a height and width of 20 for the placement region. Define any value for the placement region, provided that the region covers the blinking_led_child logic.

4. Enable the Reserved and Core-Only options.

5. Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.

6. Select Fixed with expansion for the Routing type. Selecting this option automatically assigns an expansion length of 1.
   Note: The routing region must be larger than the placement region, to provide extra flexibility for the Fitter when the engine routes different personas.

7. Repeat steps 1 -6 for the u_blinking_led instance. The parent-level placement Repeat steps 1 -6 for the u_blinking_led instance. The parent-level placement region must fully enclose the corresponding child-level placement and routing regions while allowing sufficient space for the parent-level logic placement. This tutorial uses the (X1 Y1) coordinates – (66 7), a height of 47, and a width of 26 for the placement region of the u_blinking_led instance.

Figure 6.Logic Lock Regions Window

Verify that the blinking_led.qsf contains the following assignments, corresponding to your floorplanning:

Related Information

• Floorplan the Partial Reconfiguration Design
• Incrementally Implementing Partial Reconfiguration

Step 5: Adding the Intel Arria 10 Partial Reconfiguration Controller IP Core

• Use the Intel Arria 10 Partial Reconfiguration Controller IP core to reconfigure the PR partition. This IP core uses JTAG to reconfigure the PR partition. To add the Intel Arria 10 Partial Reconfiguration Controller IP core to your Intel Quartus Prime project:

1. Type Partial Reconfiguration in the IP catalog.
2. To launch the IP Parameter Editor Pro window, select the Intel Arria 10 Partial Reconfiguration Controller IP core from the IP library, and click Add.
3. In the New IP Variant dialog box, type pr_ip as the file name and click Create. Use the default parameterization for pr_ip. Ensure that the Enable JTAG debug mode and Enable freeze interface options are turned on, and Enable Avalon-MM slave interface option is turned off.

Figure 7. Intel Arria 10 Partial Reconfiguration Controller IP Core Parameters

1. Click Finish, and exit the parameter editor without generating the system. Intel Quartus Prime software creates the pr_ip.ip IP variation file, and adds the file to the blinking_led project.

Note:

1. If you are copying the pr_ip.ip file from the hpr folder, manually edit the blinking_led.qsf file to include the following line: set_global_assignment -name IP_FILE pr_ip.ip
2. Place the IP_FILE assignment after the SDC_FILE assignments (jtag.sdc and blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures appropriate constraining of the Partial Reconfiguration IP core.
   Note: To detect the clocks, the SDC file for the PR IP must follow any SDC that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or SDC files used to create these clocks in the QSF file for your Intel Quartus Prime project revision. For more information, refer to Timing Constraints section in the Partial Reconfiguration IP Core User Guide.

Related Information

• Partial Reconfiguration IP Solutions User Guide
  • For information on the Partial Reconfiguration Region Controller IP core.
• Partial Reconfiguration IP Core User Guide
  • For information on the timing constraints.

Updating the Top-Level Design

To update the top.SV file with the PR_IP instance:

1. To add the PR_IP instance to the top-level design, uncomment the following code block at the top.SV file:
2. To force the output ports to logic 1 during reconfiguration, use the freeze control signal output from PR_IP. However, to observe the LED continue blinking from the parent PR partition while PR programming the child partition, the freeze control signal does not turn off the led_two_on. Ensure that the pr_led_two_on is directly
3. To assign an instance of the default parent persona (blinking_led), update the top.SV file with the following block of code:

Figure 8. Partial Reconfiguration IP Core Integration

Step 6: Defining Personas

This reference design defines five separate personas for the parent and child PR partitions. To define and include the personas in your project:

1. Create four SystemVerilog files, blinking_led_child.sv, blinking_led_child_slow.sv, blinking_led_child_empty.sv, and blinking_led_slow.sv in your working directory for the five personas.
   Note: If you create the SystemVerilog files from the Intel Quartus Prime Text Editor, disable the Add file to current project option, when saving the files.

Table 2. Reference Design Personas

`timescale 1 ps / 1 ps

`default_nettype none module blinking_led_child (

// clock

input wire clock,

input wire [31:0] counter,

// Control signals for the LEDs output wire led_three_on

);

localparam COUNTER_TAP = 23; reg led_three_on_r;

assign led_three_on   = led_three_on_r; always_ff @(posedge clock) begin

led_three_on_r   <= counter[COUNTER_TAP]; end

endmodule

continued…
File Name| Description| Code
---|---|---
blinking_led_child_slow.sv| The

LED_THREE

blinks slower

| ****

`timescale 1 ps / 1 ps

`default_nettype none

module blinking_led_child_slow (

// clock

input wire clock,

input wire [31:0] counter,

// Control signals for the LEDs output wire led_three_on

);

localparam COUNTER_TAP = 27; reg led_three_on_r;

assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin

led_three_on_r   <= counter[COUNTER_TAP];

end

endmodule

blinking_led_child_empty.sv| The

LED_THREE

stays ON

| ****

`timescale 1 ps / 1 ps

`default_nettype none

module blinking_led_child_empty (

// clock

input wire clock,

input wire [31:0] counter,

// Control signals for the LEDs output wire led_three_on

);

// LED is active low

assign led_three_on = 1’b0;

endmodule

blinking_led_slow.sv| The LED_TWO

blinks slower.

| ****

`timescale 1 ps / 1 ps

`default_nettype none module blinking_led_slow(

// clock

input wire clock,

input wire [31:0] counter,

// Control signals for the LEDs output wire led_two_on,

output wire led_three_on

);

localparam COUNTER_TAP = 27; reg led_two_on_r;

assign led_two_on    = led_two_on_r;

// The counter:

always_ff @(posedge clock) begin led_two_on_r <= counter[COUNTER_TAP];

end

blinking_led_child u_blinking_led_child(

.led_three_on           (led_three_on),

.counter             (counter),

.clock                  (clock)

Related Information

Step 3: Creating Design Partitions on page 7

Step 7: Creating Revisions

The PR design flow uses the project revisions feature in the Intel Quartus Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision. To compile a PR design, you must create a PR implementation revision and synthesis revision for each persona. In this reference design, in addition to the base revision (blinking_led), the three child-level personas and the two parent-level personas contain five separate synthesis revisions and five separate implementation revisions:
Table 3. Revisions for the Two-Parent Personas and Three-Child Personas

Creating Implementation Revisions

To create the PR implementation revisions:

1. To open the Revisions dialog box, click Project ➤ Revisions.
2. To create a new revision, double-click <>.
3. Specify the Revision name as blinking_led_pr_alpha and select blinking_led for Based on Revision.
4. Disable the Set as current revision option and click OK.
5. Similarly, create blinking_led_pr_bravo, blinking_led_pr_charlie, blinking_led_pr_delta, and blinking_led_pr_emma revisions, based on the blinking_led revision.
   Note: Do not set the above revisions as current revision.

Figure 9. Creating Revisions

Creating Synthesis-Only Revisions

To create synthesis-only revisions for the personas, you must assign the top- level entity and corresponding SystemVerilog file for each of the personas:

1. In the Intel Quartus Prime software, click Project ➤ Revisions.

2. Create blinking_led_default revision based on blinking_led revision. Do not set this revision as current revision.

3. Modify the blinking_led_default.qsf file to include the following assignments:
   set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_child
   set_global_assignment -name SYSTEMVERILOG_FILE

4. Similarly, create blinking_led_child_slow, blinking_led_child_empty, blinking_led_parent, and blinking_led_parent_slow revisions based on blinking_led revision. Do not set these revisions as current revisions.

5. Update the blinking_led_child_slow.qsf, blinking_led_child_empty.qsf, blinking_led_parent.qsf, and blinking_led_parent_slow.qsf files with their corresponding
   TOP_LEVEL_ENTITY and SYSTEMVERILOG_FILE assignments:

6. To avoid synthesis errors, ensure that the synthesis revision files for the child partitions do not contain any design partition, pin assignments, or Logic Lock
   region assignments. Also, the synthesis revision files for the parent partitions must only contain design partition assignments for the corresponding child partitions. Remove these assignments, if any, in the blinking_led_default.qsf, blinking_led_child_slow.qsf, blinking_led_child_empty.qsf, blinking_led_parent.qsf, and blinking_led_parent_slow.pdf files

7. Include the following assignments in blinking_led_parent.qsf and blinking_led_parent_slow.qsf files:

8. Verify that the blinking_led.qpf file contains the following revisions, in no particular order:

• • Note: If you are copying the revision files from hpr folder, manually update the blinking_led.qpf file with the above lines of code.

Specifying Revision Type

You must assign revision type for each of your revisions. There are three revision types:

• Partial Reconfiguration – Base
• Partial Reconfiguration – Persona Synthesis
• Partial Reconfiguration – Persona Implementation
• The following table lists the revision-type assignments for each of the revisions:

Table 4. Revision Types

1. Click Project ➤ Revisions. The Revisions dialog box appears.
2. Select blinking_led in the Revision Name column, and click Set Current.
3. Click Apply. The blinking_led revision opens.
4. To set the revision type for blinking_led, click Assignments ➤ Settings ➤ General.
5. Select the Revision Type as Partial Reconfiguration – Base.
6. Similarly, set the revision types for the other ten revisions, as listed in the above table.

• Note: You must set each revision as the current revision before assigning the revision type. Verify that each .qsf file contains the following assignment:
• Note: Add any Fitter-specific settings that you want to use in the PR implementation compile to the persona implementation revisions. The Fitter-specific settings affect the fit of the persona, but do not affect the imported static region. You can also add any synthesis-specific settings to individual persona synthesis revisions.

Related Information

Create Revisions for Personas

Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script

To generate the hierarchical partial reconfiguration flow script:

1. From the Intel Quartus Prime command shell, create a flow template by running the following command:

2. Intel Quartus Prime generates the a10_hier_partial_reconfig/flow.tcl file.

3. Rename the generated a10_hier_partial_reconfig/setup.tcl.example to a10_hier_partial_reconfig/setup.tcl, and modify the script to specify your partial reconfiguration project details:
   a. To define the name of the project, update the following line: b. To define the base revision, update the following line:

4. To define each of the partial reconfiguration implementation revisions, along with the PR partition names and the source revision that implements the revisions, update the following lines:

Note: All the revision projects must be in the same directory as blinking_led.qpf. Otherwise, update the flow script accordingly.

Step 9: Running the Hierarchical Partial Reconfiguration Flow Script

To run the hierarchical partial reconfiguration flow script:

1. Click Tools ➤ Tcl Scripts. The Tcl Scripts dialog box appears.
2. Click Add to Project, browse and select the a10_hier_partial_reconfig/flow.tcl.
3. Select the a10_hier_partial_reconfig/flow.tcl in the Libraries pane, and click Run.
   This script runs the synthesis for the three personas. Intel Quartus Prime generates a SRAM Object File (.sof), a Partial-Masked SRAM Object File (.pmsf), and a Raw Binary File (.rbf) for each of the personas.

Note: To run the script from the Intel Quartus Prime command shell, type the following command:

Related Information

• Compile the Partial Reconfiguration Design
• Using the Partial Reconfiguration Flow Script
• Configuring the Partial Reconfiguration Flow Script
• Generate Programming Files

Step 10: Programming the Board

Before you begin:

1. Connect the power supply to the Intel Arria 10 SoC development board.
2. Connect the USB Blaster cable between your PC USB port and the USB Blaster port on the development board.

To run the design on the Intel Arria 10 SoC development board:

1. Open the Intel Quartus Prime software and click Tools ➤ Programmer.
2. In the Programmer, click Hardware Setup and select USB-Blaster.
3. Click Auto Detect and select the device, 10AS066N3.
4. Click OK. The Intel Quartus Prime software detects and updates the Programmer with the three FPGA chips on the board.
5. Select the 10AS066N3 device, click Change File and load the blinking_led_pr_alpha.sof file.
6. Enable Program/Configure for blinking_led_pr_alpha.sof file.
7. Click Start and wait for the progress bar to reach 100%.
8. Observe the LEDs on the board blinking at the same frequency as the original flat design.
9. To program only the child PR region, right-click the blinking_led_pr_alpha.sof file in the Programmer and click Add PR Programming File.
10. Select the blinking_led_pr_bravo.pr_parent_partition.pr_partition.rbf file.
11. Disable Program/Configure for blinking_led_pr_alpha.sof file.
12. Enable Program/Configure for blinking_led_pr_bravo.pr_parent_partition.pr_partition.rbf file and click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] blinks at the same rate, and LED[3] blinks slower.
13. To program both the parent and child PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
14. Select the blinking_led_pr_delta.pr_parent_partition.rbf file.
15. Click Start. On the board, observe that LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, both LED[2] and LED[3] blink slower.
16. Repeat the above steps to dynamically re-program just the child PR region, or both the parent and child PR regions simultaneously.

Figure 10. Programming the Intel Arria 10 SoC Development Board

Modifying an Existing Persona

• You can change an existing persona, even after fully compiling the base revision.
• For example, to cause the blinking_led_child_slow persona to blink even slower:

1. In the blinking_led_child_slow.sv file, modify the COUNTER_TAP parameter from 27 to 28.
2. To re-synthesize and re-implement this persona, you must recompile all the synthesis-only revisions and implementation revisions affected by the change. Modify the setup.tcl script to include the following lines: Note: When defining the pr_parent_parition for blinking_led_pr_delta revision, you import the final snapshot of that persona for implementation. As a result, the implementation of the parent partition logic remains the same, while modifying and implementing the corresponding child partition. This command re-synthesizes the blinking_led_child_slow synthesis revision, and then runs the PR implementation compile using blinking_led_pr_bravo.
3. To perform compilation of the synthesis-only revisions, run the following command: This command does not recompile the base revision.
4. To perform compilation of the implementation revisions, run the following command:
5. This command does not recompile the base revision.
6. Follow the steps in Step 10: Programming the Board on page 22 to program the resulting RBF file into the FPGA.
   Note: To avoid running the entire flow for every revision, define the synthesis-only revisions and implementation revisions in the setup.tcl script, and run the script.

Adding a New Persona to the Design

After fully compiling your base revisions, you can still add new personas and individually compile these personas.
For example, to define a new child persona for blinking_led_parent_slow, that turns led_three off:

1. Copy blinking_led_child_empty.sv to blinking_led_chdild_off.sv.

2. In the blinking_led_child_off.sv file, modify the assignment, assign led_three_on = 1’b0; to assign led_three_on = 1’b1;. Ensure you change the module name from blinking_led_child_empty to blinking_led_child_off.

3. Create a new synthesis revision, blinking_led_child_off, by following the steps in Creating Synthesis-Only Revisions on page 16.
   Note: The blinking_led_child_off revision must use the blinking_led_child_off.sv file.

4. Create a new implementation revision, blinking_led_pr_foxtrot, by following the steps in Creating Implementation Revisions on page 15.

5. Update the a10_hier_partial_reconfig/setup.tcl file to define the new PR implementation:

6. Compile just this new synthesis and implementation revision by running the following command:

For complete information on hierarchical partial reconfiguration for Intel Arria 10 devices, refer to Creating a Partial Reconfiguration Design in Volume 1 of the Intel Quartus Prime Pro Edition Handbook.

Related Information

• Creating a Partial Reconfiguration Design
• Partial Reconfiguration Online Training

Document Revision History

Table 5. Document Revision History

with the software version

•    Updated the Flat Reference Design without PR Partitioning figure with design block changes

•    Updated the Reference Design Files table with information on the

Top_counter.sv module

•    Updated the Partial Reconfiguration IP Core Integration figure with design block changes

•    Updated the figures – Design Partitions Window and Logic Lock Regions Window to reflect the new GUI

•    File name changes

•    Text edits

2017.05.08| 17.0.0| The initial release of the document

References

• PSG Documentation
• PSG Documentation
• PSG Documentation
• PSG Documentation
• PSG Documentation
• PSG Documentation
• PSG Documentation
• PSG Documentation
• PSG Documentation
• GitHub - intel/fpga-partial-reconfig: Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
• Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10...
• 1. Answers to Top FAQs
• Intel® FPGAs and Programmable Devices-Intel® FPGA
• Intel® FPGAs and Programmable Devices-Intel® FPGA
• Intel® FPGAs and Programmable Devices-Intel® FPGA
• Intel® FPGAs and Programmable Devices-Intel® FPGA
• Intel® FPGAs and Programmable Devices-Intel® FPGA

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