intel FPGA Integer Arithmetic IP Cores User Guide
- June 9, 2024
- Intel
Table of Contents
FPGA Integer Arithmetic IP Cores
Intel FPGA Integer Arithmetic IP Cores User Guide
Updated for Intel® Quartus® Prime Design Suite: 20.3
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ID: 683490 Version: 2020.10.05
Contents
Contents
1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP Core……………………………………………………………………….. 7 2.1.
Features…………………………………………………………………………………………………7 2.2. Verilog HDL
Prototype……………………………………………………………………………….. 8 2.3. VHDL Component
Declaration……………………………………………………………………….8 2.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………… 9 2.5.
Ports……………………………………………………………………………………………………..9 2.6.
Parameters…………………………………………………………………………………………… 10
3. LPM_DIVIDE (Divider) Intel FPGA IP Core………………………………………………………….. 12 3.1.
Features………………………………………………………………………………………………. 12 3.2. Verilog HDL
Prototype……………………………………………………………………………… 12 3.3. VHDL Component
Declaration…………………………………………………………………….. 13 3.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………. 13 3.5.
Ports…………………………………………………………………………………………………… 13 3.6.
Parameters…………………………………………………………………………………………… 14
4. LPM_MULT (Multiplier) IP Core…………………………………………………………………………. 16 4.1.
Features………………………………………………………………………………………………. 16 4.2. Verilog HDL
Prototype……………………………………………………………………………… 17 4.3. VHDL Component
Declaration…………………………………………………………………….. 17 4.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………. 17 4.5.
Signals………………………………………………………………………………………………… 18 4.6. Parameters for Stratix V,
Arria V, Cyclone V, and Intel Cyclone 10 LP Devices…………… 18 4.6.1. General
Tab…………………………………………………………………………………18 4.6.2. General 2
Tab……………………………………………………………………………… 19 4.6.3. Pipelining
Tab……………………………………………………………………………… 19 4.7. Parameters for Intel Stratix 10,
Intel Arria 10, and Intel Cyclone 10 GX Devices……….. 20 4.7.1. General
Tab…………………………………………………………………………………20 4.7.2. General 2
Tab……………………………………………………………………………… 20 4.7.3.
Pipelining……………………………………………………………………………………21
5. LPM_ADD_SUB (Adder/Subtractor)…………………………………………………………………… 22 5.1.
Features………………………………………………………………………………………………. 22 5.2. Verilog HDL
Prototype……………………………………………………………………………… 23 5.3. VHDL Component
Declaration…………………………………………………………………….. 23 5.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………. 23 5.5.
Ports…………………………………………………………………………………………………… 23 5.6.
Parameters…………………………………………………………………………………………… 24
6. LPM_COMPARE (Comparator)…………………………………………………………………………… 26 6.1.
Features………………………………………………………………………………………………. 26 6.2. Verilog HDL
Prototype……………………………………………………………………………… 27 6.3. VHDL Component
Declaration…………………………………………………………………….. 27 6.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………. 27 6.5.
Ports…………………………………………………………………………………………………… 27 6.6.
Parameters…………………………………………………………………………………………… 28
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7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core…………………………………… 30
7.1. ALTECC Encoder Features…………………………………………………………………………..31 7.2. Verilog HDL
Prototype (ALTECC_ENCODER)……………………………………………………. 32 7.3. Verilog HDL Prototype
(ALTECC_DECODER)……………………………………………………. 32 7.4. VHDL Component Declaration
(ALTECC_ENCODER)……………………………………………33 7.5. VHDL Component Declaration
(ALTECC_DECODER)……………………………………………33 7.6. VHDL LIBRARY_USE
Declaration…………………………………………………………………. 33 7.7. Encoder
Ports………………………………………………………………………………………… 33 7.8. Decoder
Ports…………………………………………………………………………………………34 7.9. Encoder
Parameters………………………………………………………………………………… 34 7.10. Decoder Parameters
……………………………………………………………………………… 35
8. Intel FPGA Multiply Adder IP Core……………………………………………………………………. 36
8.1. Features………………………………………………………………………………………………. 37 8.1.1. Pre-
adder………………………………………………………………………………….. 38 8.1.2. Systolic Delay
Register………………………………………………………………….. 40 8.1.3. Pre-load
Constant………………………………………………………………………… 43 8.1.4. Double
Accumulator……………………………………………………………………… 43
8.2. Verilog HDL Prototype……………………………………………………………………………… 44 8.3. VHDL
Component Declaration…………………………………………………………………….. 44 8.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………. 44 8.5.
Signals………………………………………………………………………………………………… 44 8.6.
Parameters…………………………………………………………………………………………… 47
8.6.1. General Tab…………………………………………………………………………………47 8.6.2. Extra Modes
Tab………………………………………………………………………….. 47 8.6.3. Multipliers
Tab…………………………………………………………………………….. 49 8.6.4. Preadder
Tab………………………………………………………………………………. 51 8.6.5. Accumulator
Tab………………………………………………………………………….. 53 8.6.6. Systolic/Chainout
Tab……………………………………………………………………. 55 8.6.7. Pipelining
Tab……………………………………………………………………………… 56
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core……………………
57
9.1. Features………………………………………………………………………………………………. 57 9.2. Verilog HDL
Prototype……………………………………………………………………………… 58 9.3. VHDL Component
Declaration…………………………………………………………………….. 58 9.4.
Ports…………………………………………………………………………………………………… 59 9.5.
Parameters…………………………………………………………………………………………… 59
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core……………………………………………… 61
10.1. Features…………………………………………………………………………………………….. 62 10.2. Verilog HDL
Prototype……………………………………………………………………………..62 10.3. VHDL Component
Declaration…………………………………………………………………… 63 10.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………63 10.5.
Ports…………………………………………………………………………………………………. 63 10.6.
Parameters…………………………………………………………………………………………. 64
11. ALTMULT_ADD (Multiply-Adder) IP Core…………………………………………………………..69
11.1. Features…………………………………………………………………………………………….. 71 11.2. Verilog HDL
Prototype……………………………………………………………………………..72 11.3. VHDL Component
Declaration…………………………………………………………………… 72 11.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………72
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11.5. Ports…………………………………………………………………………………………………. 72 11.6.
Parameters…………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core……………………………………………… 86 12.1.
Complex Multiplication……………………………………………………………………………. 86 12.2. Canonical
Representation………………………………………………………………………… 87 12.3. Conventional
Representation……………………………………………………………………. 87 12.4.
Features…………………………………………………………………………………………….. 88 12.5. Verilog HDL
Prototype……………………………………………………………………………..88 12.6. VHDL Component
Declaration…………………………………………………………………… 89 12.7. VHDL LIBRARY_USE
Declaration…………………………………………………………………89 12.8.
Signals………………………………………………………………………………………………. 89 12.9.
Parameters…………………………………………………………………………………………. 90
13. ALTSQRT (Integer Square Root) IP Core……………………………………………………………92 13.1.
Features…………………………………………………………………………………………….. 92 13.2. Verilog HDL
Prototype……………………………………………………………………………..92 13.3. VHDL Component
Declaration…………………………………………………………………… 93 13.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………93 13.5.
Ports…………………………………………………………………………………………………. 93 13.6.
Parameters…………………………………………………………………………………………. 94
14. PARALLEL_ADD (Parallel Adder) IP Core………………………………………………………….. 95 14.1.
Feature……………………………………………………………………………………………….95 14.2. Verilog HDL
Prototype……………………………………………………………………………..95 14.3. VHDL Component
Declaration…………………………………………………………………… 96 14.4. VHDL LIBRARY_USE
Declaration…………………………………………………………………96 14.5.
Ports…………………………………………………………………………………………………. 96 14.6.
Parameters…………………………………………………………………………………………. 97
15. Integer Arithmetic IP Cores User Guide Document Archives………………………………… 98
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User
Guide…. 99
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1. Intel FPGA Integer Arithmetic IP Cores
You can use the Intel® FPGA integer IP cores to perform mathematical operations in your design.
These functions offer more efficient logic synthesis and device implementation than coding your own functions. You can customize the IP cores to accommodate your design requirements.
Intel integer arithmetic IP cores are divided into the following two categories: · Library of parameterized modules (LPM) IP cores · Intel-specific (ALT) IP cores
The following table lists the integer arithmetic IP cores.
Table 1.
List of IP Cores
IP Cores
LPM IP cores
LPM_COUNTER
LPM_DIVIDE
LPM_MULT
LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP cores ALTECC
Function Overview Counter Divider Multiplier
Adder or subtractor Comparator
ECC Encoder/Decoder
Supported Device
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV
GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV
GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10,
Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV
GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10,
Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V,
Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V,
Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV
GX,
Cyclone V,Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V continued…
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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IP Cores Intel FPGA Multiply Adder or ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD
Function Overview Multiplier-Adder
Memory-based Constant Coefficient Multiplier
Multiplier-Accumulator Multiplier-Adder
Complex Multiplier
Integer Square-Root
Parallel Adder
Supported Device
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime
Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP,
MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX,Intel Cyclone 10 LP, MAX
10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E,
Cyclone IV GX, Cyclone V, Intel
Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV
GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV
GX,
Cyclone V, Intel Cyclone 10 LP,Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Related Information
· Intel FPGAs and Programmable Devices Release Notes
· Introduction to Intel FPGA IP Cores Provides more information about Intel
FPGA IP Cores.
· Floating-Point IP Cores User Guide Provides more information about Intel
FPGA Floating-Point IP cores.
· Introduction to Intel FPGA IP Cores Provides general information about all
Intel FPGA IP cores, including parameterizing, generating, upgrading, and
simulating IP cores.
· Creating Version-Independent IP and Qsys Simulation Scripts Create
simulation scripts that do not require manual updates for software or IP
version upgrades.
· Project Management Best Practices Guidelines for efficient management and
portability of your project and IP files.
· Integer Arithmetic IP Cores User Guide Document Archives on page 98 Provides
a list of user guides for previous versions of the Integer Arithmetic IP
cores.
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2. LPM_COUNTER (Counter) IP Core
Figure 1.
The LPM_COUNTER IP core is a binary counter that creates up counters, down counters and up or down counters with outputs of up to 256 bits wide.
The following figure shows the ports for the LPM_COUNTER IP core.
LPM_COUNTER Ports
LPM_COUNTER
ssclr sload sset data[]
q[]
updown
cout
aclr aload aset
clk_en cnt_en cin
inst
2.1. Features
The LPM_COUNTER IP core offers the following features: · Generates up, down,
and up/down counters · Generates the following counter types:
— Plain binary– the counter increments starting from zero or decrements
starting from 255
— Modulus–the counter increments to or decrements from the modulus value
specified by the user and repeats
· Supports optional synchronous clear, load, and set input ports · Supports
optional asynchronous clear, load, and set input ports · Supports optional
count enable and clock enable input ports · Supports optional carry-in and
carry-out ports
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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2.2. Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v)
lpm.v in the
module lpm_counter ( q, data, clock, cin, cout, clk_en, cnt_en, updown, aset,
aclr, aload, sset, sclr, sload, eq ); parameter lpm_type = “lpm_counter”;
parameter lpm_width = 1; parameter lpm_modulus = 0; parameter lpm_direction =
“UNUSED”; parameter lpm_avalue = “UNUSED”; parameter lpm_svalue = “UNUSED”;
parameter lpm_pvalue = “UNUSED”; parameter lpm_port_updown =
“PORT_CONNECTIVITY”; parameter lpm_hint = “UNUSED”; output [lpm_width-1:0] q;
output cout; output [15:0] eq; input cin; input [lpm_width-1:0] data; input
clock, clk_en, cnt_en, updown; input aset, aclr, aload; input sset, sclr,
sload; endmodule
2.3. VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd)
LPM_PACK.vhd in the
component LPM_COUNTER generic ( LPM_WIDTH : natural; LPM_MODULUS : natural :=
0; LPM_DIRECTION : string := “UNUSED”; LPM_AVALUE : string := “UNUSED”;
LPM_SVALUE : string := “UNUSED”; LPM_PORT_UPDOWN : string :=
“PORT_CONNECTIVITY”; LPM_PVALUE : string := “UNUSED”; LPM_TYPE : string :=
L_COUNTER; LPM_HINT : string := “UNUSED”); port (DATA : in
std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS =>
‘0’); CLOCK : in std_logic ; CLK_EN : in std_logic := ‘1’; CNT_EN : in
std_logic := ‘1’; UPDOWN : in std_logic := ‘1’; SLOAD : in std_logic := ‘0’;
SSET : in std_logic := ‘0’; SCLR : in std_logic := ‘0’; ALOAD : in std_logic
:= ‘0’; ASET : in std_logic := ‘0’; ACLR : in std_logic := ‘0’; CIN : in
std_logic := ‘1’; COUT : out std_logic := ‘0’; Q : out
std_logic_vector(LPM_WIDTH-1 downto 0); EQ : out std_logic_vector(15 downto
0));
end component;
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2.4. VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component
Declaration.
LIBRARY lpm; USE lpm.lpm_components.all;
2.5. Ports
The following tables list the input and output ports for the LPM_COUNTER IP core.
Table 2.
LPM_COUNTER Input Ports
Port Name
Required
Description
data[]
No
Parallel data input to the counter. The size of the input port depends on the LPM_WIDTH parameter value.
clock
Yes
Positive-edge-triggered clock input.
clk_en
No
Clock enable input to enable all synchronous activities. If omitted, the default value is 1.
cnt_en
No
Count enable input to disable the count when asserted low without affecting sload, sset, or sclr. If omitted, the default value is 1.
updown
No
Controls the direction of the count. When asserted high (1), the count direction is up, and when asserted low (0), the count direction is down. If the LPM_DIRECTION parameter is used, the updown port cannot be connected. If LPM_DIRECTION is not used, the updown port is optional. If omitted, the default value is up (1).
cin
No
Carry-in to the low-order bit. For up counters, the behavior of the cin input is
identical to the behavior of the cnt_en input. If omitted, the default value is 1
(VCC).
aclr
No
Asynchronous clear input. If both aset and aclr are used and asserted, aclr overrides aset. If omitted, the default value is 0 (disabled).
aset
No
Asynchronous set input. Specifies the q[] outputs as all 1s, or to the value specified by the LPM_AVALUE parameter. If both the aset and aclr ports are used and asserted, the value of the aclr port overrides the value of the aset port. If omitted, the default value is 0, disabled.
aload
No
Asynchronous load input that asynchronously loads the counter with the value on the data input. When the aload port is used, the data[] port must be connected. If omitted, the default value is 0, disabled.
sclr
No
Synchronous clear input that clears the counter on the next active clock edge. If both the sset and sclr ports are used and asserted, the value of the sclr port overrides the value of the sset port. If omitted, the default value is 0, disabled.
sset
No
Synchronous set input that sets the counter on the next active clock edge.
Specifies the value of the q outputs as all 1s, or to the value specified by
the LPM_SVALUE parameter. If both the sset and sclr ports are used and
asserted,
the value of the sclr port overrides the value of the sset port. If omitted,
the default value is 0 (disabled).
sload
No
Synchronous load input that loads the counter with data[] on the next active clock edge. When the sload port is used, the data[] port must be connected. If omitted, the default value is 0 (disabled).
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Table 3.
LPM_COUNTER Output Ports
Port Name
Required
Description
q[]
No
Data output from the counter. The size of the output port depends on the
LPM_WIDTH parameter value. Either q[] or at least one of the eq[15..0] ports
must be connected.
eq[15..0]
No
Counter decode output. The eq[15..0] port is not accessible in the parameter
editor because the parameter only supports AHDL.
Either the q[] port or eq[] port must be connected. Up to c eq ports can be
used (0 <= c <= 15). Only the 16 lowest count values are decoded. When the
count value is c, the eqc output is asserted high (1). For example, when the
count is 0, eq0 = 1, when the count is 1, eq1 = 1, and when the count is 15,
eq 15 = 1. Decoded output for count values of 16 or greater require external
decoding. The eq[15..0] outputs are asynchronous to the q[] output.
cout
No
Carry-out port of the counter’s MSB bit. It can be used to connect to another counter to create a larger counter.
2.6. Parameters
The following table lists the parameters for the LPM_COUNTER IP core.
Table 4.
LPM_COUNTER Parameters
Parameter Name
Type
LPM_WIDTH
Integer
LPM_DIRECTION
String
LPM_MODULUS LPM_AVALUE
Integer
Integer/ String
LPM_SVALUE LPM_HINT
Integer/ String
String
LPM_TYPE
String
Required Yes No No No
No No
No
Description
Specifies the widths of the data[] and q[] ports, if they are used.
Values are UP, DOWN, and UNUSED. If the LPM_DIRECTION parameter is used, the
updown port cannot be connected. When the updown port is not connected, the
LPM_DIRECTION parameter default value is UP.
The maximum count, plus one. Number of unique states in the counter’s cycle.
If the load value is larger than the LPM_MODULUS parameter, the behavior of
the counter is not specified.
Constant value that is loaded when aset is asserted high. If the value
specified is larger than or equal to
Constant value that is loaded on the rising edge of the clock port when the
sset port is asserted high. Intel recommends that you specify this value as a
decimal number for AHDL designs.
When you instantiate a library of parameterized modules (LPM) function in a
VHDL Design File (.vhd), you must use the LPM_HINT parameter to specify an
Intel-specific parameter. For example: LPM_HINT = “CHAIN_SIZE = 8,
ONE_INPUT_IS_CONSTANT = YES”
The default value is UNUSED.
Identifies the library of parameterized modules (LPM) entity name in VHDL
design files.
continued…
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Parameter Name INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN
Type String String
String
String
Required No No
No
No
Description
This parameter is used for modeling and behavioral simulation purposes. This
parameter is used for modeling and behavioral simulation purposes. The
parameter editor calculates the value for this parameter.
Intel-specific parameter. You must use the LPM_HINT parameter to specify the
CARRY_CNT_EN parameter in VHDL design files. Values are SMART, ON, OFF, and
UNUSED. Enables the LPM_COUNTER function to propagate the cnt_en signal
through the carry chain. In some cases, the CARRY_CNT_EN parameter setting
might have a slight impact on the speed, so you might want to turn it off. The
default value is SMART, which provides the best trade-off between size and
speed.
Intel-specific parameter. You must use the LPM_HINT parameter to specify the
LABWIDE_SCLR parameter in VHDL design files. Values are ON, OFF, or UNUSED.
The default value is ON. Allows you to disable the use of the LABwide sclr
feature found in obsoleted device families. Turning this option off increases
the chances of fully using the partially filled LABs, and thus may allow
higher logic density when SCLR does not apply to a complete LAB. This
parameter is available for backward compatibility, and Intel recommends you
not to use this parameter.
Specifies the usage of the updown input port. If omitted the default value is
PORT_CONNECTIVITY. When the port value is set to PORT_USED, the port is
treated as used. When the port value is set to PORT_UNUSED, the port is
treated as unused. When the port value is set to PORT_CONNECTIVITY, the port
usage is determined by checking the port connectivity.
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3. LPM_DIVIDE (Divider) Intel FPGA IP Core
Figure 2.
The LPM_DIVIDE Intel FPGA IP core implements a divider to divide a numerator input value by a denominator input value to produce a quotient and a remainder.
The following figure shows the ports for the LPM_DIVIDE IP core.
LPM_DIVIDE Ports
LPM_DIVIDE
numer[] denom[] clock
quotient[] remain[]
clken aclr
inst
3.1. Features
The LPM_DIVIDE IP core offers the following features: · Generates a divider
that divides a numerator input value by a denominator input
value to produce a quotient and a remainder. · Supports data width of 1256
bits. · Supports signed and unsigned data representation format for both the
numerator
and denominator values. · Supports area or speed optimization. · Provides an
option to specify a positive remainder output. · Supports pipelining
configurable output latency. · Supports optional asynchronous clear and clock
enable ports.
3.2. Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v)
lpm.v in the
module lpm_divide ( quotient, remain, numer, denom, clock, clken, aclr);
parameter lpm_type = “lpm_divide”; parameter lpm_widthn = 1; parameter
lpm_widthd = 1; parameter lpm_nrepresentation = “UNSIGNED”; parameter
lpm_drepresentation = “UNSIGNED”; parameter lpm_remainderpositive = “TRUE”;
parameter lpm_pipeline = 0;
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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parameter lpm_hint = “UNUSED”; input clock; input clken; input aclr; input [lpm_widthn-1:0] numer; input [lpm_widthd-1:0] denom; output [lpm_widthn-1:0] quotient; output [lpm_widthd-1:0] remain; endmodule
3.3. VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd)
LPM_PACK.vhd in the
component LPM_DIVIDE generic (LPM_WIDTHN : natural; LPM_WIDTHD : natural;
LPM_NREPRESENTATION : string := “UNSIGNED”; LPM_DREPRESENTATION : string :=
“UNSIGNED”; LPM_PIPELINE : natural := 0; LPM_TYPE : string := L_DIVIDE;
LPM_HINT : string := “UNUSED”); port (NUMER : in std_logic_vector(LPM_WIDTHN-1
downto 0); DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0); ACLR : in
std_logic := ‘0’; CLOCK : in std_logic := ‘0’; CLKEN : in std_logic := ‘1’;
QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0); REMAIN : out
std_logic_vector(LPM_WIDTHD-1 downto 0)); end component;
3.4. VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component
Declaration.
LIBRARY lpm; USE lpm.lpm_components.all;
3.5. Ports
The following tables list the input and output ports for the LPM_DIVIDE IP core.
Table 5.
LPM_DIVIDE Input Ports
Port Name
Required
numer[]
Yes
denom[]
Yes
Description
Numerator data input. The size of the input port depends on the LPM_WIDTHN
parameter value.
Denominator data input. The size of the input port depends on the LPM_WIDTHD
parameter value.
continued…
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Port Name clock clken
aclr
Required No No
No
Description
Clock input for pipelined usage. For LPM_PIPELINE values other than 0
(default), the clock port must be enabled.
Clock enable pipelined usage. When the clken port is asserted high, the
division operation takes place. When the signal is low, no operation occurs.
If omitted, the default value is 1.
Asynchronous clear port used at any time to reset the pipeline to all ‘0’s
asynchronously to the clock input.
Table 6.
LPM_DIVIDE Output Ports
Port Name
Required
Description
quotient[]
Yes
Data output. The size of the output port depends on the LPM_WIDTHN
parameter value.
remain[]
Yes
Data output. The size of the output port depends on the LPM_WIDTHD
parameter value.
3.6. Parameters
The following table lists the parameters for the LPM_DIVIDE Intel FPGA IP core.
Parameter Name
Type
Required
Description
LPM_WIDTHN
Integer
Yes
Specifies the widths of the numer[] and
quotient[] ports. Values are 1 to 64.
LPM_WIDTHD
Integer
Yes
Specifies the widths of the denom[] and
remain[] ports. Values are 1 to 64.
LPM_NREPRESENTATION LPM_DREPRESENTATION
String String
No
Sign representation of the numerator input.
Values are SIGNED and UNSIGNED. When this
parameter is set to SIGNED, the divider
interprets the numer[] input as signed two’s
complement.
No
Sign representation of the denominator input.
Values are SIGNED and UNSIGNED. When this
parameter is set to SIGNED, the divider
interprets the denom[] input as signed two’s
complement.
LPM_TYPE
String
No
Identifies the library of parameterized
modules (LPM) entity name in VHDL design
files (.vhd).
LPM_HINT
String
No
When you instantiate a library of
parameterized modules (LPM) function in a
VHDL Design File (.vhd), you must use the
LPM_HINT parameter to specify an Intel-
specific parameter. For example: LPM_HINT
= “CHAIN_SIZE = 8,
ONE_INPUT_IS_CONSTANT = YES” The
default value is UNUSED.
LPM_REMAINDERPOSITIVE
String
No
Intel-specific parameter. You must use the
LPM_HINT parameter to specify the
LPM_REMAINDERPOSITIVE parameter in
VHDL design files. Values are TRUE or FALSE.
If this parameter is set to TRUE, then the
value of the remain[] port must be greater
continued…
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Parameter Name
Type
MAXIMIZE_SPEED
Integer
LPM_PIPELINE
Integer
INTENDED_DEVICE_FAMILY SKIP_BITS
String Integer
Required No
No No No
Description
than or equal to zero. If this parameter is set to TRUE, then the value of the
remain[] port is either zero, or the value is the same sign, either positive
or negative, as the value of the numer port. In order to reduce area and
improve speed, Intel recommends setting this parameter to TRUE in operations
where the remainder must be positive or where the remainder is unimportant.
Intel-specific parameter. You must use the LPM_HINT parameter to specify the
MAXIMIZE_SPEED parameter in VHDL design files. Values are [0..9]. If used, the
Intel Quartus Prime software attempts to optimize a specific instance of the
LPM_DIVIDE function for speed rather than routability, and overrides the
setting of the Optimization Technique logic option. If MAXIMIZE_SPEED is
unused, the value of the Optimization Technique option is used instead. If the
value of MAXIMIZE_SPEED is 6 or higher, the Compiler optimizes the LPM_DIVIDE
IP core for higher speed by using carry chains; if the value is 5 or less, the
compiler implements the design without carry chains.
Specifies the number of clock cycles of latency associated with the quotient[]
and remain[] outputs. A value of zero (0) indicates that no latency exists,
and that a purely combinational function is instantiated. If omitted, the
default value is 0 (nonpipelined). You cannot specify a value for the
LPM_PIPELINE parameter that is higher than LPM_WIDTHN.
This parameter is used for modeling and behavioral simulation purposes. The
parameter editor calculates the value for this parameter.
Allows for more efficient fractional bit division to optimize logic on the
leading bits by providing the number of leading GND to the LPM_DIVIDE IP core.
Specify the number of leading GND on the quotient output to this parameter.
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4. LPM_MULT (Multiplier) IP Core
Figure 3.
The LPM_MULT IP core implements a multiplier to multiply two input data values to produce a product as an output.
The following figure shows the ports for the LPM_MULT IP core.
LPM_Mult Ports
LPM_MULT clock dataa[] result[] datab[] aclr/sclr clken
inst
Related Information Features on page 71
4.1. Features
The LPM_MULT IP core offers the following features: · Generates a multiplier
that multiplies two input data values · Supports data width of 1256 bits ·
Supports signed and unsigned data representation format · Supports area or
speed optimization · Supports pipelining with configurable output latency ·
Provides an option for implementation in dedicated digital signal processing
(DSP)
block circuitry or logic elements (LEs) Note: When building multipliers larger
than the natively supported size there may/
will be a performance impact resulting from the cascading of the DSP blocks. ·
Supports optional asynchronous clear and clock enable input ports · Supports
optional synchronous clear for Intel Stratix 10, Intel Arria 10 and Intel
Cyclone 10 GX devices
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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4.2. Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v)
lpm.v in the
module lpm_mult ( result, dataa, datab, sum, clock, clken, aclr ) parameter
lpm_type = “lpm_mult”; parameter lpm_widtha = 1; parameter lpm_widthb = 1;
parameter lpm_widths = 1; parameter lpm_widthp = 1; parameter
lpm_representation = “UNSIGNED”; parameter lpm_pipeline = 0; parameter
lpm_hint = “UNUSED”; input clock; input clken; input aclr; input
[lpm_widtha-1:0] dataa; input [lpm_widthb-1:0] datab; input [lpm_widths-1:0]
sum; output [lpm_widthp-1:0] result; endmodule
4.3. VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd)
LPM_PACK.vhd in the
component LPM_MULT generic ( LPM_WIDTHA : natural; LPM_WIDTHB : natural;
LPM_WIDTHS : natural := 1; LPM_WIDTHP : natural;
LPM_REPRESENTATION : string := “UNSIGNED”; LPM_PIPELINE : natural := 0;
LPM_TYPE: string := L_MULT; LPM_HINT : string := “UNUSED”); port ( DATAA : in
std_logic_vector(LPM_WIDTHA-1 downto 0); DATAB : in
std_logic_vector(LPM_WIDTHB-1 downto 0); ACLR : in std_logic := ‘0’; CLOCK :
in std_logic := ‘0’; CLKEN : in std_logic := ‘1’; SUM : in
std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => ‘0’); RESULT : out
std_logic_vector(LPM_WIDTHP-1 downto 0)); end component;
4.4. VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component
Declaration.
LIBRARY lpm; USE lpm.lpm_components.all;
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4.5. Signals
Table 7.
LPM_MULT Input Signals
Signal Name
Required
Description
dataa[]
Yes
Data input.
For Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices, the size of the input signal depends on the Dataa width parameter value.
For older and Intel Cyclone 10 LP devices, the size of the input signal depends on the LPM_WIDTHA parameter value.
datab[]
Yes
Data input.
For Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices, the size of the input signal depends on the Datab width parameter value.
For older and Intel Cyclone 10 LP devices, the size of the input signal depends
on the LPM_WIDTHB parameter value.
clock
No
Clock input for pipelined usage.
For older and Intel Cyclone 10 LP devices, the clock signal must be enabled for LPM_PIPELINE values other than 0 (default).
For Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices, the clock signal must be enabled if Latency value is other than 1 (default).
clken
No
Clock enable for pipelined usage. When the clken signal is asserted high, the
adder/subtractor operation takes place. When the signal is low, no operation
occurs. If omitted, the default value is 1.
aclr sclr
No
Asynchronous clear signal used at any time to reset the pipeline to all 0s,
asynchronously to the clock signal. The pipeline initializes to an undefined (X)
logic level. The outputs are a consistent, but non-zero value.
No
Synchronous clear signal used at any time to reset the pipeline to all 0s,
synchronously to the clock signal. The pipeline initializes to an undefined (X)
logic level. The outputs are a consistent, but non-zero value.
Table 8.
LPM_MULT Output signals
signal Name
Required
Description
result[]
Yes
Data output.
For older and Intel Cyclone 10 LP devices, the size of the output signal depends on the LPM_WIDTHP parameter value. If LPM_WIDTHP < max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) or (LPM_WIDTHA + LPM_WIDTHS), only the LPM_WIDTHP MSBs are present.
For Intel Stratix 10, Intel Arria 10 and Intel Cyclone 10 GX, the size of the output signals depends on the Result width parameter.
4.6. Parameters for Stratix V, Arria V, Cyclone V, and Intel Cyclone 10 LP Devices
4.6.1. General Tab
Table 9.
General Tab
Parameter
Value
Multiplier Configuration
Multiply ‘dataa’ input by ‘datab’ input
Default Value
Description
Multiply ‘dataa’ input by ‘datab’ input
Select the desired configuration for the multiplier.
continued…
Intel FPGA Integer Arithmetic IP Cores User Guide 18
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Parameter
How wide should the ‘dataa’ input be? How wide should the ‘datab’ input be?
How should the width of the ‘result’ output be determined? Restrict the width
Value
Multiply ‘dataa’ input by itself (squaring operation)
1 – 256 bits
Default Value
Description
8 bits
Specify the width of the dataa[] port.
1 – 256 bits
8 bits
Specify the width of the datab[] port.
Automatically calculate the width Restrict the width
1 – 512 bits
Automaticall y calculate the width
Select the desired method to determine the width of the result[] port.
16 bits
Specify the width of the result[] port.
This value will only be effective if you select Restrict the width in the Type
parameter.
4.6.2. General 2 Tab
Table 10. General 2 Tab
Parameter
Value
Datab Input
Does the ‘datab’ input bus have a constant value?
No Yes
Multiplication Type
Which type of
Unsigned
multiplication do you want? Signed
Implementation
Which multiplier implementation should be used?
Use the default implementation
Use the dedicated multiplier circuitry (Not available for all families)
Use logic elements
Default Value
Description
No
Select Yes to specify the constant value of the
`datab’ input bus, if any.
Unsigned
Specify the representation format for both dataa[] and datab[] inputs.
Use the default implementat ion
Select the desired method to determine the width of the result[] port.
4.6.3. Pipelining Tab
Table 11. Pipelining Tab
Parameter
Do you want to pipeline the No
function?
Yes
Value
Create an ‘aclr’
—
asynchronous clear port
Default Value
Description
No
Select Yes to enable pipeline register to the
multiplier’s output and specify the desired
output latency in clock cycle. Enabling the
pipeline register adds extra latency to the
output.
Unchecked
Select this option to enable aclr port to use asynchronous clear for the
pipeline register.
continued…
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Parameter
Create a ‘clken’ clock enable clock
Optimization
What type of optimization do you want?
Value —
Default Speed Area
Default Value
Description
Unchecked
Specifies active high clock enable for the clock port of the pipeline register
Default
Specify the desired optimization for the IP core.
Select Default to let Intel Quartus Prime software to determine the best
optimization for the IP core.
4.7. Parameters for Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX Devices
4.7.1. General Tab
Table 12. General Tab
Parameter
Value
Default Value
Description
Multiplier Configuration Type
Data Port Widths
Multiply ‘dataa’ input by ‘datab’ input
Multiply ‘dataa’ input by itself (squaring operation)
Multiply ‘dataa’ input by ‘datab’ input
Select the desired configuration for the multiplier.
Dataa width
1 – 256 bits
8 bits
Specify the width of the dataa[] port.
Datab width
1 – 256 bits
8 bits
Specify the width of the datab[] port.
How should the width of the ‘result’ output be determined?
Type
Automatically calculate the width
Restrict the width
Automaticall y calculate the width
Select the desired method to determine the width of the result[] port.
Value
1 – 512 bits
16 bits
Specify the width of the result[] port.
This value will only be effective if you select Restrict the width in the Type
parameter.
Result width
1 – 512 bits
—
Displays the effective width of the result[] port.
4.7.2. General 2 Tab
Table 13. General 2 Tab
Parameter
Datab Input
Does the ‘datab’ input bus have a constant value?
No Yes
Value
Default Value
Description
No
Select Yes to specify the constant value of the
`datab’ input bus, if any.
continued…
Intel FPGA Integer Arithmetic IP Cores User Guide 20
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Parameter
Value
Value
Any value greater than 0
Multiplication Type
Which type of
Unsigned
multiplication do you want? Signed
Implementation Style
Which multiplier implementation should be used?
Use the default implementation
Use the dedicated multiplier circuitry
Use logic elements
Default Value
Description
0
Specify the constant value of datab[] port.
Unsigned
Specify the representation format for both dataa[] and datab[] inputs.
Use the default implementat ion
Select the desired method to determine the width of the result[] port.
4.7.3. Pipelining
Table 14. Pipelining Tab
Parameter
Value
Do you want to pipeline the function?
Pipeline
No Yes
Latency Clear Signal Type
Any value greater than 0.
NONE ACLR SCLR
Create a ‘clken’ clock
—
enable clock
What type of optimization do you want?
Type
Default Speed Area
Default Value
Description
No 1 NONE
—
Select Yes to enable pipeline register to the multiplier’s output. Enabling
the pipeline register adds extra latency to the output.
Specify the desired output latency in clock cycle.
Specify the type of reset for the pipeline register. Select NONE if you do not
use any pipeline register. Select ACLR to use asynchronous clear for the
pipeline register. This will generate ACLR port. Select SCLR to use
synchronous clear for the pipeline register. This will generate SCLR port.
Specifies active high clock enable for the clock port of the pipeline register
Default
Specify the desired optimization for the IP core.
Select Default to let Intel Quartus Prime software to determine the best
optiomization for the IP core.
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5. LPM_ADD_SUB (Adder/Subtractor)
Figure 4.
The LPM_ADD_SUB IP core lets you implement an adder or a subtractor to add or subtract sets of data to produce an output containing the sum or difference of the input values.
The following figure shows the ports for the LPM_ADD_SUB IP core.
LPM_ADD_SUB Ports
LPM_ADD_SUB add_sub cin
dataa[]
clock clken datab[] aclr
result[] overflow cout
inst
5.1. Features
The LPM_ADD_SUB IP core offers the following features: · Generates adder,
subtractor, and dynamically configurable adder/subtractor
functions. · Supports data width of 1256 bits. · Supports data representation
format such as signed and unsigned. · Supports optional carry-in (borrow-out),
asynchronous clear, and clock enable
input ports. · Supports optional carry-out (borrow-in) and overflow output
ports. · Assigns either one of the input data buses to a constant. · Supports
pipelining with configurable output latency.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v)
lpm.v in the
module lpm_add_sub ( result, cout, overflow,add_sub, cin, dataa, datab, clock,
clken, aclr ); parameter lpm_type = “lpm_add_sub”; parameter lpm_width = 1;
parameter lpm_direction = “UNUSED”; parameter lpm_representation = “SIGNED”;
parameter lpm_pipeline = 0; parameter lpm_hint = “UNUSED”; input
[lpm_width-1:0] dataa, datab; input add_sub, cin; input clock; input clken;
input aclr; output [lpm_width-1:0] result; output cout, overflow; endmodule
5.3. VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd)
LPM_PACK.vhd in the
component LPM_ADD_SUB generic (LPM_WIDTH : natural;
LPM_DIRECTION : string := “UNUSED”; LPM_REPRESENTATION: string := “SIGNED”;
LPM_PIPELINE : natural := 0; LPM_TYPE : string := L_ADD_SUB; LPM_HINT : string
:= “UNUSED”); port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0); DATAB :
in std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := ‘0’; CLOCK :
in std_logic := ‘0’; CLKEN : in std_logic := ‘1’; CIN : in std_logic := ‘Z’;
ADD_SUB : in std_logic := ‘1’; RESULT : out std_logic_vector(LPM_WIDTH-1
downto 0); COUT : out std_logic; OVERFLOW : out std_logic); end component;
5.4. VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component
Declaration.
LIBRARY lpm; USE lpm.lpm_components.all;
5.5. Ports
The following tables list the input and output ports for the LPM_ADD_SUB IP
core.
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Table 15. LPM_ADD_SUB IP Core Input Ports
Port Name
Required
Description
cin
No
Carry-in to the low-order bit. For addition operations, the default value is 0. For
subtraction operations, the default value is 1.
dataa[]
Yes
Data input. The size of the input port depends on the LPM_WIDTH parameter value.
datab[]
Yes
Data input. The size of the input port depends on the LPM_WIDTH parameter value.
add_sub
No
Optional input port to enable dynamic switching between the adder and subtractor
functions. If the LPM_DIRECTION parameter is used, add_sub cannot be used. If
omitted, the default value is ADD. Intel recommends that you use the
LPM_DIRECTION parameter to specify the operation of the LPM_ADD_SUB function,
rather than assigning a constant to the add_sub port.
clock
No
Input for pipelined usage. The clock port provides the clock input for a pipelined
operation. For LPM_PIPELINE values other than 0 (default), the clock port must be
enabled.
clken
No
Clock enable for pipelined usage. When the clken port is asserted high, the adder/
subtractor operation takes place. When the signal is low, no operation occurs. If
omitted, the default value is 1.
aclr
No
Asynchronous clear for pipelined usage. The pipeline initializes to an undefined (X)
logic level. The aclr port can be used at any time to reset the pipeline to all 0s,
asynchronously to the clock signal.
Table 16. LPM_ADD_SUB IP Core Output Ports
Port Name
Required
Description
result[]
Yes
Data output. The size of the output port depends on the LPM_WIDTH parameter
value.
cout
No
Carry-out (borrow-in) of the most significant bit (MSB). The cout port has a physical
interpretation as the carry-out (borrow-in) of the MSB. The cout port detects
overflow in UNSIGNED operations. The cout port operates in the same manner for
SIGNED and UNSIGNED operations.
overflow
No
Optional overflow exception output. The overflow port has a physical interpretation as
the XOR of the carry-in to the MSB with the carry-out of the MSB. The overflow port
asserts when results exceed the available precision, and is used only when the
LPM_REPRESENTATION parameter value is SIGNED.
5.6. Parameters
The following table lists the LPM_ADD_SUB IP core parameters.
Table 17. LPM_ADD_SUB IP Core Parameters
Parameter Name LPM_WIDTH
Type Integer
Required Yes
Description
Specifies the widths of the dataa[], datab[], and result[] ports.
LPM_DIRECTION
String
No
Values are ADD, SUB, and UNUSED. If omitted, the default value is DEFAULT,
which directs the parameter to take its value from the add_sub port. The
add_sub port cannot be used if LPM_DIRECTION is used. Intel recommends that
you use the LPM_DIRECTION parameter to specify the operation of the
LPM_ADD_SUB function, rather than assigning a constant to the add_sub port.
continued…
Intel FPGA Integer Arithmetic IP Cores User Guide 24
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Parameter Name LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE
ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY
Type String Integer String String String Integer
String
Required No No No No No No
No
Description
Specifies the type of addition performed. Values are SIGNED and UNSIGNED. If
omitted, the default value is SIGNED. When this parameter is set to SIGNED,
the adder/subtractor interprets the data input as signed two’s complement.
Specifies the number of latency clock cycles associated with the result[]
output. A value of zero (0) indicates that no latency exists, and that a
purely combinational function will be instantiated. If omitted, the default
value is 0 (non-pipelined).
Allows you to specify Intel-specific parameters in VHDL design files (.vhd).
The default value is UNUSED.
Identifies the library of parameterized modules (LPM) entity name in VHDL
design files.
Intel-specific parameter. You must use the LPM_HINT parameter to specify the
ONE_INPUT_IS_CONSTANT parameter in VHDL design files. Values are YES, NO, and
UNUSED. Provides greater optimization if one input is constant. If omitted,
the default value is NO.
Intel-specific parameter. You must use the LPM_HINT parameter to specify the
MAXIMIZE_SPEED parameter in VHDL design files. You can specify a value between
0 and 10. If used, the Intel Quartus Prime software attempts to optimize a
specific instance of the LPM_ADD_SUB function for speed rather than
routability, and overrides the setting of the Optimization Technique logic
option. If MAXIMIZE_SPEED is unused, the value of the Optimization Technique
option is used instead. If the setting for MAXIMIZE_SPEED is 6 or higher, the
Compiler optimizes the LPM_ADD_SUB IP core for higher speed using carry
chains; if the setting is 5 or less, the Compiler implements the design
without carry chains. This parameter must be specified for Cyclone, Stratix,
and Stratix GX devices only when the add_sub port is not used.
This parameter is used for modeling and behavioral simulation purposes. The
parameter editor calculates the value for this parameter.
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6. LPM_COMPARE (Comparator)
Figure 5.
The LPM_COMPARE IP core compares the value of two sets of data to determine the relationship between them. In its simplest form, you can use an exclusive- OR gate to determine whether two bits of data are equal.
The following figure shows the ports for the LPM_COMPARE IP core.
LPM_COMPARE Ports
LPM_COMPARE
clken
alb
aeb
dataa[]
agb
datab[]
ageb
clock
aneb
aclr
aleb
inst
6.1. Features
The LPM_COMPARE IP core offers the following features: · Generates a
comparator function to compare two sets of data · Supports data width of 1256
bits · Supports data representation format such as signed and unsigned ·
Produces the following output types:
— alb (input A is less than input B) — aeb (input A is equal to input B) — agb
(input A is greater than input B) — ageb (input A is greater than or equal to
input B) — aneb (input A is not equal to input B) — aleb (input A is less than
or equal to input B) · Supports optional asynchronous clear and clock enable
input ports · Assigns the datab[] input to a constant · Supports pipelining
with configurable output latency
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
6.2. Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v)
lpm.v in the
module lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, clock,
clken, aclr ); parameter lpm_type = “lpm_compare”; parameter lpm_width = 1;
parameter lpm_representation = “UNSIGNED”; parameter lpm_pipeline = 0;
parameter lpm_hint = “UNUSED”; input [lpm_width-1:0] dataa, datab; input
clock; input clken; input aclr; output alb, aeb, agb, aleb, aneb, ageb;
endmodule
6.3. VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd)
LPM_PACK.vhd in the
component LPM_COMPARE generic (LPM_WIDTH : natural;
LPM_REPRESENTATION : string := “UNSIGNED”; LPM_PIPELINE : natural := 0;
LPM_TYPE: string := L_COMPARE; LPM_HINT : string := “UNUSED”); port (DATAA :
in std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : in
std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := ‘0’; CLOCK : in
std_logic := ‘0’; CLKEN : in std_logic := ‘1’; AGB : out std_logic; AGEB : out
std_logic; AEB : out std_logic; ANEB : out std_logic; ALB : out std_logic;
ALEB : out std_logic); end component;
6.4. VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component
Declaration.
LIBRARY lpm; USE lpm.lpm_components.all;
6.5. Ports
The following tables list the input and output ports for the LMP_COMPARE IP
core.
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Table 18. LPM_COMPARE IP core Input Ports
Port Name
Required
Description
dataa[]
Yes
Data input. The size of the input port depends on the LPM_WIDTH parameter value.
datab[]
Yes
Data input. The size of the input port depends on the LPM_WIDTH parameter value.
clock
No
Clock input for pipelined usage. The clock port provides the clock input for a pipelined
operation. For LPM_PIPELINE values other than 0 (default), the clock port must be
enabled.
clken
No
Clock enable for pipelined usage. When the clken port is asserted high, the
comparison operation takes place. When the signal is low, no operation occurs. If
omitted, the default value is 1.
aclr
No
Asynchronous clear for pipelined usage. The pipeline initializes to an undefined (X) logic
level. The aclr port can be used at any time to reset the pipeline to all 0s,
asynchronously to the clock signal.
Table 19. LPM_COMPARE IP core Output Ports
Port Name
Required
Description
alb
No
Output port for the comparator. Asserted if input A is less than input B.
aeb
No
Output port for the comparator. Asserted if input A is equal to input B.
agb
No
Output port for the comparator. Asserted if input A is greater than input B.
ageb
No
Output port for the comparator. Asserted if input A is greater than or equal to input
B.
aneb
No
Output port for the comparator. Asserted if input A is not equal to input B.
aleb
No
Output port for the comparator. Asserted if input A is less than or equal to input B.
6.6. Parameters
The following table lists the parameters for the LPM_COMPARE IP core.
Table 20. LPM_COMPARE IP core Parameters
Parameter Name
Type
Required
LPM_WIDTH
Integer Yes
LPM_REPRESENTATION
String
No
LPM_PIPELINE
Integer No
LPM_HINT
String
No
Description
Specifies the widths of the dataa[] and datab[] ports.
Specifies the type of comparison performed. Values are SIGNED and UNSIGNED. If
omitted, the default value is UNSIGNED. When this parameter value is set to
SIGNED, the comparator interprets the data input as signed two’s complement.
Specifies the number of clock cycles of latency associated with the alb, aeb,
agb, ageb, aleb, or aneb output. A value of zero (0) indicates that no latency
exists, and that a purely combinational function will be instantiated. If
omitted, the default value is 0 (nonpipelined).
Allows you to specify Intel-specific parameters in VHDL design files (.vhd).
The default value is UNUSED.
continued…
Intel FPGA Integer Arithmetic IP Cores User Guide 28
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Parameter Name LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT
Type String String
String
Required No No
No
Description
Identifies the library of parameterized modules (LPM) entity name in VHDL
design files.
This parameter is used for modeling and behavioral simulation purposes. The
parameter editor calculates the value for this parameter.
Intel-specific parameter. You must use the LPM_HINT parameter to specify the
ONE_INPUT_IS_CONSTANT parameter in VHDL design files. Values are YES, NO, or
UNUSED. Provides greater optimization if an input is constant. If omitted, the
default value is NO.
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7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
Figure 6.
Intel provides the ALTECC IP core to implement the ECC functionality. ECC detects corrupted data that occurs at the receiver side during data transmission. This error correction method is best suited for situations where errors occur at random rather than in bursts.
The ECC detects errors through the process of data encoding and decoding. For example, when the ECC is applied in a transmission application, data read from the source are encoded before being sent to the receiver. The output (code word) from the encoder consists of the raw data appended with the number of parity bits. The exact number of parity bits appended depends on the number of bits in the input data. The generated code word is then transmitted to the destination.
The receiver receives the code word and decodes it. Information obtained by the decoder determines whether an error is detected. The decoder detects single-bit and double-bit errors, but can only fix single-bit errors in the corrupted data. This type of ECC is single error correction double error detection (SECDED).
You can configure encoder and decoder functions of the ALTECC IP core. The data input to the encoder is encoded to generate a code word that is a combination of the data input and the generated parity bits. The generated code word is transmitted to the decoder module for decoding just before reaching its destination block. The decoder generates a syndrome vector to determine if there is any error in the received code word. The decoder corrects the data only if the single-bit error is from the data bits. No signal is flagged if the single-bit error is from the parity bits. The decoder also has flag signals to show the status of the data received and the action taken by the decoder, if any.
The following figures show the ports for the ALTECC IP core.
ALTECC Encoder Ports
ALTECC_ENCODER
data[]
q[]
clock
clocken
aclr
inst
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core 683490 | 2020.10.05
Figure 7. ALTECC Decoder Ports
ALTECC_DECODER
data[] clock clocken
q[] err_detected err_corrected
err_fatal
aclr
inst
7.1. ALTECC Encoder Features
The ALTECC encoder IP core offers the following features: · Performs data encoding using the Hamming Coding scheme · Supports data width of 264 bits · Supports signed and unsigned data representation format · Support pipelining with output latency of either one or two clock cycles · Supports optional asynchronous clear and clock enable ports
The ALTECC encoder IP core takes in and encodes the data using the Hamming Coding scheme. The Hamming Coding scheme derives the parity bits and appends them to the original data to produce the output code word. The number of parity bits appended depends on the width of the data.
The following table lists the number of parity bits appended for different ranges of data widths. The Total Bits column represents the total number of input data bits and appended parity bits.
Table 21.
Number of Parity Bits and Code Word According to Data Width
Data Width
Number of Parity Bits
Total Bits (Code Word)
2-4
3+1
6-8
5-11
4+1
10-16
12-26
5+1
18-32
27-57
6+1
34-64
58-64
7+1
66-72
The parity bit derivation uses an even-parity checking. The additional 1 bit
(shown in the table as +1) is appended to the parity bits as the MSB of the
code word. This ensures that the code word has an even number of 1’s. For
example, if the data width is 4 bits, 4 parity bits are appended to the data
to become a code word with a total of 8 bits. If 7 bits from the LSB of the
8-bit code word have an odd number of 1’s, the 8th bit (MSB) of the code word
is 1 making the total number of 1’s in the code word even.
The following figure shows the generated code word and the arrangement of the
parity bits and data bits in an 8-bit data input.
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Figure 8.
Parity Bits and Data Bits Arrangement in an 8-Bit Generated Code Word
MSB
LSB
4 parity bits
4 data bits
8
1
The ALTECC encoder IP core accepts only input widths of 2 to 64 bits at one time. Input widths of 12 bits, 29 bits, and 64 bits, which are ideally suited to Intel devices, generate outputs of 18 bits, 36 bits, and 72 bits respectively. You can control the bitselection limitation in the parameter editor.
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
The following Verilog HDL prototype is located in the Verilog Design File (.v)
lpm.v in the
module altecc_encoder #( parameter intended_device_family = “unused”,
parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter
width_dataword = 8, parameter lpm_type = “altecc_encoder”, parameter lpm_hint
= “unused”) ( input wire aclr, input wire clock, input wire clocken, input
wire [width_dataword-1:0] data, output wire [width_codeword-1:0] q); endmodule
7.3. Verilog HDL Prototype (ALTECC_DECODER)
The following Verilog HDL prototype is located in the Verilog Design File (.v)
lpm.v in the
module altecc_decoder #( parameter intended_device_family = “unused”,
parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter
width_dataword = 8, parameter lpm_type = “altecc_decoder”, parameter lpm_hint
= “unused”) ( input wire aclr, input wire clock, input wire clocken, input
wire [width_codeword-1:0] data, output wire err_corrected, output wire
err_detected, outut wire err_fatal, output wire [width_dataword-1:0] q);
endmodule
Intel FPGA Integer Arithmetic IP Cores User Guide 32
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7.4. VHDL Component Declaration (ALTECC_ENCODER)
The VHDL component declaration is located in the VHDL Design File (.vhd)
altera_mf_components.vhd in the <Intel Quartus Prime installation
directory>librariesvhdlaltera_mf directory.
component altecc_encoder generic ( intended_device_family:string := “unused”;
lpm_pipeline:natural := 0; width_codeword:natural := 8; width_dataword:natural
:= 8; lpm_hint:string := “UNUSED”; lpm_type:string := “altecc_encoder”); port(
aclr:in std_logic := ‘0’; clock:in std_logic := ‘0’; clocken:in std_logic :=
‘1’; data:in std_logic_vector(width_dataword-1 downto 0); q:out
std_logic_vector(width_codeword-1 downto 0)); end component;
7.5. VHDL Component Declaration (ALTECC_DECODER)
The VHDL component declaration is located in the VHDL Design File (.vhd)
altera_mf_components.vhd in the <Intel Quartus Prime installation
directory>librariesvhdlaltera_mf directory.
component altecc_decoder generic ( intended_device_family:string := “unused”;
lpm_pipeline:natural := 0; width_codeword:natural := 8; width_dataword:natural
:= 8; lpm_hint:string := “UNUSED”; lpm_type:string := “altecc_decoder”); port(
aclr:in std_logic := ‘0’; clock:in std_logic := ‘0’; clocken:in std_logic :=
‘1’; data:in std_logic_vector(width_codeword-1 downto 0); err_corrected : out
std_logic; err_detected : out std_logic; q:out
std_logic_vector(width_dataword-1 downto 0); syn_e : out std_logic); end
component;
7.6. VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component
Declaration.
LIBRARY altera_mf; USE altera_mf.altera_mf_components.all;
7.7. Encoder Ports
The following tables list the input and output ports for the ALTECC encoder IP
core.
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7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core 683490 | 2020.10.05
Table 22. ALTECC Encoder Input Ports
Port Name
Required
Description
data[]
Yes
Data input port. The size of the input port depends on the WIDTH_DATAWORD
parameter value. The data[] port contains the raw data to be encoded.
clock
Yes
Clock input port that provides the clock signal to synchronize the encoding operation.
The clock port is required when the LPM_PIPELINE value is greater than 0.
clocken
No
Clock enable. If omitted, the default value is 1.
aclr
No
Asynchronous clear input. The active high aclr signal can be used at any time to
asynchronously clear the registers.
Table 23. ALTECC Encoder Output Ports
Port Name q[]
Required Yes
Description
Encoded data output port. The size of the output port depends on the
WIDTH_CODEWORD parameter value.
7.8. Decoder Ports
The following tables list the input and output ports for the ALTECC decoder IP core.
Table 24. ALTECC Decoder Input Ports
Port Name
Required
Description
data[]
Yes
Data input port. The size of the input port depends on the WIDTH_CODEWORD parameter value.
clock
Yes
Clock input port that provides the clock signal to synchronize the encoding operation. The clock port is required when the LPM_PIPELINE value is greater than 0.
clocken
No
Clock enable. If omitted, the default value is 1.
aclr
No
Asynchronous clear input. The active high aclr signal can be used at any time to asynchronously clear the registers.
Table 25. ALTECC Decoder Output Ports
Port Name q[]
Required Yes
Description
Decoded data output port. The size of the output port depends on the
WIDTH_DATAWORD parameter value.
err_detected Yes
Flag signal to reflect the status of data received and specifies any errors found.
err_correcte Yes d
Flag signal to reflect the status of data received. Denotes single-bit error found and corrected. You can use the data because it has already been corrected.
err_fatal
Yes
Flag signal to reflect the status of data received. Denotes double-bit error found, but not corrected. You must not use the data if this signal is asserted.
syn_e
No
An output signal which will go high whenever a single-bit error is detected on the parity
bits.
7.9. Encoder Parameters
The following table lists the parameters for the ALTECC encoder IP core.
Intel FPGA Integer Arithmetic IP Cores User Guide 34
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Table 26. ALTECC Encoder Parameters
Parameter Name
Type
Required
Description
WIDTH_DATAWORD
Integer Yes
Specifies the width of the raw data. Values are from 2 to 64. If omitted, the default value is 8.
WIDTH_CODEWORD
Integer Yes
Specifies the width of the corresponding code word. Valid values are from 6 to 72, excluding 9, 17, 33, and 65. If omitted, the default value is 13.
LPM_PIPELINE
Integer No
Specifies the pipeline for the circuit. Values are from 0 to 2. If the value is 0, the ports are not registered. If the value is 1, the output ports are registered. If the value is 2, the input and output ports are registered. If omitted, the default value is 0.
7.10. Decoder Parameters
The following table lists the ALTECC decoder IP core parameters.
Table 27. ALTECC Decoder Parameters
Parameter Name WIDTH_DATAWORD
Type Integer
Required
Description
Yes
Specifies the width of the raw data. Values are 2 to 64. The
default value is 8.
WIDTH_CODEWORD
Integer
Yes
Specifies the width of the corresponding code word. Values are 6
to 72, excluding 9, 17, 33, and 65. If omitted, the default value
is 13.
LPM_PIPELINE
Integer
No
Specifies the register of the circuit. Values are from 0 to 2. If the
value is 0, no register is implemented. If the value is 1, the
output is registered. If the value is 2, both the input and the
output are registered. If the value is greater than 2, additional
registers are implemented at the output for the additional
latencies. If omitted, the default value is 0.
Create a ‘syn_e’ port
Integer
No
Turn on this parameter to create a syn_e port.
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8. Intel FPGA Multiply Adder IP Core
Figure 9.
The Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices) or ALTERA_MULT_ADD (Arria V, Stratix V, and Cyclone V devices) IP core allows you to implement a multiplier-adder.
The following figure shows the ports for the Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP core.
Intel FPGA Multiply Adder or ALTERA_MULT_ADD Ports
Intel FPGA Multiply Adder or ALTERA_MULT_ADD
dataa[] signa datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[]
coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] clock0 clock1 clock2 ena0
ena1 ena2 sload_accum
accum_sload chainin[]
scanouta[] result[]
aclr0 aclr1
inst
A multiplier-adder accepts pairs of inputs, multiplies the values together and
then adds to or subtracts from the products of all other pairs.
If all of the input data widths are 9-bits wide or smaller, the function uses
the 9 x 9 bit input multiplier configuration in the DSP block for devices
which support 9 x 9 configuration. If not, the DSP block uses 18 × 18-bit
input multipliers to process data with widths between 10 bits and 18 bits. If
multiple Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP cores occur in a
design, the functions are distributed to as
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
many different DSP blocks as possible so that routing to these blocks is more
flexible. Fewer multipliers per DSP block allow more routing choices into the
block by minimizing paths to the rest of the device.
The registers and extra pipeline registers for the following signals are also
placed inside the DSP block: · Data input · Signed or unsigned select · Add or
subtract select · Products of multipliers
In the case of the output result, the first register is placed in the DSP
block. However the extra latency registers are placed in logic elements
outside the block. Peripheral to the DSP block, including data inputs to the
multiplier, control signal inputs, and outputs of the adder, use regular
routing to communicate with the rest of the device. All connections in the
function use dedicated routing inside the DSP block. This dedicated routing
includes the shift register chains when you select the option to shift a
multiplier’s registered input data from one multiplier to an adjacent
multiplier.
For more information about DSP blocks in any of the Stratix V, and Arria V
device series, refer to the DSP Blocks chapter of the respective handbooks on
the Literature and Technical Documentation page.
Related Information AN 306: Implementing Multipliers in FPGA Devices
Provides more information about implementing multipliers using DSP and memory
blocks in Intel FPGA devices.
8.1. Features
The Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP core offers the following
features: · Generates a multiplier to perform multiplication operations of two
complex
numbers Note: When building multipliers larger than the natively supported
size there may/
will be a performance impact resulting from the cascading of the DSP blocks. ·
Supports data widths of 1 256 bits · Supports signed and unsigned data
representation format · Supports pipelining with configurable input latency ·
Provides an option to dynamically switch between signed and unsigned data
support · Provides an option to dynamically switch between add and subtract
operation · Supports optional asynchronous and synchronous clear and clock
enable input ports · Supports systolic delay register mode · Supports pre-
adder with 8 pre-load coefficients per multiplier · Supports pre-load constant
to complement accumulator feedback
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8.1.1. Pre-adder
With pre-adder, additions or subtractions are done prior to feeding the
multiplier.
There are five pre-adder modes: · Simple mode · Coefficient mode · Input mode
· Square mode · Constant mode
Note:
When pre-adder is used (pre-adder coefficient/input/square mode), all data inputs to the multiplier must have the same clock setting.
8.1.1.1. Pre-adder Simple Mode
In this mode, both operands derive from the input ports and pre-adder is not used or bypassed. This is the default mode.
Figure 10. Pre-adder Simple Mode
a0 b0
Mult0
result
8.1.1.2. Pre-adder Coefficient Mode
In this mode, one multiplier operand derives from the pre-adder, and the other
operand derives from the internal coefficient storage. The coefficient storage
allows up to 8 preset constants. The coefficient selection signals are
coefsel[0..3].
This mode is expressed in the following equation.
The following shows the pre-adder coefficient mode of a multiplier.
Figure 11. Pre-adder Coefficient Mode
Preadder
a0
Mult0
+/-
result
b0
coefsel0 coef
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8.1.1.3. Pre-adder Input Mode In this mode, one multiplier operand derives
from the pre-adder, and the other operand derives from the datac[] input port.
This mode is expressed in the following equation.
The following shows the pre-adder input mode of a multiplier.
Figure 12. Pre-adder Input Mode
a0 b0
Mult0
+/-
result
c0
8.1.1.4. Pre-adder Square Mode This mode is expressed in the following equation.
The following shows the pre-adder square mode of two multipliers.
Figure 13. Pre-adder Square Mode
a0 b0
Mult0
+/-
result
8.1.1.5. Pre-adder Constant Mode
In this mode, one multiplier operand derives from the input port, and the
other operand derives from the internal coefficient storage. The coefficient
storage allows up to 8 preset constants. The coefficient selection signals are
coefsel[0..3].
This mode is expressed in the following equation.
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The following figure shows the pre-adder constant mode of a multiplier.
Figure 14. Pre-adder Constant Mode
a0
Mult0
result
coefsel0
coef
8.1.2. Systolic Delay Register
In a systolic architecture, the input data is fed into a cascade of registers
acting as a data buffer. Each register delivers an input sample to a
multiplier where it is multiplied by the respective coefficient. The chain
adder stores the gradually combined results from the multiplier and the
previously registered result from the chainin[] input port to form the final
result. Each multiply-add element must be delayed by a single cycle so that
the results synchronize appropriately when added together. Each successive
delay is used to address both the coefficient memory and the data buffer of
their respective multiply-add elements. For example, a single delay for the
second multiply add element, two delays for the third multiply-add element,
and so on.
Figure 15. Systolic Registers
Systolic registers
x(t) c(0)
S -1
S -1
c(1)
S -1
S -1
c(2)
S -1
S -1
c(N-1)
S -1
S -1
S -1
S -1 y(t)
x(t) represents the results from a continuous stream of input samples and y(t)
represents the summation of a set of input samples, and in time, multiplied by
their
respective coefficients. Both the input and output results flow from left to
right. The c(0) to c(N-1) denotes the coefficients. The systolic delay
registers are denoted by S-1, whereas the 1 represents a single clock delay.
Systolic delay registers are added at
the inputs and outputs for pipelining in a way that ensures the results from
the
multiplier operand and the accumulated sums stay in synch. This processing
element
is replicated to form a circuit that computes the filtering function. This
function is
expressed in the following equation.
Intel FPGA Integer Arithmetic IP Cores User Guide 40
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N represents the number of cycles of data that has entered into the
accumulator, y(t) represents the output at time t, A(t) represents the input
at time t, and B(i) are the coefficients. The t and i in the equation
correspond to a particular instant in time, so to compute the output sample
y(t) at time t, a group of input samples at N different points in time, or
A(n), A(n-1), A(n-2), … A(n-N+1) is required. The group of N input samples are
multiplied by N coefficients and summed together to form the final result y.
The systolic register architecture is available only for sum-of-2 and sum-of-4
modes. For both systolic register architecture modes, the first chainin signal
needs to be tied to 0.
The following figure shows the systolic delay register implementation of 2
multipliers.
Figure 16. Systolic Delay Register Implementation of 2 Multipliers
chainin
a0
Mult0
+/-
b0
a1
Mult1
+/-
b1
result
The sum of two multipliers is expressed in the following equation.
The following figure shows the systolic delay register implementation of 4
multipliers.
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Figure 17. Systolic Delay Register Implementation of 4 Multipliers
chainin
a0
Mult0
+/-
b0
a1
Mult1
+/-
b1
a2
Mult2
+/-
b2
a3
Mult3
+/-
b3
result
The sum of four multipliers is expressed in the following equation. Figure 18.
Sum of 4 Multipliers
The following lists the advantages of systolic register implementation: ·
Reduces DSP resource usage · Enables efficient mapping in the DSP block using
the chain adder structure
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8.1.3. Pre-load Constant
The pre-load constant controls the accumulator operand and complements the
accumulator feedback. The valid LOADCONST_VALUE ranges from 064. The constant
value is equal to 2N, where N = LOADCONST_VALUE. When the LOADCONST_VALUE is
set to 64, the constant value is equal to 0. This function can be used as
biased rounding.
The following figure shows the pre-load constant implementation.
Figure 19. Pre-load Constant
Accumulator feedback
constant
a0
Mult0
+/-
b0
a1
Mult1
+/b1
result
accum_sload sload_accum
Refer to the following IP cores for other multiplier implementations: ·
ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Double Accumulator
The double accumulator feature adds an additional register in the accumulator
feedback path. The double accumulator register follows the output register,
which includes the clock, clock enable, and aclr. The additional accumulator
register returns result with a one-cycle delay. This feature enables you to
have two accumulator channels with the same resource count.
The following figure shows the double accumulator implementation.
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Figure 20. Double Accumulator
Dou ble Accu mulator Register
Accu mulator feedba ck
a0
Mult0
+/-
b0
a1
Mult1
+/b1
Output result Output Register
8.2. Verilog HDL Prototype
You can find the Intel FPGA Multiply Adder or ALTERA_MULT_ADD Verilog HDL
prototype file (altera_mult_add_rtl.v) in the <Intel Quartus Prime
installation directory>librariesmegafunctions directory.
8.3. VHDL Component Declaration
The VHDL component declaration is located in the altera_lnsim_components.vhd
in the
8.4. VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component
Declaration.
LIBRARY altera_mf; USE altera_mf.altera_mf_components.all;
8.5. Signals
The following tables list the input and output signals of the Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.
Table 28. Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD Input Signals
Signal
Required
Description
dataa_0[]/dataa_1[]/
Yes
dataa_2[]/dataa_3[]
Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1
… 0] wide
continued…
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Signal datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/
datac_2[]/datac_3[] clock[1:0] aclr[1:0] sclr[1:0] ena[1:0] signa
signb
scanina[] accum_sload
Required Yes No
No No No No No
No
No No
Description
The simulation model for this IP supports undetermined input value (X) to
these signals. When you provide X value to these signals,the X value is
propagated on the output signals.
Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS WIDTH_B –
1 … 0] wide The simulation model for this IP supports undetermined input value
(X) to these signals. When you provide X value to these signals, the X value
is propagated on the output signals.
Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS WIDTH_C –
1, … 0] wide Select INPUT for Select preadder mode parameter to enable these
signals. The simulation model for this IP supports undetermined input value
(X) to these signals. When you provide X value to these signals, the X value
is propagated on the output signals.
Clock input port to the corresponding register. This signal can be used by any
register in the IP core. The simulation model for this IP supports
undetermined input value (X) to these signals. When you provide X value to
these signals, the X value is propagated on the output signals.
Asynchronous clear input to the corresponding register. The simulation model
for this IP supports undetermined input value (X) to these signals. When you
provide X value to these signals, the X value is propagated on the output
signals.
Synchronous clear input to the corresponding register. The simulation model
for this IP supports undetermined input value X to these signals. When you
provide X value to these signals, the X value is propagated on the output
signals
Enable signal input to the corresponding register. The simulation model for
this IP supports undetermined input value (X) to these signals. When you
provide X value to these signals, the X value is propagated on the output
signals.
Specifies the numerical representation of the multiplier input A. If the signa
signal is high, the multiplier treats the multiplier input A signal as a
signed number. If the signa signal is low, the multiplier treats the
multiplier input A signal as an unsigned number. Select VARIABLE for What is
the representation format for Multipliers A inputs parameter to enable this
signal. The simulation model for this IP supports undetermined input value (X)
to this signal. When you provide X value to this input, the X value is
propagated on the output signals.
Specifies the numerical representation of the multiplier input B signal. If
the signb signal is high, the multiplier treats the multiplier input B signal
as a signed two’s complement number. If the signb signal is low, the
multiplier treats the multiplier input B signal as an unsigned number. The
simulation model for this IP supports undetermined input value (X) to this
signal. When you provide X value to this input, the X value is propagated on
the output signals.
Input for scan chain A. Input signal [WIDTH_A – 1, … 0] wide. When the
INPUT_SOURCE_A parameter has a value of SCANA, the scanina[] signal is
required.
Dynamically specifies whether the accumulator value is constant. If the
accum_sload signal is low, then the multiplier output is loaded into the
accumulator. Do not use accum_sload and sload_accum simultaneously.
continued…
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Signal sload_accum
chainin[] addnsub1
addnsub3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]
Required No
No No
No
No No No No
Description
The simulation model for this IP supports undetermined input value (X) to this
signal. When you provide X value to this input, the X value is propagated on
the output signals.
Dynamically specifies whether the accumulator value is constant. If the
sload_accum signal is high, then the multiplier output is loaded into the
accumulator. Do not use accum_sload and sload_accum simultaneously. The
simulation model for this IP supports undetermined input value (X) to this
signal. When you provide X value to this input, the X value is propagated on
the output signals.
Adder result input bus from the preceding stage. Input signal [WIDTH_CHAININ –
1, … 0] wide.
Perform addition or subtraction to the outputs from the first pair of
multipliers. Input 1 to addnsub1 signal to add the outputs from the first pair
of multipliers. Input 0 to addnsub1 signal to subtract the outputs from the
first pair of multipliers. The simulation model for this IP supports
undetermined input value (X) to this signal. When you provide X value to this
input, the X value is propagated on the output signals.
Perform addition or subtraction to the outputs from the first pair of
multipliers. Input 1 to addnsub3 signal to add the outputs from the second
pair of multipliers. Input 0 to addnsub3 signal to subtract the outputs from
the first pair of multipliers. The simulation model for this IP supports
undetermined input value (X) to this signal. When you provide X value to this
input, the X value is propagated on the output signals.
Coefficient input signal[0:3] to the first multiplier. The simulation model
for this IP supports undetermined input value (X) to this signal. When you
provide X value to this input, the X value is propagated on the output
signals.
Coefficient input signal[0:3]to the second multiplier. The simulation model
for this IP supports undetermined input value (X) to this signal. When you
provide X value to this input, the X value is propagated on the output
signals.
Coefficient input signal[0:3]to the third multiplier. The simulation model for
this IP supports undetermined input value (X) to this signal. When you provide
X value to this input, the X value is propagated on the output signals.
Coefficient input signal [0:3] to the fourth multiplier. The simulation model
for this IP supports undetermined input value (X) to this signal. When you
provide X value to this input, the X value is propagated on the output
signals.
Table 29. Multiply Adder Intel FPGA IP Output Signals
Signal
Required
Description
result []
Yes
Multiplier output signal. Output signal [WIDTH_RESULT – 1 … 0] wide
The simulation model for this IP supports undetermined output value (X). When you provide X value as the input, the X value is propagated on this signal.
scanouta []
No
Output of scan chain A. Output signal [WIDTH_A – 1..0] wide.
Select more than 2 for numbers of multipliers and choose Scan chain input for What is the input A of the multiplier connected to parameter to enable this signal.
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8.6. Parameters
8.6.1. General Tab
Table 30. General Tab
Parameter
IP Generated Parameter
Value
What is the number of multipliers?
number_of_m 1 – 4 ultipliers
How wide should the A width_a input buses be?
1 – 256
How wide should the B width_b input buses be?
1 – 256
How wide should the ‘result’ output bus be?
width_result
1 – 256
Create an associated clock enable for each clock
gui_associate On d_clock_enabl Off e
8.6.2. Extra Modes Tab
Table 31. Extra Modes Tab
Parameter
IP Generated Parameter
Value
Outputs Configuration
Register output of the adder unit
gui_output_re On
gister
Off
What is the source for clock input?
gui_output_re gister_clock
Clock0 Clock1 Clock2
What is the source for asynchronous clear input?
gui_output_re gister_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_output_re gister_sclr
NONE SCLR0 SCLR1
Adder Operation
What operation should be performed on outputs of the first pair of multipliers?
gui_multiplier 1_direction
ADD, SUB, VARIABLE
Default Value 1
16
Description
Number of multipliers to be added together. Values are 1 up to 4. Specify the
width of the dataa[] port.
16
Specify the width of the datab[] port.
32
Specify the width of the result[] port.
Off
Select this option to create clock enable
for each clock.
Default Value
Description
Off Clock0
NONE NONE
Select this option to enable output register of the adder module.
Select Clock0 , Clock1 or Clock2 to enable and specify the clock source for
output registers. You must select Register output of the adder unit to enable
this parameter.
Specifies the asynchronous clear source for the adder output register. You
must select Register output of the adder unit to enable this parameter.
Specifies the synchronous clear source for the adder output register. You must
select Register output of the adder unit to enable this parameter.
ADD
Select addition or subtraction operation to perform for the outputs between
the first and second multipliers.
· Select ADD to perform addition operation.
· Select SUB to perform subtraction operation.
· Select VARIABLE to use addnsub1 port for dynamic addition/subtraction
control.
continued…
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Parameter
IP Generated Parameter
Value
Register ‘addnsub1’ input
guiaddnsub On multiplier_reg Off ister1
What is the source for clock input?
guiaddnsub multiplier_reg ister1_clock
Clock0 Clock1 Clock2
What is the source for asynchronous clear input?
guiaddnsub multiplier_aclr 1
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
guiaddnsub multiplier_sclr 1
NONE SCLR0 SCLR1
What operation should be performed on outputs of the second pair of multipliers?
gui_multiplier 3_direction
ADD, SUB, VARIABLE
Register ‘addnsub3’ input
guiaddnsub On multiplier_reg Off ister3
What is the source for clock input?
guiaddnsub multiplier_reg ister3_clock
Clock0 Clock1 Clock2
Default Value
Off Clock0 NONE NONE ADD
Off Clock0
Description
When VARIABLE value is selected: · Drive addnsub1 signal to high for
addition operation. · Drive addnsub1 signal to low for
subtraction operation. You must select more than two multipliers to enable
this parameter.
Select this option to enable input register for addnsub1 port. You must select
VARIABLE for What operation should be performed on outputs of the first pair
of multipliers to enable this parameter.
Select Clock0 , Clock1 or Clock2 to specify the input clock signal for
addnsub1 register. You must select Register ‘addnsub1’ input to enable this
parameter.
Specifies the asynchronous clear source for the addnsub1 register. You must
select Register ‘addnsub1’ input to enable this parameter.
Specifies the synchronous clear source for the addnsub1 register. You must
select Register ‘addnsub1’ input to enable this parameter.
Select addition or subtraction operation to perform for the outputs between
the third and fourth multipliers. · Select ADD to perform addition
operation. · Select SUB to perform subtraction
operation. · Select VARIABLE to use addnsub1
port for dynamic addition/subtraction control. When VARIABLE value is
selected: · Drive addnsub1 signal to high for addition operation. · Drive
addnsub1 signal to low for subtraction operation. You must select the value 4
for What is the number of multipliers? to enable this parameter.
Select this option to enable input register for addnsub3 signal. You must
select VARIABLE for What operation should be performed on outputs of the
second pair of multipliers to enable this parameter.
Select Clock0 , Clock1 or Clock2 to specify the input clock signal for
addnsub3 register. You must select Register ‘addnsub3′ input to enable this
parameter.
continued…
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Parameter
What is the source for asynchronous clear input?
IP Generated Parameter
Value
guiaddnsub multiplier_aclr 3
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
guiaddnsub multiplier_sclr 3
NONE SCLR0 SCLR1
Polarity Enable `use_subadd’
gui_use_subn On
add
Off
8.6.3. Multipliers Tab
Table 32. Multipliers Tab
Parameter
IP Generated Parameter
Value
What is the
gui_represent
representation format ation_a
for Multipliers A inputs?
SIGNED, UNSIGNED, VARIABLE
Register `signa’ input
gui_register_s On
igna
Off
What is the source for clock input?
gui_register_s igna_clock
Clock0 Clock1 Clock2
What is the source for asynchronous clear input?
gui_register_s igna_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_register_s igna_sclr
NONE SCLR0 SCLR1
What is the
gui_represent
representation format ation_b
for Multipliers B inputs?
SIGNED, UNSIGNED, VARIABLE
Register `signb’ input
gui_register_s On
ignb
Off
Default Value NONE
NONE
Description
Specifies the asynchronous clear source for the addnsub3 register. You must
select Register ‘addnsub3’ input to enable this parameter.
Specifies the synchronous clear source for the addnsub3 register. You must
select Register ‘addnsub3′ input to enable this parameter.
Off
Select this option to reverse the function
of addnsub input port.
Drive addnsub to high for subtraction operation.
Drive addnsub to low for addition operation.
Default Value
Description
UNSIGNED Specify the representation format for the multiplier A input.
Off
Select this option to enable signa
register.
You must select VARIABLE value for What is the representation format for Multipliers A inputs? parameter to enable this option.
Clock0
Select Clock0 , Clock1 or Clock2 to enable and specify the input clock signal
for signa register.
You must select Register `signa’ input to enable this parameter.
NONE
Specifies the asynchronous clear source for the signa register.
You must select Register `signa’ input to enable this parameter.
NONE
Specifies the synchronous clear source for the signa register.
You must select Register `signa’ input to enable this parameter.
UNSIGNED Specify the representation format for the multiplier B input.
Off
Select this option to enable signb
register.
continued…
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Parameter
IP Generated Parameter
Value
Default Value
What is the source for clock input?
gui_register_s ignb_clock
Clock0 Clock1 Clock2
Clock0
What is the source for asynchronous clear input?
gui_register_s ignb_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_register_s ignb_sclr
NONE SCLR0 SCLR1
Input Configuration
Register input A of the multiplier
What is the source for clock input?
gui_input_reg On
ister_a
Off
gui_input_reg ister_a_clock
Clock0 Clock1 Clock2
NONE NONE
Off Clock0
What is the source for asynchronous clear input?
gui_input_reg ister_a_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_input_reg ister_a_sclr
NONE SCLR0 SCLR1
Register input B of the multiplier
What is the source for clock input?
gui_input_reg On
ister_b
Off
gui_input_reg ister_b_clock
Clock0 Clock1 Clock2
NONE NONE Off Clock0
What is the source for asynchronous clear input?
gui_input_reg ister_b_aclr
NONE ACLR0 ACLR1
NONE
What is the source for synchronous clear input?
gui_input_reg ister_b_sclr
NONE SCLR0 SCLR1
NONE
What is the input A of the multiplier connected to?
gui_multiplier Multiplier input Multiplier
_a_input
Scan chain input input
Description
You must select VARIABLE value for What is the representation format for
Multipliers B inputs? parameter to enable this option.
Select Clock0 , Clock1 or Clock2 to enable and specify the input clock signal
for signb register. You must select Register signb’ input to enable this parameter. Specifies the asynchronous clear source for the signb register. You must select Registersignb’ input to enable this parameter.
Specifies the synchronous clear source for the signb register. You must select
Register `signb’ input to enable this parameter.
Select this option to enable input register for dataa input bus.
Select Clock0 , Clock1 or Clock2 to enable and specify the register input
clock signal for dataa input bus. You must select Register input A of the
multiplier to enable this parameter.
Specifies the register asynchronous clear source for the dataa input bus. You
must select Register input A of the multiplier to enable this parameter.
Specifies the register synchronous clear source for the dataa input bus. You
must select Register input A of the multiplier to enable this parameter.
Select this option to enable input register for datab input bus.
Select Clock0 , Clock1 or Clock2 to enable and specify the register input
clock signal for datab input bus. You must select Register input B of the
multiplier to enable this parameter.
Specifies the register asynchronous clear source for the datab input bus. You
must select Register input B of the multiplier to enable this parameter.
Specifies the register synchronous clear source for the datab input bus. You
must select Register input B of the multiplier to enable this parameter.
Select the input source for input A of the multiplier.
continued…
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Parameter
IP Generated Parameter
Value
Scanout A Register Configuration
Register output of the scan chain
gui_scanouta On
_register
Off
What is the source for clock input?
gui_scanouta _register_cloc k
Clock0 Clock1 Clock2
What is the source for asynchronous clear input?
gui_scanouta _register_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_scanouta _register_sclr
NONE SCLR0 SCLR1
8.6.4. Preadder Tab
Table 33. Preadder Tab
Parameter
IP Generated Parameter
Value
Select preadder mode
preadder_mo de
SIMPLE, COEF, INPUT, SQUARE, CONSTANT
Default Value
Description
Select Multiplier input to use dataa input bus as the source to the
multiplier. Select Scan chain input to use scanin input bus as the source to
the multiplier and enable the scanout output bus. This parameter is available
when you select 2, 3 or 4 for What is the number of multipliers? parameter.
Off Clock0 NONE NONE
Select this option to enable output register for scanouta output bus.
You must select Scan chain input for What is the input A of the multiplier
connected to? parameter to enable this option.
Select Clock0 , Clock1 or Clock2 to enable and specify the register input
clock signal for scanouta output bus.
You must turn on Register output of the scan chain parameter to enable this
option.
Specifies the register asynchronous clear source for the scanouta output bus.
You must turn on Register output of the scan chain parameter to enable this
option.
Specifies the register synchronous clear source for the scanouta output bus.
You must select Register output of the scan chain parameter to enable this
option.
Default Value
SIMPLE
Description
Specifies the operation mode for preadder module. SIMPLE: This mode bypass the
preadder. This is the default mode. COEF: This mode uses the output of the
preadder and coefsel input bus as the inputs to the multiplier. INPUT: This
mode uses the output of the preadder and datac input bus as the inputs to the
multiplier. SQUARE: This mode uses the output of the preadder as both the
inputs to the multiplier.
continued…
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Parameter
IP Generated Parameter
Value
Select preadder direction
gui_preadder ADD,
_direction
SUB
How wide should the C width_c input buses be?
1 – 256
Data C Input Register Configuration
Register datac input
gui_datac_inp On
ut_register
Off
What is the source for clock input?
gui_datac_inp ut_register_cl ock
Clock0 Clock1 Clock2
What is the source for asynchronous clear input?
gui_datac_inp ut_register_a clr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_datac_inp ut_register_sc lr
NONE SCLR0 SCLR1
Coefficients
How wide should the coef width be?
width_coef
1 – 27
Coef Register Configuration
Register the coefsel input
gui_coef_regi On
ster
Off
What is the source for clock input?
gui_coef_regi ster_clock
Clock0 Clock1 Clock2
Default Value
ADD
16
Description
CONSTANT: This mode uses dataa input bus with preadder bypassed and coefsel
input bus as the inputs to the multiplier.
Specifies the operation of the preadder. To enable this parameter, select the
following for Select preadder mode: · COEF · INPUT · SQUARE or · CONSTANT
Specifies the number of bits for C input bus. You must select INPUT for Select
preadder mode to enable this parameter.
On Clock0 NONE NONE
Select this option to enable input register for datac input bus. You must set
INPUT to Select preadder mode parameter to enable this option.
Select Clock0 , Clock1 or Clock2 to specify the input clock signal for datac
input register. You must select Register datac input to enable this parameter.
Specifies the asynchronous clear source for the datac input register. You must
select Register datac input to enable this parameter.
Specifies the synchronous clear source for the datac input register. You must
select Register datac input to enable this parameter.
18
Specifies the number of bits for
coefsel input bus.
You must select COEF or CONSTANT for preadder mode to enable this parameter.
On Clock0
Select this option to enable input register for coefsel input bus. You must
select COEF or CONSTANT for preadder mode to enable this parameter.
Select Clock0 , Clock1 or Clock2 to specify the input clock signal for coefsel
input register. You must select Register the coefsel input to enable this
parameter.
continued…
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Parameter
What is the source for asynchronous clear input?
IP Generated Parameter
Value
gui_coef_regi ster_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input
gui_coef_regi ster_sclr
NONE SCLR0 SCLR1
Coefficient_0 Configuration
coef0_0 to coef0_7
0x00000 0xFFFFFFF
Coefficient_1 Configuration
coef1_0 to coef1_7
0x00000 0xFFFFFFF
Coefficient_2 Configuration
coef2_0 to coef2_7
0x00000 0xFFFFFFF
Coefficient_3 Configuration
coef3_0 to coef3_7
0x00000 0xFFFFFFF
8.6.5. Accumulator Tab
Table 34. Accumulator Tab
Parameter
IP Generated Parameter
Value
Enable accumulator?
accumulator
YES, NO
What is the accumulator operation type?
accum_directi ADD,
on
SUB
Default Value NONE
NONE
0x0000000 0
0x0000000 0
0x0000000 0
0x0000000 0
Description
Specifies the asynchronous clear source for the coefsel input register. You
must select Register the coefsel input to enable this parameter.
Specifies the synchronous clear source for the coefsel input register. You
must select Register the coefsel input to enable this parameter.
Specifies the coefficient values for this first multiplier. The number of bits
must be the same as specified in How wide should the coef width be? parameter.
You must select COEF or CONSTANT for preadder mode to enable this parameter.
Specifies the coefficient values for this second multiplier. The number of
bits must be the same as specified in How wide should the coef width be?
parameter. You must select COEF or CONSTANT for preadder mode to enable this
parameter.
Specifies the coefficient values for this third multiplier. The number of bits
must be the same as specified in How wide should the coef width be? parameter.
You must select COEF or CONSTANT for preadder mode to enable this parameter.
Specifies the coefficient values for this fourth multiplier. The number of
bits must be the same as specified in How wide should the coef width be?
parameter. You must select COEF or CONSTANT for preadder mode to enable this
parameter.
Default Value NO
ADD
Description
Select YES to enable the accumulator. You must select Register output of adder
unit when using accumulator feature.
Specifies the operation of the accumulator: · ADD for addition operation · SUB
for subtraction operation. You must select YES for Enable accumulator?
parameter to enable this option.
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Parameter
Preload Constant Enable preload constant
IP Generated Parameter
Value
gui_ena_prelo On
ad_const
Off
What is the input of accumulate port connected to?
gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM
Select value for preload loadconst_val 0 – 64
constant
ue
What is the source for clock input?
gui_accum_sl oadregister clock
Clock0 Clock1 Clock2
What is the source for asynchronous clear input?
gui_accum_sl oadregister aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_accum_sl oadregister sclr
NONE SCLR0 SCLR1
Enable double accumulator
gui_double_a On
ccum
Off
Default Value
Description
Off
Enable the accum_sload or
sload_accum signals and register input
to dynamically select the input to the
accumulator.
When accum_sload is low or sload_accum, the multiplier output is feed into the accumulator.
When accum_sload is high or sload_accum, a user specified preload constant is feed into the accumulator.
You must select YES for Enable accumulator? parameter to enable this option.
ACCUM_SL OAD
Specifies the behavior of accum_sload/ sload_accum signal.
ACCUM_SLOAD: Drive accum_sload low to load the multiplier output to the
accumulator.
SLOAD_ACCUM: Drive sload_accum high to load the multiplier output to the
accumulator.
You must select Enable preload constant option to enable this parameter.
64
Specify the preset constant value.
This value can be 2N where N is the preset constant value.
When N=64, it represents a constant zero.
You must select Enable preload constant option to enable this parameter.
Clock0
Select Clock0 , Clock1 or Clock2 to specify the input clock signal for
accum_sload/sload_accum register.
You must select Enable preload constant option to enable this parameter.
NONE
Specifies the asynchronous clear source for the accum_sload/sload_accum
register.
You must select Enable preload constant option to enable this parameter.
NONE
Specifies the synchronous clear source for the accum_sload/sload_accum
register.
You must select Enable preload constant option to enable this parameter.
Off
Enables the double accumulator register.
Intel FPGA Integer Arithmetic IP Cores User Guide 54
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8.6.6. Systolic/Chainout Tab
Table 35. Systolic/Chainout Adder Tab
Parameter Enable chainout adder
IP Generated Parameter
Value
chainout_add YES,
er
NO
What is the chainout adder operation type?
chainout_add ADD,
er_direction
SUB
Enable `negate’ input for chainout adder?
Port_negate
PORT_USED, PORT_UNUSED
Register `negate’ input? negate_regist er
UNREGISTERED, CLOCK0, CLOCK1, CLOCK2, CLOCK3
What is the source for asynchronous clear input?
negate_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
negate_sclr
NONE SCLR0 SCLR1
Systolic Delay
Enable systolic delay registers
gui_systolic_d On
elay
Off
What is the source for clock input?
gui_systolic_d CLOCK0,
elay_clock
CLOCK1,
Default Value
NO
Description
Select YES to enable chainout adder module.
ADD
Specifies the chainout adder operation.
For subtraction operation, SIGNED must be selected for What is the
representation format for Multipliers A inputs? and What is the representation
format for Multipliers B inputs? in the Multipliers Tab.
PORT_UN USED
Select PORT_USED to enable negate input signal.
This parameter is invalid when chainout adder is disabled.
UNREGIST ERED
To enable the input register for negate input signal and specifies the input
clock signal for negate register.
Select UNREGISTERED if the negate input register to is not needed
This parameter is invalid when you select:
· NO for Enable chainout adder or
· PORT_UNUSED for Enable ‘negate’ input for chainout adder? parameter or
NONE
Specifies the asynchronous clear source for the negate register.
This parameter is invalid when you select:
· NO for Enable chainout adder or
· PORT_UNUSED for Enable ‘negate’ input for chainout adder? parameter or
NONE
Specifies the synchronous clear source for the negate register.
This parameter is invalid when you select:
· NO for Enable chainout adder or
· PORT_UNUSED for Enable ‘negate’ input for chainout adder? parameter or
Off CLOCK0
Select this option to enable systolic mode. This parameter is available when
you select 2, or 4 for What is the number of multipliers? parameter. You must
enable the Register output of the adder unit to use the systolic delay
registers.
Specifies the input clock signal for systolic delay register.
continued…
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Parameter
IP Generated Parameter
Value
CLOCK2,
What is the source for asynchronous clear input?
gui_systolic_d elay_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_systolic_d elay_sclr
NONE SCLR0 SCLR1
Default Value
NONE
NONE
Description
You must select enable systolic delay registers to enable this option.
Specifies the asynchronous clear source for the systolic delay register. You
must select enable systolic delay registers to enable this option.
Specifies the synchronous clear source for the systolic delay register. You
must select enable systolic delay registers to enable this option.
8.6.7. Pipelining Tab
Table 36. Pipelining Tab
Parameter Pipelining Configuration
IP Generated Parameter
Value
Do you want to add pipeline register to the input?
gui_pipelining No, Yes
Default Value
No
Please specify the
latency
number of latency clock
cycles
Any value greater 0 than 0
What is the source for clock input?
gui_input_late ncy_clock
CLOCK0, CLOCK1, CLOCK2
What is the source for asynchronous clear input?
gui_input_late ncy_aclr
NONE ACLR0 ACLR1
What is the source for synchronous clear input?
gui_input_late ncy_sclr
NONE SCLR0 SCLR1
CLOCK0 NONE NONE
Description
Select Yes to enable an additional level of pipeline register to the input
signals. You must specify a value greater than 0 for Please specify the number
of latency clock cycles parameter.
Specifies the desired latency in clock cycles. One level of pipeline register
= 1 latency in clock cycle. You must select YES for Do you want to add
pipeline register to the input? to enable this option.
Select Clock0 , Clock1 or Clock2 to enable and specify the pipeline register
input clock signal. You must select YES for Do you want to add pipeline
register to the input? to enable this option.
Specifies the register asynchronous clear source for the additional pipeline
register. You must select YES for Do you want to add pipeline register to the
input? to enable this option.
Specifies the register synchronous clear source for the additional pipeline
register. You must select YES for Do you want to add pipeline register to the
input? to enable this option.
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683490 | 2020.10.05 Send Feedback
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
Attention:
Intel has removed the support of this IP in Intel Quartus Prime Pro Edition version 20.3. If the IP core in your design targets devices in Intel Quartus Prime Pro Edition, you can replace the IP with LPM_MULT Intel FPGA IP or re- generate the IP and compile your design using Intel Quartus Prime Standard Edition software.
The ALTMEMMULT IP core is used to create memory-based multipliers using the
onchip memory blocks found in Intel FPGAs (with M512, M4K, M9K, and MLAB
memory blocks). This IP core is useful if you do not have sufficient resources
to implement the multipliers in logic elements (LEs) or dedicated multiplier
resources.
The ALTMEMMULT IP core is a synchronous function that requires a clock. The
ALTMEMMULT IP core implements a multiplier with the smallest throughput and
latency possible for a given set of parameters and specifications.
The following figure shows the ports for the ALTMEMMULT IP core.
Figure 21. ALTMEMMULT Ports
ALTMEMMULT
data_in[] sload_data coeff_in[]
result[] result_valid load_done
sload_coeff
sclr clock
inst
Related Information Features on page 71
9.1. Features
The ALTMEMMULT IP core offers the following features: · Creates only memory-
based multipliers using on-chip memory blocks found in
Intel FPGAs · Supports data width of 1512 bits · Supports signed and unsigned
data representation format · Supports pipelining with fixed output latency
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ISO 9001:2015 Registered
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 |
2020.10.05
· Stores multiples constants in random-access memory (RAM)
· Provides an option to select the RAM block type
· Supports optional synchronous clear and load-control input ports
9.2. Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v)
altera_mf.v in the
module altmemmult #( parameter coeff_representation = “SIGNED”, parameter
coefficient0 = “UNUSED”, parameter data_representation = “SIGNED”, parameter
intended_device_family = “unused”, parameter max_clock_cycles_per_result = 1,
parameter number_of_coefficients = 1, parameter ram_block_type = “AUTO”,
parameter total_latency = 1, parameter width_c = 1, parameter width_d = 1,
parameter width_r = 1, parameter width_s = 1, parameter lpm_type =
“altmemmult”, parameter lpm_hint = “unused”) ( input wire clock, input wire
[width_c-1:0]coeff_in, input wire [width_d-1:0] data_in, output wire
load_done, output wire [width_r-1:0] result, output wire result_valid, input
wire sclr, input wire [width_s-1:0] sel, input wire sload_coeff, input wire
sload_data)/ synthesis syn_black_box=1 /; endmodule
9.3. VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd)
altera_mf_components.vhd in the <Intel Quartus Prime installation
directory>librariesvhdlaltera_mf directory.
component altmemmult generic ( coeff_representation:string := “SIGNED”;
coefficient0:string := “UNUSED”; data_representation:string := “SIGNED”;
intended_device_family:string := “unused”; max_clock_cycles_per_result:natural
:= 1; number_of_coefficients:natural := 1; ram_block_type:string := “AUTO”;
total_latency:natural; width_c:natural; width_d:natural; width_r:natural;
width_s:natural := 1; lpm_hint:string := “UNUSED”; lpm_type:string :=
“altmemmult”); port( clock:in std_logic; coeff_in:in
std_logic_vector(width_c-1 downto 0) := (others => ‘0’); data_in:in
std_logic_vector(width_d-1 downto 0);
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load_done:out std_logic; result:out std_logic_vector(width_r-1 downto 0); result_valid:out std_logic; sclr:in std_logic := ‘0’; sel:in std_logic_vector(width_s-1 downto 0) := (others => ‘0’); sload_coeff:in std_logic := ‘0’; sload_data:in std_logic := ‘0’); end component;
9.4. Ports
The following tables list the input and output ports for the ALTMEMMULT IP core.
Table 37. ALTMEMMULT Input Ports
Port Name
Required
Description
clock
Yes
Clock input to the multiplier.
coeff_in[]
No
Coefficient input port for the multiplier. The size of the input port depends on the WIDTH_C parameter value.
data_in[]
Yes
Data input port to the multiplier. The size of the input port depends on the WIDTH_D parameter value.
sclr
No
Synchronous clear input. If unused, the default value is active high.
sel[]
No
Fixed coefficient selection. The size of the input port depends on the WIDTH_S
parameter value.
sload_coeff
No
Synchronous load coefficient input port. Replaces the current selected coefficient value with the value specified in the coeff_in input.
sload_data
No
Synchronous load data input port. Signal that specifies new multiplication operation and cancels any existing multiplication operation. If the MAX_CLOCK_CYCLES_PER_RESULT parameter has a value of 1, the sload_data input port is ignored.
Table 38. ALTMEMMULT Output Ports
Port Name
Required
Description
result[]
Yes
Multiplier output port. The size of the input port depends on the WIDTH_R parameter value.
result_valid
Yes
Indicates when the output is the valid result of a complete multiplication. If the MAX_CLOCK_CYCLES_PER_RESULT parameter has a value of 1, the result_valid output port is not used.
load_done
No
Indicates when the new coefficient has finished loading. The load_done signal asserts when a new coefficient has finished loading. Unless the load_done signal is high, no other coefficient value can be loaded into the memory.
9.5. Parameters
The following table lists the parameters for the ALTMEMMULT IP core.
Table 39.
WIDTH_D WIDTH_C
ALTMEMMULT Parameters
Parameter Name
Type Required
Description
Integer Yes
Specifies the width of the data_in[] port.
Integer Yes
Specifies the width of the coeff_in[] port. continued…
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9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
Parameter Name WIDTH_R WIDTH
References
- FPGA Documentation Index
- 1. Intel FPGA Integer Arithmetic IP Cores
- 1. About Floating-Point IP Cores
- Does the ALTMULT_COMPLEX IP support unsigned operation in V-series...