intel F-Tile Interlaken FPGA IPDesign Example User Guide
- June 3, 2024
- Intel
Table of Contents
- intel F-Tile Interlaken FPGA IPDesign Example User Guide
- 1. Quick Start Guide
- 2. Design Example Description
- 3. F-Tile Interlaken Intel FPGA IP Design Example User Guide Archives
- 4. Document Revision History for F-Tile Interlaken Intel FPGA IP Design
- Read User Manual Online (PDF format)
- Download This Manual (PDF format)
intel F-Tile Interlaken FPGA IPDesign Example User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.4
IP Version: 3.1.0
1. Quick Start Guide
The F-Tile Interlaken Intel® FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design.
The testbench and design example supports NRZ and PAM4 mode for F-tile
devices.
The F-Tile Interlaken Intel FPGA IP core generates design examples for the
following supported combinations of number of lanes and data rates.
Table 1. IP Supported Combinations of Number of Lanes and Data Rates
The following combinations are supported in the Intel Quartus® Prime Pro
Edition software version 21.4. All
other combinations will be supported in a future version of the Intel Quartus
Prime Pro Edition.
Figure 1. Development Steps for the Design Example
(1) This variant supports the Interlaken Look-aside Mode.
(2) For a 10-lane configuration design, the F-tile requires 12 lanes of TX PMA
to enable bonded transceiver clocking for minimizing the channel skew.
*Other names and brands may be claimed as the property of others.
The F-Tile Interlaken Intel FPGA IP core design example supports the following features:
- Internal TX to RX serial loopback mode
- Automatically generates fixed size packets
- Basic packet checking capabilities
- Ability to use System Console to reset the design for re-testing purpose
Figure 2. High-level Block Diagram
Related Information
- F-Tile Interlaken Intel FPGA IP User Guide
- F-Tile Interlaken Intel FPGA IP Release Notes
1.1. Hardware and Software Requirements
To test the example design, use the following hardware and software:
-
Intel Quartus Prime Pro Edition software version 21.4
-
System console available with the Intel Quartus Prime Pro Edition software
-
A supported simulator:
— Synopsys VCS
— Synopsys VCS MX
— Siemens EDA ModelSim SE or Questa
— Cadence Xcelium* -
Intel Agilex™ I-Series Transceiver-SoC Development Kit
1.2. Generating the Design
Figure 3. Procedure
Follow these steps to generate the design example and testbench:
- In the Intel Quartus Prime Pro Edition software, click File ➤ New Project Wizard to create a new Intel Quartus Prime project, or click File ➤ Open Project to open an existing Intel Quartus Prime project. The wizard prompts you to specify a device.
- Specify the device family Agilex and select device with F-Tile for your design.
- In the IP Catalog, locate and double-click F-Tile Interlaken Intel FPGA IP. The New IP Variant window appears.
- Specify a top-level name
for your custom IP variation. The parameter editor saves the IP variation settings in a file named .ip. - Click OK. The parameter editor appears.
Figure 4. Example Design Tab
6. On the IP tab, specify the parameters for your IP core variation.
7. On the Example Design tab, select the Simulation option to generate the
testbench. Select the Synthesis option to generate the hardware design
example. You must select at least one of the Simulation and Synthesis options
to generate the design example.
8. For Generated HDL Format, both Verilog and VHDL option is available.
9. For Target Development Kit, select the Agilex I-Series Transceiver-SOC
Development Kit.
Note: When you select the Development Kit option, the pin assignments are set
according to the Intel Agilex I-Series Transceiver-SoC Development Kit device
part number (AGIB027R31B1E2VR0) and may differ from your selected device. If
you intend to test the design on hardware on a different PCB, select No
development kit option and make the appropriate pin assignments in the .qsf
file
10. Click Generate Example Design. The Select Example Design Directory window
appears.
11. If you want to modify the design example directory path or name from the
defaults displayed (ilk_f_0_example_design), browse to the new path and type
the new design example directory name.
12. Click OK.
Note: In the F-Tile Interlaken Intel FPGA IP design example, a SystemPLL is instantiated automatically, and connected to F-Tile Interlaken Intel FPGA IP core. The SystemPLL hierarchy path in the design example is:
example_design.test_env_inst.test_dut.dut.pll
The SystemPLL in the design example shares the same 156.26 MHz reference clock as the Transceiver.
1.3. Directory Structure
The F-Tile Interlaken Intel FPGA IP core generates the following files for the
design
example:
Figure 5. Directory Structure
Table 2. Hardware Design Example File Descriptions
These files are in the
Table 3. Testbench File Description
This file is in the
Table 4. Testbench Scripts
These files are in the
1.4. Simulating the Design Example Testbench
Figure 6. Procedure
Follow these steps to simulate the testbench:
- At the command prompt, change to the testbench simulation directory. The directory path is
/example_design/testbench. - Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Your script should check that the SOP and EOP counts match after simulation is complete.
Table 5. Steps to Run Simulation
3. Analyze the results. A successful simulation sends and receives packets,
and displays “Test PASSED”.
The testbench for the design example completes the following tasks:
-
Instantiates the F-Tile Interlaken Intel FPGA IP core.
-
Prints PHY status.
-
Checks metaframe synchronization (SYNC_LOCK) and word (block) boundaries
(WORD_LOCK). -
Waits for individual lanes to be locked and aligned.
-
Starts transmitting packets.
-
Checks packet statistics:
— CRC24 errors
— SOPs
— EOPs
The following sample output illustrates a successful simulation test run:
Note: The Interlaken design example simulation testbench sends 100 packets and receives 100 packets.
The following sample output illustrates a successful simulation test run for Interlaken Look-aside mode:
1.5. Compiling and Configuring the Hardware Design Example
- Ensure the example design generation is complete.
- In the Intel Quartus Prime Pro Edition software, open the Intel Quartus Prime project
/example_design.qpf>. - On the Processing menu, click Start Compilation.
- After successful compilation, a .sof file is available in your specified directory.
Follow these steps to program the hardware example design on the Intel Agilex device with F-tile:
a. Connect the Development Kit to the host computer.
b. Launch the Clock Control application, which is part of the development kit. Set new frequencies for the design example as following:
• For NRZ mode:
— Si5391 (U18), OUT0: Set to the value of pll_ref_clk(3) per your design requirement.
• For PAM mode:
— Si5391 (U45), OUT1: Set to the value of pll_ref_clk(3) per your design requirement.
— Si5391 (U19), OUT1: Set to the value of mac_pll_ref_clk(3) per your design requirement. c. Click Tools ➤ Programmer ➤ Hardware Setup.
d. Select a programming device. Add the Intel Agilex I-Series Transceiver-SoC Development Kit.
e. Ensure that Mode is set to JTAG.
f. Select the Intel Agilex I-Series device and click Add Device. The programmer displays a diagram of the connections between the devices on your board.
g. Check the box for the . sof.
h. Check the box in the Program/Configure column.
i. Click Start.
1.6. Testing the Hardware Design Example
After you compile the F-tile Interlaken Intel FPGA IP design example and
configure your device, you can use the System Console to program the IP core
and its registers.
Follow these steps to bring up the System Console and test the hardware design example:
- No errors for CRC32, CRC24, and checker.
- Transmitted SOPs and EOPs should match with the received SOPs and EOPs.
The following sample output illustrates a successful test run in Interlaken mode:
The following sample output illustrates a successful test run in Interlaken Lookaside mode:
2. Design Example Description
The design example demonstrates the functionalities of the Interlaken IP core.
2.1. Design Example Components
The example design connects system and PLL reference clocks and required
design components. The example design configures the IP core in internal
loopback mode and generates packets on the IP core TX user data transfer
interface. The IP core sends these packets on the internal loopback path
through the transceiver.
After the IP core receiver receives the packets on the loopback path, it processes the Interlaken packets and transmits them on the RX user data transfer interface. The example design checks that the packets received and transmitted match.
The F-Tile Interlaken Intel FPGA IP design example includes the following components:
- F-Tile Interlaken Intel FPGA IP core
- Packet Generator and Packet Checker
- F-Tile Reference and System PLL Clocks Intel FPGA IP core
2.2. Design Example Flow
The F-Tile Interlaken Intel FPGA IP hardware design example completes the
following steps:
- Reset the the F-tile Interlaken Intel FPGA IP and F-Tile.
- Release the reset on Interlaken IP (system reset) and F-tile TX (tile_tx_rst_n).
- Configures the F-tile Interlaken Intel FPGA IP in the internal loopback mode.
- Release the reset of F-tile RX (tile_rx_rst_n).
- Sends a stream of Interlaken packets with predefined data in the payload to the TX user data transfer interface of the IP core.
- Checks the received packets and reports the status. The packet checker included in the hardware design example provides the following basic packet checking capabilities:
• Check that the transmitted packet sequence is correct.
• Checks that the received data matches the expected values by ensuring both the start of packet (SOP) and end of packet (EOP) counts align while data is being transmitted and received.
*Other names and brands may be claimed as the property of others.
2.3. Interface Signals
Table 6. Design Example Interface Signals
2.4. Register Map
Note:
- Design Example register address starts with 0x20 while the Interlaken IP core register address starts with 0x10.
- F-tile PHY register address starts with 0x30 while the F-tile FEC register address starts with 0x40. FEC register is only available in PAM4 mode.
- Access code: RO—Read Only, and RW—Read/Write.
- System console reads the design example registers and reports the test status on the screen.
Table 7. Design Example Register Map
Table 8. Design Example Register Map for Interlaken Look-aside Design
Example
Use this register map when you generate the design example with Enable
Interlaken Look-aside Mode parameter turned on.
2.5. Reset
In the F-Tile Interlaken Intel FPGA IP core, you initiate the reset
(reset_n=0) and hold until the IP core returns a reset acknowledge
(reset_ack_n=0). After the reset is removed (reset_n=1), the reset acknowledge
returns to its initial state (reset_ack_n=1). In the design example, a
rst_ack_sticky register holds the reset acknowledge assertion and then
triggers the removal of the reset (reset_n=1). You can use alternative methods
that fit your design needs.
Important: In any scenario where the internal serial loopback is required, you must release TX and RX of the F-tile separately in a specific order. Refer to the system console script for more information.
Figure 7. Reset Sequence in NRZ Mode
Figure 8. Reset Sequence in PAM4 Mode
3. F-Tile Interlaken Intel FPGA IP Design Example User Guide Archives
If an IP core version is not listed, the user guide for the previous IP core version applies.
4. Document Revision History for F-Tile Interlaken Intel FPGA IP Design
Example User Guide
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performance of its FPGA and semiconductor products to current
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