SIEMENS GT 2 Smartwatch User Guide

Table of Contents

Supporting eMRAM technology in a high-volume production environment requires:
- automation to optimize the DFT implementation.
- integrated ECC and repair capabilities to improve yield and durability.

Outline

Introduction to MRAM, industry landscape
MRAM testing challenges
- ECC-aware Test and Repair technology
- Automated Read self-trimming
Summary and Conclusion
Introduction to MRAM, industry landscape
MRAM testing challenges
- ECC-aware Test and Repair technology
- Automated Read self-trimming
- Summary and Conclusion

What is (STT-) MRAM?
CMOS-friendly, fast, dense and low mask adder non-volatile memory

MRAM stands for Magneto-resistive RAM Magnetic polarization sets the memory state
STT stands for Spin Transfer Torque Electron spin is used to switch magnetic polarization
1T-1MTJ bitcell
Allows dense configuration and scalability MTJ in metal stack enables low mask count add.

Memory element Perpendicular Magnetic Tunnel Junction (pMTJ)

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Wearables, fusion processors & microcontrollers, AI/ML acceleration.

AmbiqApollo 4 SoCs

2MB 22nm MRAM Arm® Cortex®-M4F core SIEMENS GT 2 Smartwatch
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Alif Semiconductor Ensemble™Family

Up to 5.5MB MRAM. Arm® Cortex®-M55, A32 Arm Ethos™-U55 microNPUsfor AI/ML acceleration.

Sony Semiconductor Solutions

GPS/GNSS receiver/processor chips 2MB 28nm MRAM.

Arm collaborated with Siemens EDA to develop an automated solution for handing embedded MRAM technology
- Goal is to help bring a new industry standard testing solution to market
Arm provides an MRAM compiler IP for Samsung 28nm FDSOI technology
- IP was used as the basis to validate the new automated MBIST technology

Outline

Introduction to MRAM, industry landscape
MRAM testing challenges
- ECC-aware Test and Repair technology
- Automated Read self-trimming
Summary and Conclusion

Write operation is stochastic in nature, so in-field failures can occur
Some bit cells are defective upon manufacturing, and ECC is a better option to “repair” them instead of using spare elements
A typical scenario is to use two-bit error correction, where one ECC bit is used to repair single-bit fails during manufacturing, leaving at least one error correction capability for in-field correction.

ECC-aware test and repair technology

Hardware architecture to support MRAM

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How to avoid ECC test escapes SIEMENS GT 2 Smartwatch
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ECC test escape mitigation with error accumulation

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Overview of three main tests

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MBIST pre/post-repair tests

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Outline

Introduction to MRAM, industry landscape
MRAM testing challenges
- ECC-aware Test and Repair technology
- Automated Read self-trimming
Summary and Conclusion

Memory BIST solution to enable reference trimming

Trimming is the process of determining a reference value, which decides if the read (electrical) value must be interpreted as a logical ‘0’ or as a logical ‘1’.
For MRAM, whose storage elements are resistance-based, trimming is done to determine a specific reference resistance.
This reference value cannot be determined up-front with high confidence but must be learned, preferably on-chip by using fully autonomous circuitry for each memory and sense amplifier.

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Automated Read self-trimming test flow

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Outline

Introduction to MRAM, industry landscape
MRAM testing challenges
- ECC-aware Test and Repair technology
- Automated Read self-trimming
Summary and Conclusion

We demonstrated the effectiveness of the automated ECC-aware test and repair technology.
The same technology is applicable to all types of RAM.
The technology allows us to trade-off simple error correction using ECC versus using repair resources during manufacturing test.
Performing online/offline MBIST testing to detect errors before they become uncorrectable enables us to secure yield on our most advanced technology nodes.