QUECTEL RG500L Series MediaTek Based 5G Module User Guide

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The execution of AT+CFUN command will not affect GNSS function. For more details about AT commands, see Chapter 9.1.

3.4. Power Supply
3.4.1. Power Supply Pins
The module provides 7 VBAT pins dedicated to the connection with the external power supply and provides power supply for external GPIO’s pull-up circuits with VDD_EXT. There are two separate voltage domains for VBAT and one voltage for external circuits.
Four VBAT_RF1 pins for RF part. Three VBAT_BB pins for baseband part. One VDD_EXT pin for external GPIO’s pull-up circuits

Table 8: Pin Definition of Power Supply

Pin Name VBAT_BB VBAT_RF1 VDD_EXT

Pin No.

I/O

235, 236, 238

PI

229, 230, 232, 233 PI

66

PO

Description
Power supply for the module’s baseband part Power supply for the module’s RF part Provide 1.8 V for external circuit

Comment
Power supply for external GPIO’s pull-up circuits.

3.4.2. Reference Design for Power Supply
The performance of the module largely depends on the power source. The power supply of the module should be able to provide sufficient current of 4.5 A at least. If the voltage difference between input and output is not too high, it is suggested that an LDO should be used to supply power to the module. If there is a big voltage difference between input and the desired output VBAT, a buck converter is preferred as the power supply.

The following figure illustrates a reference design for +5 V input power source. RG500L_Series_QuecOpen_Hardware_Design

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VCC_5 V D1

R3

51K

C1

C2

C3

470 F 10 F 100 nF

Q1 3V8_EN R1 4.7K
R2 47K

PGND PGND AGND PVIN PVIN PVIN EN SS/TR

U1 GND

C6 3.3 nF

SW SW SW VOS PG FB FSW DEF

L1 2.2 H

R4

100K

R5

75K

R6 20K

DC_3V8

C4

C5

22 F 100 nF

Figure 3: Reference Design of Power Supply

3.4.3. Requirements for Voltage Stability
The power supply range of the module is from 3.3 V to 4.3 V. Please make sure the input voltage will never drop below 3.3 V.

Burst Transmission

Burst Transmission

VBAT

Drop

Ripple

Figure 4: Power Supply Limits during Burst Transmission
To decrease voltage drop, a bypass capacitor of about 470 F with low ESR (ESR = 0.7 ) should be used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It is recommended to use ceramic capacitors for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application must be a single voltage source and can be expanded to two sub paths with the star structure. The width of VBAT_BB trace should be no less than 2.5 mm. The width of VBAT_RF trace should be no less than 3 mm. In principle, the longer the VBAT trace is, the wider it should be.

In addition, to ensure the stability of the power supply, it is necessary to add a high-power TVS diode at the front end of the power supply. Reference circuit is shown as below:

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VBAT

R1 0R

R2 0R

C1 C2

C3

C4

C5

470 F 100 nF 6.8 nF 220 pF 68 pF

VBAT_BB VBAT_RF1 VBAT_RF2

470 F 100 nF 220 pF 68 pF 15 pF 9.1 pF 4.7 pF 470 F 100 nF 220 pF 68 pF 15 pF 9.1 pF 4.7 pF D1

C6 C7 C8 C9 C10 C11 C12

C13 C14 C15 C16 C17 C18 C19

Module

Figure 5: Star Structure of the Power Supply
NO TE To avoid damaging internal flash, do not switch off the power supply when the module works normally. Only after shutting down the module with PWRKEY or PON_1 can you cut off the power supply.

3.5. Turn On
3.5.1. Turn on the Module with PWRKEY

Table 9: Pin Definition of PWRKEY

Pin Name Pin No.

I/O

PWRKEY 7

DI

Description Turn on/off the module

Comment Internally pulled up to 1.8 V.

When the module is in power-off mode, you can turn it on to make it enter normal operation mode by driving PWRKEY low for at least 500 ms. It is recommended to use an open drain/collector driver to control PWRKEY. If PWRKEY is kept low for more than 8 s after turning on the module, the module would reset repeatedly.[JW5]

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500 ms

GPIO MCU

Turn-on pulse

4.7 K

47 K Q1

PWRKEY Module

Figure 6: Reference Circuit of Turing on the Module with Driving Circuit
Another way to control PWRKEY is by using a button directly. When pressing the button, an electrostatic strike may be generated from finger. Therefore, a TVS component shall be placed near the button for ESD protection.
S1 PWRKEY

TVS

Close to S1 Figure 7: Reference Circuit of Turing on the Module with Keystroke

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The turn-on scenario is illustrated in the following figure.
NOTE

5G Module Series

VBAT PWRKEY

500 ms

RESET_N STATUS UART
USB

OD

TBD

TBD

TBD

Active Active

Figure 8: Timing of Turning on the Module

. NOTE
1. Please ensure that VBAT is stable for at least 30 ms before pulling down PWRKEY. 2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.

3.5.2. Turn on the Module with PON_1
When the module is in power-down mode, you can turn it on to normal mode by driving the PON_1 pin high.

Table 10: Pin Definition of PON_1

Pin Name PON_1

Pin No.

I/O

9

DI

Description Turn on/off the module

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3.6. Turn Off
You can use the following ways to turn off the module.

3.6.1. Turn off the Module with PWRKEY
You can turn off the module by driving PWRKEY low for at least 1000 ms and then releasing it. The turn-off scenario is illustrated in the following figure.

VBAT

1000 ms

TBD

PWRKEY

STATUS
Module Status

Running

Power-down procedure

OFF

Figure 9: Timing of Turning off the Module

3.6.2. Turn off the Module with PON_1
You can turn off the module by driving PON_1 low.
NOTE 1. When turning off the module with PON_1, please keep PWRKEY at a high level after the execution
of power-off. Otherwise, the module will be turned on again after power-off. 2. When USB_VBUS is in place, the module always remains in the power-on state. 3. To avoid damaging internal flash, do not switch off the power supply when the module works
normally. Only after shutting down the module with PWRKEY or PON_1, can you cut off the power supply.

3.7. Reset
You can reset the module by driving RESET_N low for at least 250­550 ms* and then releasing it. The

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RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible and surround it with ground.

Table 11: Pin Definition of RESET_N

Pin Name RESET_N

Pin No.

I/O

8

DI

Description Reset the module

Comment
Internally pulled up to 1.8 V. Active low.

The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N.

250­550 ms

GPIO MCU

Reset pulse

4.7 K

47 K Q1

RESET_N Module

Figure 10: Reference Circuit of RESET_N with Driving Circuit

VBAT TBD
TBD RESET_N

Module Status

Running

Resetting

Restart

Figure 11: Timing of Resetting the Module
NO TE 1. Use RESET_N only when you fail to turn off the module with PWRKEY or PON_1. 2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.

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4 Application Interfaces

4.1. USB Interface
The module provides one integrated Universal Serial Bus (USB) interface which complies with the USB 3.0/2.0 specifications and supports super speed (5 Gbps) on USB 3.0, high speed (480 Mbps) and full speed (12 Mbps) modes on USB 2.0. The USB interface is used for AT command communication, data transmission, GNSS NMEA* sentence output, software debugging and firmware upgrade.
Pin definition of the USB interface is as follows:

Table 12: Pin Definition of USB Interface

Pin Name

Pin No. I/O

USB_VBUS

82

AI

USB_DP

83

AIO

USB_DM

85

AIO

USB_SS_TX_P 76

AO

USB_SS_TX_M 74

AO

USB_SS_RX_P 79

AI

USB_SS_RX_M 77

AI

USB_ID

75

DI

OTG_PWR_EN 80

DO

Description
USB connection detect
USB differential data (+) USB differential data (-)

Comment
Used for USB connection detection (disabled by default). Cannot be used for power supply.
Require differential impedance of 90 .

USB 3.0 super-speed transmit (+) USB 3.0 super-speed transmit (-) USB 3.0 super-speed receive (+) USB 3.0 super-speed receive (-)

Require differential impedance of 90 . If unused, connect RX to GND directly.

USB ID detect

OTG power control

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It is recommended to reserve test points for debugging and firmware upgrading in your design.

Minimize these stubs

Test Points

Module

VBUS

R3

NM_0R

R4

NM_0R

USB_VBUS USB_DM USB_DP

R1

0R

R2

0R

USB_SS_TX_P C1 USB_SS_TX_M C2 USB_SS_RX_P

Close to Module 100 nF
100 nF

USB_SS_RX_M

GND

ESD Array
100 nF C3 100 nF C4

USB_DM USB_DP
USB_SS_RX_P USB_SS_RX_M USB_SS_TX_P USB_SS_TX_M
GND

Figure 12: Reference Circuit of USB Interface
To ensure the signal integrity of USB data traces, you must place R1, R2, R3, R4, C1 and C2 close to the module, C3 and C4 close to the device, and keep these resistors close to each other. Keep the extra stubs of traces as short as possible.
To meet the USB specifications, the following principles should be complied with when designing the USB interface,
It is important to route the USB signal traces as differential pairs with ground surrounded. The impedance of USB 2.0/3.0 differential trace is 90 .
For USB 2.0 signal traces, length matching within the differential data pair (between USB_DM and USB_DP) should be less than 0.5 mm. For USB 3.0 signal traces, length matching within each differential data pair (within TX or RX) should be less than 0.125 mm.
Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and ground planes above and below.
Junction capacitance of the ESD protection components might cause influences on USB data traces, so please pay attention to the selection of the device. Typically, the stray capacitance should be less than 3.0 pF for USB 2.0, and less than 0.5 pF for USB 3.0.
If possible, reserve a 0 resistor on USB_DP and USB_DM traces respectively.

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For more details about the USB specifications, please visit http://www.usb.org/home.
NOTE 1. Currently only USB 2.0 interface supports firmware upgrade. 2. When USB_VBUS is in place, the module always remains in the power-on state.

4.2. (U)SIM Interfaces
The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both Class B (3.0 V) and Class C (1.8 V) (U)SIM cards are supported, and Dual SIM Single Standby function is supported.

Table 13: Pin Definition of (U)SIM Interfaces

Pin Name USIM1_VDD USIM1_DATA USIM1_CLK USIM1_RST USIM1_DET USIM2_VDD USIM2_DATA USIM2_CLK USIM2_RST USIM2_DET

Pin No.

I/O

245

PO

248

DIO

247

DO

244

DO

249

DI

250

PO

251

DIO

253

DO

254

DO

252

DI

Description (U)SIM1 card power supply (U)SIM1 card data (U)SIM1 card clock (U)SIM1 card reset (U)SIM1 card hot-plug detect (U)SIM2 card power supply (U)SIM2 card data (U)SIM2 card clock (U)SIM2 card reset (U)SIM2 card hot-plug detect

The module supports (U)SIM card hot-plug via the USIM_DET pin, which is a level-triggered pin. The hot-plug function is disabled by default.

4.2.1. Normally Closed (U)SIM Card Connector
With a normally closed (U)SIM card connector, USIM_DET is normally short- circuited to ground when there is no (U)SIM card inserted. A (U)SIM card insertion will drive USIM_DET from low to high level, and

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the removal of it will drive USIM_DET from high to low level.
When the (U)SIM is absent, CD is short-circuited to ground and USIM_DET is at low level. When the (U)SIM is inserted, CD is open from ground and USIM_DET is at high level.
The following figure shows a reference design of (U)SIM interface with a normally closed (NC) (U)SIM card connector.
VDD_EXT USIM_VDD

100 K

Module

USIM_VDD USIM_RST USIM_CLK USIM_DET

USIM_DATA

33 R 33 R 1 K
33 R

NM 10 pF 1 µF (U)SIM Card Connector

VCC

GND

RST

VPP

CLK Switch IO

CD1

CD2

10 pF 10 pF 10 pF

GND

GND
Figure 13: Reference Circuit of Normally Closed (U)SIM Card Connector

4.2.2. Normally Open (U)SIM Card Connector
With a normally open (U)SIM card connector, USIM_DET is normally open when a (U)SIM card is not inserted. A (U)SIM card insertion will drive USIM_DET from high to low level, and the removal of it will drive USIM_DET from low to high level.
When the (U)SIM is absent, CD1 is open from CD2 and USIM_DET is at high level. When the (U)SIM is inserted, CD1 is short-circuited to ground and USIM_DET is at low level.
The following figure shows a reference design of (U)SIM interface with a normally open (NO) (U)SIM card connector.

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VDD_EXT USIM_VDD

100 K

Module

USIM_VDD USIM_RST USIM_CLK USIM_DET
USIM_DATA

33 R 33 R 1 K
33 R

NM 10 pF 1 µF (U)SIM Card Connector

VCC

GND

RST

VPP

CLK Switch IO

CD1

CD2

10 pF 10 pF 10 pF

GND

GND
Figure 14: Reference Circuit of Normally Open (U)SIM Card Connector

4.2.3. (U)SIM Card Connector Without Hot-Plug
If (U)SIM card detection function is not needed, please keep USIM_DET unconnected.
A reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector without hot-plug function is illustrated in the following figure.

USIM_VDD NM

Module

USIM_VDD USIM_RST USIM_CLK

USIM_DATA

33 R
33 R 33 R

10 pF

1 µF (U)SIM Card Connector

VCC RST CLK

GND VPP
IO

10 pF 10 pF 10 pF

ESD diode

GND

Figure 15: Reference Circuit of a 6-Pin (U)SIM Card Connector

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To enhance the reliability and availability of the (U)SIM card interface in applications, please follow the criteria below in (U)SIM circuit design.
Keep (U)SIM card connector as close as possible to the module. Keep the trace length as less than 200 mm as possible.
Keep (U)SIM card signal traces away from RF and VCC traces. To avoid crosstalk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with ground surrounded. To offer better ESD protection, it is recommended to add a TVS array with a parasitic capacitance not
exceeding 45 pF. The 33 resistors should be added in series between the module and the (U)SIM card connector to suppress EMI spurious transmission and enhance ESD protection. The 10 pF capacitors are used to filter out RF interference. Reserve a 1 µF shunt capacitor on the power rails of (U)SIM and place this capacitor close to the (U)SIM connector.

4.3. I2C Interface
The module provides one I2C interface. As an open drain output, I2C interface should be pulled up to 1.8 V.

Table 14: Pin Definition of I2C Interface

Pin Name

Pin No.

I/O

TP_I2C_SCL

243

OD

TP_I2C_SDA

242

OD

Description I2C serial clock I2C serial data

Comment
Should be externally pulled up to 1.8 V. If unused, keep them open.

4.4. PCM Interfaces
The module provides two PCM interfaces. The key features of the PCM interfaces are listed below:
Used for audio function with external SLIC Supports long frame synchronization/short frame synchronization Supports master and slave modes, but must be the master in long frame synchronization

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Table 15: Pin Definition of PCM Interfaces

Pin Name

Pin No. I/O

Description

Comment

PCM0_SYNC
PCM0_CLK PCM0_DIN PCM0_DOUT PCM1_SYNC PCM1_CLK PCM1_DIN PCM1_DOUT

62

PCM0 data frame DIO

In master mode, they are

sync

output signals. In slave mode,

63

DIO PCM0 clock

they are input signals.

61

DI

PCM0 data input

If unused, keep them open.

59

DO PCM0 data output

217

PCM1 data frame DIO

In master mode, they are

sync

output signals. In slave mode,

215

DIO PCM1 clock

they are input signals.

212

DI

PCM1 data input

If unused, keep them open.

211

DO PCM1 data output

NOTE PCM1 is used for SLIC by default.

4.5. UART Interfaces

The module provides three UART interfaces and the following table shows their features:

Table 16: UART Information

UART Types

Baud Rate

Main UART interface

115200 bps

Debug UART interface

921600 bps

Bluetooth UART interface 115200 bps

Functions AT command communication and data transmission Linux console and log output
Bluetooth communication

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Table 17: Pin Definition of UART Interfaces

Pin Name MAIN_CTS MAIN_RTS MAIN_RXD MAIN_TXD BT_TXD BT_RXD BT_RTS BT_CTS DBG_RXD DBG_TXD

Pin No.

I/O

201

DO

203

DI

202

DI

200

DO

45

DO

276

DI

48

DI

277

DO

205

DI

206

DO

Description

Comment

DTE clear to send signal from DCE DTE request to send signal to DCE

Connect to DTE’s CTS Connect to DTE’s RTS

Main UART receive

Main UART transmit

Bluetooth UART transmit

Bluetooth UART receive

DTE request to send signal to DCE DTE clear to send signal from DCE

Connect to DTE’s RTS Connect to DTE’s CTS

Debug UART receive

Debug UART transmit

The following figure illustrates the reference design for Bluetooth UART interface connection between RG500L series and Wi-Fi/Bluetooth module.

BT_TXD

RG500L

BT_RXD BT_RTS

BT_CTS

BT_UART_RXD
BT_UART_TXD Bluetooth
BT_UART_RTS
BT_UART_CTS

Figure 16: Bluetooth UART Interface Connection
The module provides 1.8 V UART interfaces. A level shift circuit should be used if the application is equipped with a 3.3 V UART interface. The following figure shows a reference design with voltage level translator chip.

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VDD_EXT

0.1 F

MAIN_RTS MAIN_CTS MAIN_TXD MAIN_RXD

VCCA

VCCB

OE

GND

A1

B1

A2

B2

A3 Translator B3

A4

B4

0.1 F

VDD_MCU
RTS_MCU CTS_MCU RXD_MCU TXD_MCU

Figure 17: Reference Circuit with Level Translator Chip

Another example with transistor circuit is shown as below. For the design of circuits shown in dotted lines, see that shown in solid lines, but pay attention to the direction of connection.

Module
MAIN_RXD MAIN_TXD
MAIN_RTS MAIN_CTS
GND

VDD_EXT 10 K
VDD_EXT

4.7 K 1 nF

VDD_EXT

1 nF

10 K

4.7 K VDD_MCU

MCU/ARM
TXD RXD
RTS CTS GND

Figure 18: Reference Circuit with Transistor Circuit
NOTE 1. Transistor circuit solution is not suitable for applications with baud rates exceeding 460 kbps. 2. Please note that the module CTS is connected to the device CTS, and the module RTS is
connected to the device RTS.

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4.6. SDIO Interface
The module provides one SD 3.0 protocol compliant SDIO interface for SD card connection.

Table 18: Pin Definition of SDIO Interface

Pin Name SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 SD_DET
SDIO_PU_VDD

Pin No. 67 64 65 71 70 68 69
72

I/O

Description

Comment

DO

SD card clock

DIO

SD card command

DIO

SDIO data bit 0

DIO

SDIO data bit 1

DIO

SDIO data bit 2

Only used for SD card.

DIO

SDIO data bit 3

SD card hot-plug DI
detect SD card IO pull-up PO power supply

The following figure illustrates a reference design of SD card interface with the module.

Module
SDIO_PU_VDD
SD_DATA3 SD_DATA2 SD_DATA1 SD_DATA0
SD_CLK SD_CMD SD_DET

VDD_EXT

R7 100 K R1 0 R
R2 0 R
R3 0 R R4 0 R
R5 0 R R6 0 R

R8

R9

100 K 100 K

R10 100K

R11 100K

R12 100 K

C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 D7 C6

NM

NM

NM

NM

NM

NM

VDD_3V

• C8 4.7 F

C7 33 pF

D6

SD Card Connector
VDD
CD/DAT3 DAT2 DAT1 DAT0 CLK CMD DETECTIVE VSS

Figure 19: Reference Circuit of SD Card Interface RG500L_Series_QuecOpen_Hardware_Design

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To ensure communication performance with SD card, the following design principles should be complied with:
The voltage range of SD card power supply VDD_3V is 2.7­3.6 V and a sufficient current of up to 0.8 A should be provided. SDIO_PU_VDD is the SDIO bus power domain, which can be used for SD card IO signal pull-up.
To avoid jitter of bus, pull up SD_CMD and SD_DATA to SDIO_PU_VDD with R7­R11. Value of these resistors can be 10­100 k and the recommended value is 100 k.
To improve signal quality, it is recommended to add 0 resistors R1 to R6 in series between the module and the SD card connector. The bypass capacitors C1 to C6 are reserved and not mounted by default. All resistors and bypass capacitors should be placed close to the connector.
For good ESD protection, it is recommended to add a TVS diode with capacitance value less than 3 pF on each SD card pins.
It is important to route the SDIO signal traces with ground surrounded. The impedance of SDIO data trace is 50 (±10 %).
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
It is recommended to keep the trace length difference between SD_CLK and SD_DATA/CMD less than 7.7 mm and the total routing length less than 102 mm. The total trace length inside the module is 18 mm, so the exterior total trace length should be less than 84 mm.
Ensure the adjacent trace spacing is two times the trace width and the load capacitance of SDIO bus should be less than 5 pF.
NOTE
For SD 3.0 SDR104 mode, a sufficient current of up to 800 mA and a 4.7 µF capacitor for the power supply is necessary.

4.7. ADC Interfaces
The module provides three Analog-to-Digital Converter (ADC) interfaces. To improve the accuracy of ADC, the traces of ADC interfaces should be surrounded by ground.

Table 19: Pin Definition of ADC Interfaces

Pin Name ADC0

Pin No. 241

I/O

Description

General-purpose ADC AI
interface

Comment
Max input 1.78 V. If unused, connect it to GND directly.

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ADC1 ADC2

General-purpose ADC

135

AI

interface

Max input 1.45 V.

If unused, connect them to

General-purpose ADC

138

AI

GND directly.

interface

The voltage value on ADC pins can be read via AT+QADC=* command:

AT+QADC=0: read the voltage value on ADC0 AT+QADC=1: read the voltage value on ADC1 AT+QADC=2: read the voltage value on ADC2

For more details about the AT command, see Chapter 9.3.

The resolution of the ADC interfaces is up to 12 bits. The following table describes the voltage range of the ADC interfaces.

Table 20: Voltage Range of ADC Interfaces

ADC Interfaces ADC0 ADC1 ADC2

Min. 0.04 0.05 0.05

Max.

Unit

1.78

V

1.45

V

1.45

V

NOTE
1. The input voltage of ADC should not exceed its corresponding voltage range. 2. It is prohibited to supply any voltage to ADC pin when VBAT is removed. 3. It is recommended to use voltage divider circuit for ADC application.

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4.8. LCM Interface
The module provides an LCM interface, the pin definition of the LCM interface is shown below.

Table 21: Pin Definition of LCM Interface

Pin Name LSDI LSA0 LSCE0B LSRSTB LSCK LSDA PWM LCD_TE LCD_RST

Pin No.

I/O

102

DI

108

DO

105

DO

422

DO

114

DO

111

DO

88

DO

99

DI

93

DO

The following figures show the reference design for LCM interface.

Module
LCD_TE LSCK
LSDA LSA0 LSCE0B LSDI LSRSTB
GND

Description SPI serial input data Indicate transmission of data or command SPI chip select SPI reset SPI serial clock SPI serial output data PWM output (For LCD only) LCM tearing effect LCM reset
LCM
TE SCLK
SDI RS CS SDO RESET GND

Figure 20: Reference Circuit Design for LCM Interface

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PWM
GND
Module

VPH_PWR

C1 2.2 F

Backlight Driver

LCM_LED+ LCM_LED-

Figure 21: Reference Circuit of LCM External Backlight Driver

4.9. SGMII Interfaces
The module includes two integrated Ethernet MAC with two SGMII interfaces and one MDIO management interface. Key features of the SGMII interfaces are shown below:
IEEE 802.3 compliant Full duplex mode for 10/100/1000/2500 Mbps Can be connected to an external Ethernet Switch or PHY, such as MT7531AE and RTL8221B The MDIO management interface and SGMII interrupt/reset signals support 1.8 V power domain

Table 22: Pin Definition of SGMII Interfaces

Pin Name MDIO_DATA MDIO_CLK EPHY0_INT_N EPHY0_RST_N EPHY1_INT_N EPHY1_RST_N SGMII0_RX_M SGMII0_RX_P

Pin No.

I/O

267

DIO

265

DO

410

DI

411

DO

258

DI

261

DO

5

AI

4

AI

Description

Comment

MDIO data

MDIO clock

SGMII0 interrupt

SGMII0 reset

SGMII1 interrupt

SGMII1 reset SGMII0 receive (-) SGMII0 receive (+)

Require differential impedance of 100 .

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SGMII0_TX_P

1

SGMII0_TX_M

2

SGMII1_RX_M

260

SGMII1_RX_P

262

SGMII1_TX_P

264

SGMII1_TX_M

263

5G Module Series

AO

SGMII0 transmit (+) If unused, connect

RX to GND directly.

AO

SGMII0 transmit (-)

AI

SGMII1 receive (-)

AI

SGMII1 receive (+)

AO

SGMII1 transmit (+)

AO

SGMII1 transmit (-)

Module

EPHY_INT_N

Control

EPHY_RST_N MDIO_DATA

MDIO_CLK

SGMII_RX_P

SGMII_RX_M
SGMII Data
SGMII_TX_P

100 nF

SGMII_TX_M 100 nF

R1

NM

VDD_EXT

R2

10 K

PHY
INT RSTN MDIO MDC

100 nF TX_P 100 nF TX_M
RX_P RX_M

Figure 22: Reference Circuit of SGMII Interface with PHY Application
To enhance the reliability and availability of customers’ application, please follow the criteria below in the Ethernet PHY circuit design:
Keep SGMII data and control signals away from RF and VBAT traces. Keep the maximum trace length less than 150 mm and keep length matching within each differential pair
less than 0.125 mm. The differential impedance of SGMII data traces is 100 ±10%. To minimize crosstalk, the distance between separate adjacent pairs on the same layer must be equal to
or larger than 1 mm. Less than 2 vias should be designed in each differential pair. Reserve enough GND plane between MDC and MDIO to prevent crosstalk.

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5G Module Series 0.1 µF AC coupling capacitors should be placed close to the transmitter source.

4.10. SPI Interfaces
The module provides two SPI interfaces which supports slave mode* and master mode with a maximum clock frequency of up to 52 MHz.

Table 23: Pin Definition of SPI Interfaces

Pin Name SPI0_CS SPI0_CLK

Pin No.

I/O

255

DO

257

DO

SPI0_MOSI*

259

DO

SPI0_MISO*

256

DI

SPI3_CS

218

DO

SPI3_CLK

220

DO

SPI3_MOSI

223

DO

SPI3_MISO

221

DI

Description
SPI0 chip select
SPI0 clock SPI0 master-out slave-in SPI0 master-in salve-out SPI3 chip select
SPI3 clock SPI3 master-out slave-in SPI3 master-in salve-out

Comment

The module provides 1.8 V SPI interfaces. A level translator between the module and the host should be used if the application is equipped with a 3.3 V processor or device interface.

VDD_EXT

0.1 F

SPI_CS SPI_CLK SPI_MOSI SPI_MISO

VCCA

VCCB

OE

GND

A1

B1

Translator

A2

B2

A3

B3

A4

B4

NC

NC

0.1 F

VDD_MCU
SPI_CS_N_MCU SPI_CLK_MCU SPI_MOSI_MCU SPI_MISO_MCU

Figure 23: Reference Circuit of SPI Interface with a Level Translator

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5G Module Series

4.11. PCIe Interfaces
The module provides four integrated PCIe (Peripheral Component Interconnect Express) interfaces which follow PCI Express Base Specification Revision 3.0. The key features of the PCIe interfaces are listed below:
PCI Express Base Specification Revision 3.0 compliant Data rate at 8 Gbps per lane Only supports Root Complex mode Can be used to connect to an external Ethernet IC (MAC and PHY) or WLAN IC

Table 24: Pin Definition of PCIe Interfaces

Pin Name PCIE0_REFCLK_P

Pin No. I/O

56

AO

PCIE0_REFCLK_M

55

AO

PCIE0_TX_M

50

AO

PCIE0_TX_P

49

AO

PCIE0_RX_M

52

AI

PCIE0_RX_P

53

AI

PCIE0_CLKREQ_N

281

DI

PCIE0_RST_N

54

DO

PCIE0_WAKE_N

60

DI

PCIE1_REFCLK_P

46

AO

PCIE1_REFCLK_M

44

AO

PCIE1_TX0_M

34

AO

PCIE1_TX0_P

32

AO

PCIE1_RX0_M

38

AI

PCIE1_RX0_P

40

AI

PCIE1_CLKREQ_N

273

DI

Description PCIe0 reference clock (+) PCIe0 reference clock (-) PCIe0 transmit (-)
PCIe0 transmit (+)
PCIe0 receive (-)

Comment
Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly.

PCIe0 receive (+)

PCIe0 clock request

PCIe0 reset

PCIe0 wake up PCIe1 reference clock (+) PCIe1 reference clock (-) PCIe1 transmit (-)
PCIe1 transmit (+)
PCIe1 receive (-)

Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly.

PCIe1 receive (+)

PCIe1 clock request

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PCIE1_RST_N

27

PCIE1_WAKE_N

30

PCIE2_REFCLK_P

29

PCIE2_REFCLK_M

28

PCIE2_TX_M

25

PCIE2_TX_P

26

PCIE2_RX_M

22

PCIE2_RX_P

23

PCIE2_CLKREQ_N

21

PCIE2_RST_N

18

PCIE2_WAKE_N

270

PCIE3_REFCLK_P*

13

PCIE3_REFCLK_M*

11

PCIE3_TX_M*

14

PCIE3_TX_P*

16

PCIE3_RX_M*

17

PCIE3_RX_P*

19

PCIE3_CLKREQ_N*

15

PCIE3_RST_N*

269

PCIE3_WAKE_N*

268

5G Module Series

DO

PCIe1 reset

DI

PCIe1 wake up

PCIe2 reference AO
clock (+)

PCIe2 reference

AO clock (-)

Require differential

impedance of 85 .

AO

PCIe2 transmit (-)

PCIe Gen3 compliant.

AO

PCIe2 transmit (+)

If unused, connect RX to

GND directly.

AI

PCIe2 receive (-)

AI

PCIe2 receive (+)

DI

PCIe2 clock request

DO

PCIe2 reset

DI

PCIe2 wake up

PCIe3 reference AO
clock (+)

PCIe3 reference

AO clock (-)

Require differential

impedance of 85 .

AO

PCIe3 transmit (-)

PCIe Gen3 compliant.

AO

PCIe3 transmit (+)

If unused, connect RX to

GND directly.

AI

PCIe3 receive (-)

AI

PCIe3 receive (+)

DI

PCIe3 clock request

DO

PCIe3 reset

DI

PCIe3 wake up

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The following figure illustrates the PCIe interface connection.
VDD_EXT

5G Module Series

R1 100K

PCIE_CLKREQ_N

PCIE_WAKE_N

PCIE_RST_N

RG500L

PCIE_REFCLK_P
PCIE_REFCLK_M
C1
PCIE_TX_M 220nF
C2
PCIE_TX_P 220nF

PCIE_RX_M

PCIE_RX_P

R2 100K

R3 NM_100K

RR44 4499..99 RR ++//–11%%
RR55 4499..99 RR ++//–11%%
C3 220nF
C4 220nF

PCIE_CLKREQ_N PCIE_WAKE_N PCIE_RST_N PCIE_REFCLK_P PCIE_REFCLK_M PCIE_RX_M PCIE_RX_P PCIE_TX_M PCIE_TX_P

Device

Figure 24: Reference Circuit of PCIe Interface
The following principles of PCIe interface design should be complied with to meet PCIe specifications.
It is important to route the PCIE_TX/RX/REFCLK signal traces as differential pairs with ground surrounded. The differential impedance is 85 is recommended.
PCIe signals must be protected from noisy signals (clocks, DC-DC, RF and so forth). All other sensitive/high-speed signals and circuits must be routed far away from PCIe traces.
For each differential pair, intra-lane length matching should be less than 0.125 mm. Inter-lane length matching, that is, (the trace length matching between the PCIE_TX/RX/REFCLK
pairs) is not required. The PCIe inter-lane spacing, and the spacing between PCIe lanes and all other signals, should be
larger than 4 times the trace width. It is better to place the PCIe AC coupling capacitors close to the transmitter source. Ensure not to stagger the capacitors. This can affect the differential integrity of the design and can
create EMI. PCIe TX AC coupling capacitors should be 220 nF for Gen 3, and 100 nF is recommended for Gen 2
application. To reduce the probability for layer-to-layer manufacturing variation, minimize layer transitions on the
main route (in other words, apply layer transitions only at module breakouts and connectors to

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5G Module Series
ensure minimum layer transitions on the main route). Hardware acceleration is supported by PCIe0 and PCIe1 only. For the PCIE_REFCLK pair, add resistors near the slot (EP) side and the recommended resister
value is 49.9 +/-1 %.

4.12. WWAN/WLAN Control Interface

Table 25: Pin Definition of WWAN/WLAN Control Interface

Pin Name WLAN_SYSRST_5G

Pin No. I/O

271

DO

WIFI_2.4G_EN*

272

DO

WLAN_SYSRST_2.4G 274

DO

WLAN_5G_EN*

406

DO

BT_ACT_TXD 8

36

DO

BT_PRI_RXD 8

275

DO

WLAN_ACT

39

DI

PTA_TX

279

DO

PTA_RX

278

DO

GPIO_15

280

DI

Description

Comment

WLAN 5 GHz system reset

WLAN 2.4 GHz function enable Reserved.
control

WLAN 2.4 GHz system reset

WLAN 5 GHz function enable control Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 2.4 GHz Wi-Fi Coexistence interface for WWAN and 2.4 GHz Wi-Fi
Coexistence interface for WWAN and 2.4 GHz Wi-Fi

Reserved.
Used for WWAN/WLAN coexistence by default.
Used for WWAN/WLAN coexistence by default.

8 Please note that this pin is for WWAN and Wi-Fi coexistence function, not for WWAN and Bluetooth coexistence function.

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5G Module Series

4.13. USB_BOOT Interface

Table 26: Pin Definition of USB_BOOT Interface

Pin Name USB_BOOT

Pin No.

I/O

81

DI

Description Force the module into emergency download mode

The module provides a USB_BOOT pin. You can pull up USB_BOOT to VDD_EXT before powering on the module, and then the module will enter emergency download mode when powered on. In this mode, the module supports firmware upgrade over USB 2.0 interface.

Module

USB_BOOT

Test point

VDD_EXT
1 K

TVS

TVS

Close to test point

Figure 25: Reference Circuit of USB_BOOT Interface

NOTE
It is not recommended to pull up USB_BOOT to 1.8 V before powering up VBAT. Directly connecting the test points as shown in the above figure can manually force the module to enter download mode.

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4.14. Control Signals

Table 27: Pin Definition of Control Signals

Pin Name RESTORE_KEY WPS_KEY*

Pin No. 207 204

Reference circuit is shown as below.

S2

5G Module Series

I/O

Description

DI

Restore the module

DI

Wi-Fi protected setup

KEY

TVS

Close to S2 Figure 26: Reference Circuit of KEY

4.15. Indication Signals

Table 28: Pin Definition of Indication Signals

Pin Name STATUS NET_MODE*

Pin No. I/O

222

OD

219

DO

NET_STATUS* 239

OD

AIR_MODE*

225

OD

WIFI_MESH*

210

DO

Description

Comment

Indicate the module’s operation status
Indicate the module’s network registration mode Indicate the module’s network activity status
Indicate the module’s airplane mode

PMIC_ISINK3
PMIC_ISINK2 PMIC_ISINK1

Indicate the Wi-Fi mesh function status

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USIM_LED*

216

VOIP_LED*

213

Indicate the (U)SIM card function DO
status DO Indicate the VoIP function status

5G Module Series

4.15.1. STATUS
The STATUS pin is an open drain output to indicate the module’s operation status. It will output low level when the module is powered ON successfully.
A reference circuit is shown as below.

Module

VBAT

STATUS

2.2K

Figure 27: Reference Circuit of STATUS Indicator

4.15.2. Network Status Indication*
The network indication pins can be used to drive network status indication LEDs. The module provides two network indication pins: NET_MODE and NET_STATUS. The following tables describe pin definition and logic level changes in different network status.

Table 29: Working Mechanism of Network Registration Mode/Network Activity Indication

Pin Name NET_MODE NET_STATUS

Status Always High Always Low Flicker slowly (200 ms High/1800 ms Low) Flicker slowly (1800 ms High/200 ms Low)

Description Registered on 5G network Others Network searching Idle

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5G Module Series

Flicker quickly (125 ms High/125 ms Low) Always High

Data transfer is ongoing Voice calling

Reference circuit is shown as below.

VBAT
Module

NET_MODE

2.2 K
4.7 K 47 K

Figure 28: Reference Circuit of NET_MODE Indicator

Module

VBAT

2.2K

NET_STATUS

Figure 29: Reference Circuit of NET_STATUS Indicator
4.15.3. AIR_MODE*
The AIR_MODE pin is an open drain output for indicating the module’s flight mode status. It will output low level when the module enters airplane mode successfully.

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A reference circuit is shown as below.
Module

VBAT

AIR_MODE

2.2K

5G Module Series

Figure 30: Reference Circuit of AIR_MODE Indicator

4.15.4. Other Indication Signals*
The WIFI_MESH, USIM_LED and VOIP_LED pins are output signals for indicating the functional state of the module.
A reference circuit is shown as below.

VBAT
Module

2.2 K

Indicator

4.7 K 47 K

Figure 31: Reference Circuit of Other Indicators

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5G Module Series

5 RF Specifications

5.1. Cellular Network

5.1.1. Antenna Interfaces & Frequency Bands
The module provides 8 cellular antenna interfaces and the pin definition is shown below:

Table 30: Pin Definition of Cellular Antenna Interfaces

Pin Name ANT0 ANT1 ANT2 ANT3 ANT4 ANT5 ANT6 ANT7

Pin No.

I/O

121

AIO

130

AIO

139

AI

148

AI

157

AI

166

AI

175

AIO

184

AIO

Description Antenna 0 interface Antenna 1 interface Antenna 2 interface Antenna 3 interface Antenna 4 interface Antenna 5 interface Antenna 6 interface Antenna 7 interface

Comment 50 impedance.

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Table 31: Operating Frequency of RG500L-EU

Operating Frequency
IMT (2100)

Transmit (MHz)
1920­1980

Receive (MHz)
2110­2170

5G NR n1

DCS (1800)

1710­1785

1805­1880 n3

Cell (850)

824­849

869­894

n5

IMT-E (2600) 2500­2570

2620­2690 n7

EGSM (950) 880­915

925­960

n8

EU800

832­862

791­821

n20

700 APAC

703­748

758­803

n28

L-band

–

1452­1496

B38

2570­2620

2570­2620 n38

B40

2300­2400

2300­2400 n40

B41/B41-XGP 2496­2690

2496­2690 n41

B42

3400­3600

3400­3600

B43

3600­3800

3600­3800

n77

3300­4200

3300­4200 n77

n78

3300­3800

3300­3800 n78

Table 32: Operating Frequency of RG500L-NA

Operating Frequency
PCS (1900)

Transmit (MHz)
1850­1910

Receive (MHz)
1930­1990

5G NR n2

B4

1710­1755

2110­2155 –

Cell (850)

824­849

869­894

n5

IMT-E (2600) 2500­2570

2620­2690 n7

B12

699­716

729­746

n12

RG500L_Series_QuecOpen_Hardware_Design

5G Module Series

LTE

UMTS

B1

B1

B3

B5

B5

B7

B8

B8

B20

B28

B32

B38

B40

B41

B42

B43

LTE

UMTS

B2

–

B4

–

B5

–

B7

–

B12

–

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B13

777­787

746­756

–

B14

788­798

758­768

–

B17

704-716

734­746

–

B25

1850-1915

1930-1995

n25

B26

814-849

859-894

–

B29

–

717-728

–

B30

2305-2315

2350-2360

–

B38

2570-2620

2570-2620

n38

B41

2496-2690

2496-2690

n41

B42

3400-3600

3400-3600

–

B43

3600-3800

3600-3800

–

B46

–

5150-5925

–

B48

3550-3700

3550-3700

n48

B66

1710-1780

2110-2200

n66

B71

663-698

617-652

n71

n77

3300­4200

3300­4200 n77

n78

3300­3800

3300­3800 n78

5G Module Series

B13

–

B14

–

B17

–

B25

–

B26

–

B29

–

B30

–

B38

–

B41

–

–

–

B43

–

B46

–

B48

–

B66

–

B71

–

–

–

–

–

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5G Module Series

Table 33: RG500L-EU Cellular Antenna Mapping

Antenna WCDMA LTE

ANT0 ANT1 ANT2

B1 TRX

B42/B43_TRX MHB TRX0 9 B42/B43 DRX1

5G NR

Refarmed

n41 n77/n78

n1/n3/n7/n38/n40 TRX0 n28 TRX0 10

n77/n78 TRX0 TRX0
n77/n78 DRX0

ANT3 ANT4 ANT5

B5/B8 DRX

B42/B43 PRX1
MHB DRX1 LB DRX B32 DRX
MHB PRX1

n1/n3/n7/n38/n40 DRX1 n5/n8/n20/n28 DRX
n1/n3/n7/n38/n40 PRX1

n77/n78 PRX1 DRX0 PRX0

ANT6 ANT7

B42/B43 DRX

B1 DRX B5/B8 TRX

MHB TRX1 9 LB TRX0

n1/n3/n7/n38/n40 TRX1 n28 TRX1 10 n5/n8/n20 TRX0

n77/n78 TRX1 TRX1

LB (MHz) MHB (MHz) n77/n78 (MHz) Pin No.

3300­4200

121

703­803

1710­2700

130

3300­4200

139

3300­4200

148

703­960

1450­2700

157

1450­2700

166

3300­4200

175

703­960

1710­2700

184

9 LTE MHB TRX is activated when 5G NR FDD middle/high bands are supported in NSA mode. 10 n28 TRX is activated when 5G NR FDD low bands are supported in NSA mode.
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Table 34: RG500L-NA Cellular Antenna Mapping

Antenna
ANT0 ANT1 ANT2 ANT3 ANT4 ANT5 ANT6

LTE Refarmed

B42/B43/B48 TRX0

MHB DRX0 B5/B26 TRX MHB TRX0 9

n2/n7/n25/n38/n66 TX0 n2/n7/n25/n38/n66 DRX0 n5 TRX

B46 PRX1 B42/B43/B48 PRX1

B46 DRX1 B42/B43/B48 DRX1

B12/B13/B14/B17/B71 DRX MHB DRX1 B29 DRX1

n2/n7/n25/n38/n66 DRX1 n12/n71 DRX

MHB PRX1 B5/B26 DRX

n2/n7/n25/n38/n66 PRX1 n5 DRX

B42/B43/B48 DRX0

5G NR n41
TRX0
DRX1 PRX1

ANT7

B12/B13/B14/B17/B71 TRX MHB TRX0 9 B29 PRX1

n12/n71 TRX n2/n7/n25/n38/n66 TX1 n2/n7/n25/n38/n66 PRX0

TX1 DRX0

n48/n77/n78
n48/n77/n78 TRX0
n48/n77/n78 PRX1 n48/n77/n78 DRX1
n48/n77/n78 TX1 n48/n77/n78 DRX0

5G Module Series

n48/n77/n78 LB (MHz) MHB (MHz)
(MHz)
3300­4200

Pin No.
121

814­894

1710­2690

130

5150­5925

3300­4200

139

5150­5925

3300­4200

148

617­798

1710­2690

157

814­894

1710­2690

166

3300­4200

175

617­798

1710­2690

184

NOTE TRX0/1 = TX + PRX/DRX; DRX1 = DRX MIMO; PRX1 = PRX MIMO

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5G Module Series

5.1.2. Tx Power
The following table shows the RF output power of the module.

Table 35: RG500L Series Tx Power

Bands WCDMA bands LTE bands 5G NR bands 5G NR n41/n77/n78 bands UL MIMO HPUE 11

Max. 24 dBm +1/-3 dB 23 dBm ±2 dB 23 dBm ±2 dB 26 dBm +2/-3 dB

Power Class PC3 PC3 PC3 PC2

5.1.3. Rx Sensitivity
The following table shows conducted RF receiving sensitivity of the module.

Table 36: Conducted RF Receiving Sensitivity of RG500L-EU

Frequency
LTE-FDD B1 (10 MHz) LTE-FDD B3 (10 MHz) LTE-FDD B5 (10 MHz) LTE-FDD B7 (10 MHz) LTE-FDD B8 (10 MHz) LTE-FDD B20 (10 MHz) LTE-FDD B28 (10 MHz) LTE-TDD B38 (10 MHz)

Receiving Sensitivity (Typ.)

Primary

Diversity

SIMO

-98.0

-98.5

-102.0

-98.5

-99.0

-102.0

-99.0

-101.0

-102.0

-96.5

-97.5

-100.0

-99.0

-100.0

-102.0

-98.5

-100.5

-101.5

-98.5

-98.0

-101.5

-98.5

-98.0

-101.0

3GPP Requirement (SIMO 12) -96.3 dBm -93.3 dBm -94.3 dBm -94.3 dBm -93.3 dBm -93.3 dBm -94.3 dBm -96.3 dBm

11 HPUE is only for single carrier. 12 SIMO is a smart antenna technology that uses a single antenna at the transmitter side and multiple antennas at the
receiver side, which improves Rx performance.

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5G Module Series

LTE-TDD B40 (10 MHz)

-98.5

LTE-TDD B41 (10 MHz)

-97.5

LTE-TDD B42 (10 MHz)

-99.0

LTE-TDD B43 (10 MHz)
5G NR-FDD n1 (20 MHz) (SCS: 15 kHz) 5G NR-FDD n3 (20 MHz) (SCS: 15 kHz) 5G NR- FDD n5 (10 MHz) (SCS: 15 kHz) 5G NR-FDD n7 (20 MHz) (SCS: 15 kHz) 5G NR-FDD n8 (10 MHz) (SCS: 15 kHz) 5G NR-FDD n20 (10 MHz) (SCS: 15 kHz) 5G NR-FDD n28 (10 MHz) (SCS: 15 kHz) 5G NR-TDD n38 (20 MHz) (SCS: 30 kHz) 5G NR-TDD n40 (20 MHz) (SCS: 30 kHz) 5G NR-TDD n41 (100 MHz) (SCS: 30 kHz) 5G NR-TDD n77 (100 MHz) (SCS: 30 kHz) 5G NR-TDD n78 (100 MHz) (SCS: 30 kHz)

-99.0 -97 -96 -97 -96 -96 -97 -96 -97 -95 -91 -89 -89

-97.0 -97.5 -99.0 -98.5 -97 -96 -97 -96 -96 -97 -96 -97 -95 -91 -89 -89

-100.0 -101.0 -103.0 -101.5 -100 -99 -100 -99 -99 -100 -99 -100 -98 -94 -92 -92

-96.3 dBm -94.3 dBm -95 dBm -95 dBm -94 dBm -91 dBm -95 dBm -92 dBm -94 dBm -94 dBm -96 dBm -94 dBm -94 dBm -92 dBm -85 dBm -85 dBm

Table 37: Conducted RF Receiving Sensitivity of RG500L-NA

Frequency
LTE-FDD B2 (10 MHz) LTE-FDD B4 (10 MHz)

Receiving Sensitivity (Typ.)

Primary

Diversity

SIMO

-99.0

-99.0

-102.0

-98.0

-98.0

-101.0

3GPP Requirement (SIMO13)
-94.3 dBm
-96.3 dBm

13 SIMO is a smart antenna technology that uses a single antenna at the transmitter side and multiple antennas at the receiver side, which improves Rx performance.

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LTE-FDD B5 (10 MHz)

-100.0

LTE-FDD B7 (10 MHz)

-97.0

LTE-FDD B12 (10 MHz)

-99.0

LTE-FDD B13 (10 MHz)

-98.0

LTE-FDD B14 (10 MHz)

-99.0

LTE-FDD B17 (10 MHz)

-99.0

LTE-FDD B25 (10 MHz)

-99.0

LTE-FDD B26 (10 MHz)

-100.0

LTE-FDD B30 (10 MHz)

-97.0

LTE-TDD B38 (10 MHz)

-98.0

LTE-TDD B41 (10 MHz)

-96.0

LTE-TDD B42 (10 MHz)

-98.0

LTE-TDD B43 (10 MHz)

-97.5

LTE-TDD B48 (10 MHz)

-98.0

LTE-FDD B66 (10 MHz)

-97.5

LTE-FDD B71 (10 MHz)
5G NR-FDD n2 (10 MHz) (SCS: 15 kHz) 5G NR-FDD n5 (10 MHz) (SCS: 15 kHz) 5G NR- FDD n7 (10 MHz) (SCS: 15 kHz) 5G NR-FDD n12 (10 MHz) (SCS: 15 kHz) 5G NR-FDD n25 (10 MHz) (SCS: 15 kHz) 5G NR-TDD n38 (10 MHz) (SCS: 30 kHz) 5G NR-TDD n41 (100 MHz) (SCS: 30 kHz) 5G NR-TDD n48 (100 MHz) (SCS: 30 kHz)
5G NR-FDD n66 (10 MHz)

-100.0 -100 -97 -97 -97 -97 -98 -88 -89 -98

-100.0 -97.0 -99.0 -98.0 -99.0 -99.0 -99.0 -100.0 -97.0 -98.5 -96.5 -97.5 -97.0 -97.0 -98.0 -101.0 -100 -97 -97 -97 -97 -98 -88 -89 -98

RG500L_Series_QuecOpen_Hardware_Design

-103.0 -100.0 -102.0 -101.0 -102.0 -102.0 -102.0 -103.0 -100.0 -101.0 -99.0 -101.0 -100.5 -100.5 -100.5 -103.0 -103 -100 -100 -100 -100 -101 -91 -92 -101

5G Module Series
-94.3 dBm -94.3 dBm -93.3 dBm -93.3 dBm -93.3 dBm -93.3 dBm -92.8 dBm -93.8 dBm -95.3 dBm -96.3 dBm -94.3 dBm -95.0 dBm -95.0 dBm -95.0 dBm -95.8 dBm -93.5 dBm -94.8 dBm -94.8 dBm -94.8 dBm -93.8 dBm -93.3 dBm -97.1 dBm -84.7 dBm -86.7 -96.3 dBm

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(SCS: 15 kHz)

5G NR-FDD n71 (10 MHz)

-97

-97

(SCS: 15 kHz)

5G NR-TDD n77 (100 MHz)

-90

-90

(SCS: 30 kHz)

5G NR-TDD n78 (100 MHz)

-90

-90

(SCS: 30 kHz)

5G Module Series

-100 -93 -93

-94 dBm -85.1 dBm -85.6 dBm

5.1.4. Reference Design
The module provides 8 cellular antenna interfaces for antenna connection.
It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components should be placed as close to the antenna as possible. The capacitors are not mounted by default.

Module
ANT0

R1 0R

C1

C2

NM

NM

… … … …

ANT7

R7 0R

C13

C14

NM

NM

Figure 32: Reference Circuit for Cellular Antenna Interfaces

. NOTE
1. Use a -type circuit for all the antenna circuits to facilitate future debugging. 2. Keep the characteristic impedance of the cellular antenna (ANT0­ANT7) traces as 50 . 3. Keep at least 15 dB isolation between RF antennas to improve the receiving sensitivity, and at least
20 dB isolation between 5G NR UL MIMO antennas. 4. Keep 75 dB isolation between each two antenna traces. 5. Keep digital circuits such as switch mode power supply, (U)SIM card, USB interface, camera

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5G Module Series
module, display connector and SD card away from the antenna traces.
The characteristic impedance depends on the dielectric of PCB, the track width and theground plane spacing. Microstrip type is required. The detail simulation as below.

The RF trace of the test board which was used in the FCC test is defined as below.

Ant0~7 share the same design.
5.2. GNSS
The module includes a fully integrated global navigation satellite system solution that supports GPS/BeiDou/GLONASS/Galileo. The module supports NMEA 0183 protocol, and outputs NMEA* sentences via USB interface (data update rate: 1­5 Hz, 1 Hz by default). For more details about configuration of GNSS function, see document [2].

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5G Module Series

5.2.1. Antenna Interface & Frequency Bands
The following table shows the pin definition, frequency, and performance of GNSS antenna interface.

Table 38: Pin Definition of GNSS Antenna Interface

Pin Name ANT_GNSS

Pin No.

I/O

193

AI

Description
GNSS antenna interface

Comment 50 impedance.

Table 39: GNSS Frequency

Type GPS GLONASS Galileo BeiDou

Frequency 1575.42 ±1.023 (GPS L1) 1176.45 ±10.23 (GPS L5) (RG500L-EU only) 1597.5­1605.8
1575.42 ±2.046
1561.098 ±2.046

Unit MHz

5.2.2. GNSS Performance
Table 40: GNSS Performance
. NOTE
1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes.
2. Re-acquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock.
3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes position within 3 minutes after executing cold start commands.

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5G Module Series

5.2.3. Reference Design
The following is the reference circuit of GNSS antenna.
VDD

Module
ANT_GNSS NM

0.1 F

10 R

GNSS Antenna

47 nH

0 R

100 pF

NM

Figure 33: Reference Circuit of GNSS Antenna Interface
. NOTE
1. You can select an external LDO for power supply according to the active antenna requirements. 2. If the module is designed with a passive antenna, then the VDD circuit is not needed. 3. Keep the characteristic impedance of GNSS antenna trace as 50 . 4. Place the -type matching components as close to the antenna as possible. 5. Keep digital circuits such as switch mode power supply, (U)SIM card, USB interface, camera
module, display connector and SD card away from the antenna traces. 6. Keep 75 dB isolation between GNSS and cellular antenna traces. 7. Keep 15 dB isolation between GNSS and cellular antennas to improve the receiving sensitivity.

5.3. RF Routing Guidelines
For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 . The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures.

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5G Module Series Figure 34: Microstrip Design on a 2-layer PCB Figure 35: Coplanar Waveguide Design on a 2-layer PCB

Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)

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5G Module Series

Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)
To ensure RF performance and reliability, follow the principles below in RF layout design:
Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 .
The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
The distance between the RF pins and the RF connector should be as short as possible and all the right-angle traces should be changed to curved ones. The recommended trace angle is 135°.
There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2 × W). Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers.
For more details about RF layout, see document [3].
5.4. Requirements for Antenna Design

Table 41: Requirements for Antenna Design

Antenna Type GNSS

Requirements
Frequency range: GNSS L1: 1559­1606 MHz GNSS L5: 1166­1187 MHz (RG500L-EU only) Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi

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5G NR/LTE/UMTS

Active antenna embedded LNA gain: < 17 dB
VSWR: 3 Efficiency: > 30% Gain: > 0 dBi Max input power: 50 W Input impedance: 50 Polarization: Vertical Cable insertion loss: < 1 dB: LB (<1 GHz) < 1.5 dB: MB (1­2.3 GHz) < 2 dB: HB (> 2.3 GHz)

5G Module Series

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RF Connector Recommendation
The receptacle dimensions are illustrated as below.

5G Module Series

Figure 38: Dimensions of the Receptacles (Unit: mm)

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5G Module Series The following figure shows the specifications of mating plugs using Ø0.81 mm coaxial cables.

Figure 39: Specifications of Mating Plugs Using Ø0.81 mm Coaxial Cables (Unit: mm)
For more details, please visit https://www.i-pex.com.
5.5.1. Recommended RF Connector for Installation
5.5.1.1. Assemble Coaxial Cable Plug Manually The illustration for plugging in a coaxial cable plug is shown below, = 90° is acceptable, while 90° is not.

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5G Module Series

Figure 40: Plug in a Coaxial Cable Plug
The illustration of pulling out the coaxial cable plug is shown below, = 90° is acceptable, while 90° is not.

Figure 41: Pull out a Coaxial Cable Plug
5.5.1.2. Assemble Coaxial Cable Plug with Jig
The pictures of installing the coaxial cable plug with a jig is shown below, = 90° is acceptable, while 90° is not.

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5G Module Series
Figure 42: Install the Coaxial Cable Plug with Jig
5.5.2. Recommended Manufacturers of RF Connector and Cable
RF connecters and cables by I-PEX are recommended. For more details, visit https://www.i-pex.com.

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5G Module Series

6 Electrical Characteristics & Reliability

6.1. Absolute Maximum Ratings
Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table.

Table 42: Absolute Maximum Ratings

Parameter

Min.

Max.

Unit

VBAT_RF/VBAT_BB

-0.5

5

V

USB_VBUS

0

21

V

Peak Current of VBAT_BB

–

2

A

Peak Current of VBAT_RF

–

2.5

A

Voltage on Digital Pins

-0.3

1.98

V

Voltage at ADC0

-0.5

1.98

V

Voltage at ADC1

0

1.45

V

Voltage at ADC2

0

1.45

V

6.2. Power Supply Ratings

Table 43: The Module’s Power Supply Ratings

Parameter Description

VBAT

VBAT_BB and VBAT_RF

Conditions
The actual input voltages must stay between the minimum and maximum

Min. Typ. Max. Unit

3.3 3.8 4.3

V

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5G Module Series

values.

IVBAT

Peak supply current

Maximum power control level

(during transmission

–

1.5 2

A

at n41

slot)

USB connection USB_VBUS
detection

4.2 5.0 15

V

6.3. Power Consumption

Table 44: Averaged Power Consumption

Mode Power-off RF Disabled Sleep State Idle State

Conditions Power off AT+CFUN=0 (USB 3.0 disable) AT+CFUN=4 (USB 3.0 disable) AT+CFUN=0 (USB 3.0 disable) SA PF = 64 (USB 2.0 active) SA PF = 64 (USB 3.0 active)

Band/Combinations Current Unit

–

80

A

–

120

mA

–

125

mA

–

6.5

mA

–

125

mA

–

125

mA

NOTE
1. Power consumption test is carried out under 3.8 V, 25 °C with EVB and thermal dissipation measures.
2. The power consumption above is for reference only, which may vary among variants of the module. Please contact Quectel Technical Supports for detailed power consumption test report of the specific model.

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6.4. Digital I/O Characteristic

Table 45: 1.8 V I/O Requirements

Parameter VIH VIL VOH VOL

Description Input high voltage Input low voltage Output high voltage Output low voltage

Min. 1.17 -0.3 1.35 –

Table 46: SDIO 1.86 V I/O Requirements

Parameter VIH VIL VOH VOL

Description Input high voltage Input low voltage Output high voltage Output low voltage

Min. 1.27 -0.3 1.4 -0.3

Table 47: (U)SIM 1.8 V I/O Requirements

Parameter USIM_VDD VIH VIL VOH VOL

Description Power supply Input high voltage Input low voltage Output high voltage Output low voltage

Min. 1.65 1.4 0 1.4 0

5G Module Series

Max.

Unit

1.83

V

0.63

V

–

V

0.45

V

Max.

Unit

2.16

V

0.58

V

2.16

V

0.45

V

Max.

Unit

1.95

V

1.9

V

0.27

V

1.9

V

0.27

V

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Table 48: (U)SIM 3.0 V I/O Requirements

Parameter USIM_VDD VIH VIL VOH VOL

Description Power supply Input high voltage Input low voltage Output high voltage Output low voltage

Min. 2.7 2.6 0 2.6 0

5G Module Series

Max.

Unit

3.05

V

3.0

V

0.4

V

3.1

V

0.4

V

ESD Protection
If the static electricity generated by various ways discharges to the module, the module maybe damaged to a certain extent. Thus, please take proper ESD countermeasures and handling methods. For example, wearing anti-static gloves during the development, production, assembly and testing of the module; adding ESD protective component to the ESD sensitive interfaces and points in the product design of the module.
ESD characteristics of the module’s pins are as follows:

Table 49: Electrostatics Discharge Characteristics (25 °C, 45 % Relative Humidity)

Tested Interfaces

Contact Discharge

Air Discharge

Unit

VBAT, GND

±5

±10

kV

All Antenna Interfaces ±4

±8

kV

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6.6. Operating and Storage Temperatures

Table 50: Operating and Storage Temperatures

Parameter Operating Temperature Range14 Extended Operating Temperature Range15 Storage Temperature Range

Min. -30 -40 -40

Typ. +25 +25 –

5G Module Series

Max.

Unit

+70

°C

+85

°C

+90

°C

Thermal Consideration
The module offers the best performance when all internal IC chips are working within their operating temperatures. When the IC reaches or exceeds the maximum junction temperature, the module may still work but the performance and function (such as RF output power, data rate, etc.) will be affected to a certain extent. Therefore, the thermal design should be maximally optimized to ensure all internal ICs always work within in the recommended operating temperature.
The following principles for thermal consideration are provided for reference:
Keep the module away from heat sources on your PCB, especially high-power components such as processor, power amplifier, and power supply.
Do not place large size components in the area where the module is mounted on your PCB to reserve enough place for heatsink installation.
Maintain the integrity of the PCB copper layer and drill as many thermal vias as possible. Follow the principles below when the heatsink is necessary:
– Attach the heatsink to the shielding cover of the module; – Choose the heatsink with adequate fins to dissipate heat; – Choose a TIM (Thermal Interface Material) with high thermal conductivity, good softness and
good wettability and place it between the heatsink and the module; – Fasten the heatsink with four screws to ensure that it is in close contact with the module to
prevent the heatsink from falling off during the drop, vibration test, or transportation.

14 To meet this operating temperature range, additional thermal dissipation improvements are required, such as passive or active heatsink, heat-pipe, vapor chamber, cold-plate etc. Within this operating temperature range, the module can meet 3GPP specifications. 15 To meet this extended temperature range, additional thermal dissipation improvements are required, such as passive or active heatsink, heat-pipe, vapor chamber, cold-plate etc. Within this extended temperature range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again.

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5G Module Series Figure 43: Placement and Fixing of Heatsink

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5G Module Series

Mechanical Information
This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.2 mm unless otherwise specified.
7.1. Mechanical Dimensions
Pin 1

Figure 44: Module Top and Side Dimensions (Unit: mm)

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5G Module Series Pin 1

Figure 45: Module Bottom Dimensions (Bottom View, Unit: mm)
NO TE The package warpage level of the module conforms to the JEITA ED-7306 standard.

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7.2. Recommended Footprint

5G Module Series

Figure 46: Recommended Footprint (Top View, Unit: mm)
. NOTE
Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience.

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7.3. Top and Bottom Views

5G Module Series

Figure 47: Top and Bottom Views of the Module
NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel.

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5G Module Series

Storage, Manufacturing & Packaging

Storage Conditions
The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below.
1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35­60 %.
2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition.
3. The floor life of the module is 168 hours16 in a plant where the temperature is 23 ±5 °C and relative humidity is below 60 %. After the vacuum- sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g. a drying cabinet).
4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:
The module is not stored in Recommended Storage Condition; Violation of the third requirement above occurs; Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours; Before module repairing.
5. If needed, the pre-baking should follow the requirements below:
The module should be baked for 8 hours at 120 ±5 °C; All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be
put in a dry environment such as in a drying oven.

16 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start th

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