MICROCHIP H.264 4K I-Frame Encoder IP Cores User Guide

MICROCHIP H.264 4K I-Frame Encoder IP Cores

Introduction

H.264 is a popular video compression standard to compress a digital video. It is also known as MPEG-4 Part10 or Advanced Video Coding (MPEG-4 AVC). H.264 uses the block-wise approach for compressing a video where the block size is defined as 16 x 16 and such block is called a macro block. The compression standard supports various profiles that define the compression ratio and complexity of implementation. The video frames to be compressed are treated as I-Frame, P-Frame, and B-Frame. An I-Frame is an intra-coded frame where compression is done by using the information contained within the frame. No other frames are required to decode the I-Frame. A P-Frame is compressed by using the changes with respect to an earlier frame that can be an I-Frame or a P-Frame. The compression of B-Frame is done by using the motion changes with respect to both an earlier frame and an upcoming frame. The I-Frame compression process has four stages—Intra prediction, Integer transformation, Quantization, and Entropy encoding. H.264 supports two types of encoding—Context Adaptive Variable Length Coding (CAVLC) and Context Adaptive Binary Arithmetic Coding (CABAC). The current version of the IP implements Baseline profile and uses CAVLC for entropy encoding. Also, the IP supports encoding of only I-Frames upto 4K resolution.

Features

H.264 I-Frame Encoder supports the following key feature:

• Implements Compression on YCbCr 420 Video Format
• Expects the Input in YCbCr 422 Video Format
• Supports 8 bits for Each Component (Y, Cb, and Cr)
• Supports ITU-T H.264 Annex B Compliant NAL byte Stream Output
• Standalone Operation, CPU, or Processor Assistance Not Required
• User Configurable Quality Factor QP During Run Time
• Computation at the Rate of 1 pixel Per Clock
• Supports Compression up to Resolution of 4K (3840 × 2160) 60 fps
• Minimal Latency (252 μs for full HD or 17 horizontal lines)
• Supports 2 and 4 slices

Supported Families
The H.264 4K I-Frame Encoder supports the following families:

• PolarFire® SoC FPGA
• PolarFire FPGA

Hardware Implementation

The following figure shows the H.264 4K I-Frame Encoder IP block diagram.
Figure 1-1. H.264 4K I-Frame Encoder IP Block Diagram

Inputs and Outputs
The following table lists the input and output ports of H.264 4K I-Frame Encoder IP.
Table 1-1. Input and Output Ports of H.264 4K I-Frame Encoder IP

of 16.
VRES_I| Input| 16| Vertical resolution of input image. It must be multiple of 16.
QP_I| Input| 6| Quality factor for H.264 quantization. The value ranges from 0 to 51 where 0 represents the highest quality and the lowest compression and 51 represents the highest compression.
DATA0_O| Output| 16| H.264 Slice0 encoded data output that contains NAL unit, Slice header, SPS, PPS, and the encoded data of macro blocks.
DATA_VALID0_O| Output| 1| Signal denoting Slice0 encoded data is valid.
DATA1_O| Output| 16| H.264 Slice1 encoded data output that contains Slice header, and the encoded data of macro blocks.
DATA_VALID1_O| Output| 1| Signal denoting Slice1 encoded data is valid.
DATA2_O| Output| 16| H.264 Slice2 encoded data output that contains Slice header, and the encoded data of macro blocks.
DATA_VALID2_O| Output| 1| Signal denoting Slice2 encoded data is valid.
………..continued

Signal Name| Direction| Width| Description
DATA3_O| Output| 16| H.264 Slice3 encoded data output that contains Slice header, and the encoded data of macro blocks.
DATA_VALID3_O| Output| 1| Signal denoting Slice3 encoded data is valid.
DDR_LINE_GAP_I| Input| 16| Line gap between input image horizontal lines in the DDR memory.
FRAME_START_ADDR_I| Input| 7/8| DDR frame buffer address. 7 bits when the frame gap is configured for 32 MB. 8 bits when the frame gap is configured for 16 MB.
FRAME_END_O| Output| 1| End of H.264 bit stream for a frame.
Read Channel 0 Arbiter Interface Ports
RDATA0_I| Input| Input data width| Read data from arbiter
RVALID0_I| Input| 1| Read data valid from arbiter
ARREADY0_I| Input| 1| Arbiter acknowledgment
BUSER0_I| Input| 1| Read completion
ARADDR0_O| Output| 32| DDR address from where read must be started
ARVALID0_O| Output| 1| Read request to arbiter
ARSIZE0_O| Output| 8| Read burst size
Read Channel 1 Arbiter Interface Ports
RDATA1_I| Input| Input data width| Read data from arbiter
RVALID1_I| Input| 1| Read data valid from arbiter
ARREADY1_I| Input| 1| Arbiter acknowledgment
BUSER1_I| Input| 1| Read completion
ARADDR1_O| Output| 32| DDR address from where read must be started
ARVALID1_O| Output| 1| Read request to arbiter
ARSIZE1_O| Output| 8| Read burst size
Read Channel 2 Arbiter Interface Ports
RDATA2_I| Input| Input data width| Read data from arbiter
RVALID2_I| Input| 1| Read data valid from arbiter
ARREADY2_I| Input| 1| Arbiter acknowledgment
BUSER2_I| Input| 1| Read completion
ARADDR2_O| Output| 32| DDR address from where read must be started
ARVALID2_O| Output| 1| Read request to arbiter
ARSIZE2_O| Output| 8| Read burst size
Read Channel 3 Arbiter Interface Ports
RDATA3_I| Input| Input data width| Read data from arbiter
RVALID3_I| Input| 1| Read data valid from arbiter
………..continued

Signal Name| Direction| Width| Description
ARREADY3_I| Input| 1| Arbiter acknowledgment
BUSER3_I| Input| 1| Read completion
ARADDR3_O| Output| 32| DDR address from where read must be started
ARVALID3_O| Output| 1| Read request to arbiter
ARSIZE3_O| Output| 8| Read burst size

Configuration Parameters
The following table lists the description of the generic configuration parameters used in the hardware implementation of the H.264 4K I-Frame Encoder, which can vary based on the application requirements.
Table 1-2. H.264 4K I-Frame Encoder Configuration Parameters

along with 4 x 4 intra dc prediction.
NUM_SLICES| Select 2 slices to support 4K at 30 fps. Select 4 slices to support 4K at 60 fps.
DDR_AXI_DATA_WIDTH| Select the DATA width of read channel, which must be connected to video arbiter IP.
FRAME_GAP| Select the frame buffer size. For 4K select 32 MB.

IP Configurator
The following figure shows the H.264 4K I-Frame Encoder IP configurator.

Figure 1-2. IP Configuration

Hardware Implementation of H.264 4K I-Frame Encoder IP
The H.264 4K I-Frame Encoder IP divides each frame into 2/4 slices and encodes using the slice encoder. The DDR read logic expects the frame data in DDR memory as YCbCr 422 format. The line gap between every horizontal line of frame in DDR memory must be specified through DDR_LINE_GAP_I input. The IP uses 422 formats as input and implements compression in 420 formats. The Slice0 output also contains the SPS and PPS header. All slices bit stream is provided seperately. All slices bit stream combine together becomes the final H.264 bit stream. The following figure shows the H.264 4K I-Frame encoder IP block diagram.
Figure 1-3. H.264 4K I-Frame Encoder IP Block Diagram

The following figure shows the slice encoder block diagram.

Figure 1-4. Slice Encoder Block Diagram

Design Description Slice Encoder
This section describes the different internal modules of the slice encoder.
16 x 16 Matrix Framer
This module frames the 16 x 16 macro blocks for Y component as per H.264 specification. Line buffers are used to store 16 horizontal lines of input image, and a 16 x 16 matrix is framed using shift registers.
8 x 8 Matrix Framer
This module frames the 8 x 8 macro blocks for the C component as per H.264 specification for 420 formats. Line buffers are used to store 8 horizontal lines of input image, and an 8 x 16 matrix is framed using shift registers. From the 8 x 16 matrix, the Cb and Cr components are separated to frame each 8 x 8 matrix.
4 x 4 Matrix Framer
The integer transform, quantization, and CAVLC encoding operate on a 4 x 4 sub-block within a macroblock. The 4 x 4 matrix framer generates a 4 x 4 sub- block from a 16 x 16 or 8 x 8 macroblock. This matrix generator spans through all the sub-blocks of a macroblock before going to the next macroblock.
Intra Prediction
H.264 uses various intra-prediction modes to reduce the information in a 4 x 4 block. The intra-prediction block in the IP uses only 4 x 4 or 16 x 16 DC prediction. 16 x 16 is used for QP values more than 35 if 16 x 16 intra-DC prediction is enabled in the IP configurator. The DC component is computed from the adjacent top and left 4 x 4 or 16 x 16 blocks.
Integer Transform
H.264 uses integer discrete cosine transform where the coefficients are distributed across the integer transform matrix and the quantization matrix such that there are no multiplications or divisions in the integer transform. The integer transform stage implements the transformation using shift and add operations.
Quantization
The quantization multiplies each output of the integer transform with a predetermined quantization value defined by the QP user input value. The range of QP value is from 0 to 51. Any value more than 51 is clamped to 51. A lower QP value denotes lower compression and higher quality and vice versa.
CAVLC
H.264 uses two types of entropy encoding—Context Adaptive Variable Length Coding (CAVLC) and Context Adaptive Binary Arithmetic Coding (CABAC). The IP uses CAVLC for encoding the quantized output.
Header Generator
The header generator block generates the block headers, slice headers, Sequence Parameter Set (SPS), Picture Parameter Set (PPS), and Network Abstraction Layer (NAL) unit depending on the instance of the video frame.
H.264 Stream Generator
The H.264 stream generator block combines the CAVLC output along with the headers to create the encoded output as per the H.264 standard format.

Testbench

Testbench is provided to check the functionality of H.264 4K I-Frame Encoder IP.
Simulation
The simulation uses a 432 x 240 image in YCbCr422 format represented by two files, each for Y and C as input and generates a H.264 with 4 slices file format that contains two frames.
The following steps describe how to simulate the core using the testbench:

1. Go to Libero® SoC Catalog > View > Windows > Catalog, and then expand Solutions-Video. Double click H264_4K_Iframe_Encoder, and then click OK. H264_4K_Iframe-Encoder IP appears on the SmartDesign canvas.
   Figure 2-1. H.264 4K I-Frame Encoder IP Core in Libero® SoC Catalog

2. Go to the Files tab and select simulation > Import Files.
   Figure 2-2. Import Files

3. Import the H264_sim_data_in_y.txt, H264_sim_data_in_c.txt, and H264_refOut.txt files from the following path: ..\\component\Microsemi\SolutionCore\ H264_4K_Iframe_Encoder\ \Stimulus.

4. To import a different file, browse the folder that contains the required file, and click Open. The imported file is listed under simulation, see the following figure.
   Figure 2-3. Imported Files

5. Go to the Design Hierarchy tab and right click on H264_4K_Iframe_Enc_C0 and select Set As Root. Figure 2-4. Set As Root

6. Go to the Stimulus Hierarchy tab and select H264_4K_Iframe_Encoder_tb (H264_4K_Iframe_Encoder_tb. v) > Simulate Pre-Synth Design > Open Interactively. The IP is simulated for two frames. Figure 2-5. Simulating Pre-Synthesis Design

7. ModelSim opens with the testbench file as shown in the following figure.

Figure 2-6. ModelSim Simulation Window

Important: If the simulation is interrupted due to the runtime limit specified in the .do file, use the run -all command to complete the simulation.

License

• H.264 4K I-Frame Encoder IP is provided only in encrypted form under license.
• Encrypted RTL source code is license locked, must be purchased separately. You can perform simulation, synthesis, layout, and program the Field Programmable Gate Array (FPGA) silicon using the Libero design suite.
• Evaluation license is provided for free to check the H.264 Encoder features. The evaluation license expires after an hour’s use on the hardware.

Installation Instructions

• The core must be installed into Libero SoC software. It is done automatically through the Catalog update function in
• Libero SoC software, or the CPZ file can be manually added using the Add Core catalog feature. When the CPZ file is installed in Libero, the core can be configured, generated, and instantiated within SmartDesign for inclusion in the Libero project.
• For more instructions on core installation, licensing, and general use, see Libero SoC Online Help.

The following table lists the resource utilization of a sample H.264 4K I-Frame Encoder IP design made for PolarFire FPGA (MPF300TS-1FCG1152I package) and generates compressed data by using 4:2:2 sampling of input data.
Table 5-1. Resource Utilization of the H.264 4K I-Frame Encoder IP

Revision History

The revision history table describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.
Table 6-1. Revision History

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References

• Empowering Innovation | Microchip Technology
• Empowering Innovation | Microchip Technology
• Microchip Lightning Support
• Empowering Innovation | Microchip Technology
• IP Core Tools | Microchip Technology
• Client Support Services | Microchip Technology
• Microchip Lightning Support

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