ALINX AX7203 FPGA Development Board User Manual
- June 13, 2024
- ALINX
Table of Contents
AX7203 FPGA Development Board
Product Information
ARTIX-7 FPGA Development Board AX7203 User Manual
| Version | Rev 1.2 |
|---|---|
| Date | 2023-02-23 |
| Release By | Rachel Zhou |
| Description | First Release |
Part 1: FPGA Development Board Introduction
The AX7203 FPGA development board is a core board + carrier
board platform that allows for convenient secondary development
using the core board. It utilizes a high-speed inter-board
connector between the core board and the carrier board.
The AX7203 carrier board provides various peripheral interfaces,
including:
- 1 PCIex4 interface
- 2 Gigabit Ethernet interfaces
- 1 HDMI Output interface
- 1 HDMI Input interface
- 1 Uart Interface
- 1 SD card slot
- XADC connector interface (not installed by default)
- 2-way 40-pin expansion header
- Some keys
- LED
- EEPROM circuit
Part 2: AC7200 Core Board Introduction
The AC7200 core board is based on XILINX’s ARTIX-7 series 200T
AC7200-2FGG484I. It is a high-performance core board suitable for
high-speed data communication, video image processing, and
high-speed data acquisition.
Key features of the AC7200 core board include:
-
Two pieces of MICRON’s MT41J256M16HA-125 DDR3 chips with a
capacity of 4Gbit each, providing a 32-bit data bus width and up to
25Gb read/write data bandwidth between FPGA and DDR3. -
180 standard IO ports of 3.3V level
-
15 standard IO ports of 1.5V level
-
4 pairs of GTP high-speed RX/TX differential signals
-
Equal length and differential processing routing between the
FPGA chip and the interface -
Compact size of 45*55 (mm)
Product Usage Instructions
To use the ARTIX-7 FPGA Development Board AX7203, follow these
steps:
-
Connect the core board and carrier board using the high-speed
inter-board connector. -
If required, install the XADC interface using the provided
connector. -
Connect any desired peripherals to the available interfaces on
the carrier board, such as PCIex4 devices, Gigabit Ethernet
devices, HDMI devices, Uart devices, SD cards, or external
expansion headers. -
Power on the development board using the appropriate power
supply.
ARTIX-7 FPGA Development Board
AX7203
User Manual
ARTIX-7 FPGA Development Board AX7203 User Manual
Version Record
Version Rev 1.2
Date 2023-02-23
Release By Rachel Zhou
Description First Release
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ARTIX-7 FPGA Development Board AX7203 User Manual
Table of Contents
Version Record …………………………………………………………………………………2 Part 1: FPGA Development Board
Introduction …………………………………… 6 Part 2: AC7200 Core Board Introduction
……………………………………………..9
Part 2.1: FPGA Chip ………………………………………………………………… 10 Part 2.2: Active Differential
Crystal ……………………………………………..12 Part 2.3: 200Mhz Active Differential clock
……………………………………12 Part 2.4: 148.5Mhz Active Differential Crystal ……………………………..
13 Part 2.5: DDR3 DRAM ………………………………………………………………15 Part 2.6: QSPI Flash
…………………………………………………………………19 Part 2.7: LED Light on Core Board
……………………………………………. 21 Part 2.8: Reset Button ……………………………………………………………… 22 Part
2.9: JTAG Interface …………………………………………………………… 23 Part 2.10: Power Interface on
the Core Board ……………………………. 24 Part 2.11: Board to Board Connectors
……………………………………….. 25 Part 2.12: Power Supply ……………………………………………………………32 Part
2.13: Structure Diagram ……………………………………………………..33 Part 3: Carrier board
………………………………………………………………………. 34 Part 3.1: Carrier board Introduction
…………………………………………… 34 Part 3.2: Gigabit Ethernet Interface …………………………………………… 35
Part 3.3: PCIe x4 Interface ……………………………………………………….. 38 Part 3.4: HDMI output
interface ………………………………………………….40 Part 3.5: HDMI Input interface
……………………………………………………42 Part 3.6: SD Card Slot ……………………………………………………………… 44 Part
3.7: USB to Serial Port ……………………………………………………….45 Part 3.8: EEPROM 24LC04
……………………………………………………….47 Part 3.9: Expansion Header ……………………………………………………… 48
Part 3.10: JTAG Interface …………………………………………………………. 51
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.11: XADC interface (not installed by default) …………………….. 52 Part 3.12:
keys …………………………………………………………………………53 Part 3.13: LED Light
………………………………………………………………… 54 Part 3.14: Power Supply ……………………………………………………………55
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ARTIX-7 FPGA Development Board AX7203 User Manual
This ARTIX-7 FPGA development platform (Module: AX7203) adopts the core board
- carrier board mode, which is convenient for users to use the core board for
secondary development.
In the design of carrier board, we have extended a wealth of interfaces for users, such as 1 PCIex4 interface, 2 Gigabit Ethernet interfaces, 1 HDMI Output interface, 1 HDMI Input interface, Uart Interface, SD card slot etc. It meets user’s requirements for PCIe high-speed data exchange, video transmission processing and industrial control. It is a “Versatile” ARTIX-7 FPGA development platform. It provides the possibility for high-speed video transmission, pre-validation and post-application of network and fiber communication and data processing. This product is very suitable for students, engineers and other groups engaged in ARTIX-7FPGA development.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 1: FPGA Development Board Introduction
The entire structure of the AX7203 FPGA development board is inherited from
our consistent core board + carrier board model. A high-speed inter-board
connector is used between the core board and the carrier board.
The core board is mainly composed of FPGA + 2 DDR3 + QSPI FLASH, which
undertakes the functions of high-speed data processing and storage of FPGA,
high-speed data reading and writing between FPGA and two DDR3s, data bit width
is 32 bits, and the bandwidth of the whole system is up to 25Gb.
/s(800M*32bit); The two DDR3 capacities are up to 8Gbit, which meets the need
for high buffers during data processing. The selected FPGA is the XC7A200T
chip of XILINX’s ARTIX-7 series, in BGA 484 package. The communication
frequency between the XC7A200T and DDR3 reaches 400Mhz and the data rate is
800Mhz, which fully meets the needs of high-speed multi-channel data
processing. In addition, the XC7A200T FPGA features four GTP high-speed
transceivers with speeds up to 6.6Gb/s per channel, making it ideal for fiber-
optic communications and PCIe data communications.
The AX7203 carrier board expands its rich peripheral interface, including 1
PCIex4 interface, 2 Gigabit Ethernet interfaces, 1 HDMI Output interface, 1
HDMI Input interface, 1 Uart Interface, 1 SD card slot, XADC connector
interface, 2-way 40-pin expansion header, some keys, LED and EEPROM circuit.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 1-1-1: The Schematic Diagram of the AX7203 Through this diagram, you
can see the interfaces and functions that the AX7203 FPGA Development Board
contains: Artix-7 FPGA core board
The core board consists of XC7A200T + 8Gb DDR3 + 128Mb QSPI FLASH. There are
two high-precision Sitime LVDS differential crystals, one at 200MHz and the
other at 125MHz, providing stable clock input for FPGA systems and GTP
modules. 1-channel PCIe x4 interface Supports PCI Express 2.0 standard,
provides PCIe x4 high-speed data transmission interface, single channel
communication rate up to 5GBaud 2-channel Gigabit Ethernet Interface RJ-45
interface The Gigabit Ethernet interface chip uses Micrel’s KSZ9031RNX
Ethernet PHY chip to provide network communication services to users.
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ARTIX-7 FPGA Development Board AX7203 User Manual
The KSZ9031RNX chip supports 10/100/1000 Mbps network transmission rates; full
duplex and adaptive. 1-channel HDMI Output interface Silion Image’s SIL9134
HDMI encoding chip is selected to support up to 1080P@60Hz output and support
3D output. 1-channel HDMI Input interface Silion Image’s SIL9013 HDMI decoder
chip is selected, which supports up to 1080P@60Hz input and supports data
output in different formats. 1-channel Uart to USB interface 1 Uart to USB
interface for communication with the computer for user debugging. The serial
port chip is the USB-UAR chip of Silicon Labs CP2102GM, and the USB interface
is the MINI USB interface. Micro SD card holder 1-port Micro SD card holder,
support SD mode and SPI mode EEPROM Onboard an IIC interface EEPROM 24LC04
2-way 40-pin expansion port 2-way 40-pin 2.54mm pitch expansion port can be
connected to various ALINX modules (binocular camera, TFT LCD screen, high-
speed AD module, etc.). The expansion port contains 1 channel 5V power supply,
2 channel 3.3V power supply, 3 way ground, 34 IOs port. JTAG Interface A
10-pin 0.1inch spacing standard JTAG ports for FPGA program download and
debugging. keys 2 keys; 1 reset key (on the core board) LED Light 5 user LEDs
(1 on the core board and 4 on the carrier board)
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2: AC7200 Core Board Introduction
AC7200 (core board model, the same below) FPGA core board, it is based on
XILINX’s ARTIX-7 series 200T AC7200-2FGG484I. It is a high-performance core
board with high speed, high bandwidth and high capacity. It is suitable for
high-speed data communication, video image processing, high-speed data
acquisition, etc.
This AC7200 core board uses two pieces of MICRON’s MT41J256M16HA-125 DDR3
chip, each DDR has a capacity of 4Gbit; two DDR chips are combined into a
32-bit data bus width, and the read/write data bandwidth between FPGA and DDR3
is up to 25Gb; such a configuration can meet the needs of high bandwidth data
processing.
The AC7200 core board expands 180 standard IO ports of 3.3V level, 15 standard
IO ports of 1.5V level, and 4 pairs of GTP high speed RX/TX differential
signals. For users who need a lot of IO, this core board will be a good
choice. Moreover, the routing between the FPGA chip and the interface is equal
length and differential processing, and the core board size is only 45*55
(mm), which is very suitable for secondary development.
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ARTIX-7 FPGA Development Board AX7203 User Manual AC7200 Core Board (Front View)
AC7200 Core Board (Rear View)
Part 2.1: FPGA Chip
As mentioned above, the FPGA model we use is AC7200-2FGG484I, which belongs to
Xilinx’s Artix-7 series. The speed grade is 2, and the temperature grade is
industry grade. This model is a FGG484 package with 484 pins. Xilinx ARTIX-7
FPGA chip naming rules as below
The Specific Chip Model Definition of ARTIX-7 Series
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ARTIX-7 FPGA Development Board AX7203 User Manual
FPGA chip on board The main parameters of the FPGA chip AC7200 are as follows
Name Logic Cells
Slices CLB flip-flops Block RAMkb DSP Slices
PCIe Gen2 XADC
GTP Transceiver Speed Grade
Temperature Grade
Specific parameters 215360 33650 269200 13140 740 1
1 XADC,12bit, 1Mbps AD 4 GTP6.6Gb/s max -2 Industrial
FPGA power supply system Artix-7 FPGA power supplies are V , CCINT V , CCBRAM V , CCAUX VCCO, VMGTAVCC and V . MGTAVTT VCCINT is the FPGA core power supply pin, which needs to be connected to 1.0V; VCCBRAM is the power supply pin of FPGA block RAM, connect to 1.0V; VCCAUX is FPGA auxiliary power supply pin, connect 1.8V; VCCO is the voltage of
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ARTIX-7 FPGA Development Board AX7203 User Manual
each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On AC7200 FPGA core
board, BANK34 and BANK35 need to be connected to DDR3, the voltage connection
of BANK is 1.5V, and the voltage of other BANK is 3.3V. The VCCO of BANK15 and
BANK16 is powered by the LDO, and can be changed by replacing the LDO chip.
VMGTAVCC is the supply voltage of the FPGA internal GTP transceiver, connected
to 1.0V; VMGTAVTT is the termination voltage of the GTP transceiver, connected
to 1.2V.
The Artix-7 FPGA system requires that the power-up sequence be powered by
VCCINT, then VCCBRAM, then VCCAUX, and finally VCCO. If VCCINT and VCCBRAM
have the same voltage, they can be powered up at the same time. The order of
power outages is reversed. The power-up sequence of the GTP transceiver is
VCCINT, then VMGTAVCC, then VMGTAVTT. If VCCINT and VMGTAVCC have the same
voltage, they can be powered up at the same time. The power-off sequence is
just the opposite of the power-on sequence.
Part 2.2: Active Differential Crystal
The AC7200 core board is equipped with two Sitime active differential
crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main clock
for FPGA and used to generate DDR3 control clock; the other is 125MHz, model
is SiT9102 -125MHz, reference clock input for GTP transceivers.
Part 2.3: 200Mhz Active Differential clock
G1 in Figure 3-1 is the 200M active differential crystal that provides the
development board system clock source. The crystal output is connected to the
BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz differential
clock can be used to drive the user logic in the FPGA. Users can configure the
PLLs and DCMs inside the FPGA to generate clocks of different frequencies.
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ARTIX-7 FPGA Development Board AX7203 User Manual
200Mhz Active Differential Crystal Schematic
200Mhz Active Differential Crystal on the Core Board
200Mhz Differential Clock Pin Assignment
Signal Name SYS_CLK_P SYS_CLK_N
FPGA PIN R4 T4
Part 2.4: 148.5Mhz Active Differential Crystal
G2 is the 148.5Mhz active differential crystal, which is the reference input
clock provided to the GTP module inside the FPGA. The crystal output is
connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and MGTREFCLK0N (E6)
of the FPGA.
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ARTIX-7 FPGA Development Board AX7203 User Manual
148.5Mhz Active Differential Crystal Schematic
1148.5Mhz Active Differential Crystal on the Core Board
125Mhz Differential Clock Pin Assignment
Net Name
FPGA PIN
MGT_CLK0_P
F6
MGT_CLK0_N
E6
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.5: DDR3 DRAM
The FPGA core board AC7200 is equipped with two Micron 4Gbit (512MB) DDR3 chips, model MT41J256M16HA-125 (compatible with MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed of 800MHz (data rate 1600Mbps). The DDR3 memory system is directly connected to the memory interface of the BANK 34 and BANK35 of the FPGA. The specific configuration of DDR3 SDRAM is shown in Table 4-1.
Bit Number U5,U6
Chip Model MT41J256M16HA-125
Capacity 256M x 16bit
Factory Micron
DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal integrity. We have fully considered the matching resistor/terminal resistance, trace impedance control, and trace length control in circuit design and PCB design to ensure high-speed and stable operation of DDR3.
The DDR3 DRAM Schematic
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ARTIX-7 FPGA Development Board AX7203 User Manual
The DDR3 on the Core Board
DDR3 DRAM pin assignment:
Net Name
FPGA PIN Name
DDR3_DQS0_P
IO_L3P_T0_DQS_AD5P_35
DDR3_DQS0_N DDR3_DQS1_P DDR3_DQS1_N DDR3_DQS2_P DDR3_DQS2_N DDR3_DQS3_P
DDR3_DQS3_N
DDR3_DQ[0] DDR3_DQ [1] DDR3_DQ [2] DDR3_DQ [3] DDR3_DQ [4] DDR3_DQ [5]
IO_L3N_T0_DQS_AD5N_35 IO_L9P_T1_DQS_AD7P_35 IO_L9N_T1_DQS_AD7N_35
IO_L15P_T2_DQS_35 IO_L15N_T2_DQS_35 IO_L21P_T3_DQS_35 IO_L21N_T3_DQS_35
IO_L2P_T0_AD12P_35 IO_L5P_T0_AD13P_35 IO_L1N_T0_AD4N_35
IO_L6P_T0_35 IO_L2N_T0_AD12N_35 IO_L5N_T0_AD13N_35
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FPGA P/N E1 D1 K2 J2 M1 L1 P5 P4 C2 G1 A1 F3 B2 F1
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ARTIX-7 FPGA Development Board AX7203 User Manual
DDR3_DQ [6]
IO_L1P_T0_AD4P_35
B1
DDR3_DQ [7]
IO_L4P_T0_35
E2
DDR3_DQ [8]
IO_L11P_T1_SRCC_35
H3
DDR3_DQ [9]
IO_L11N_T1_SRCC_35
G3
DDR3_DQ [10]
IO_L8P_T1_AD14P_35
H2
DDR3_DQ [11]
IO_L10N_T1_AD15N_35
H5
DDR3_DQ [12]
IO_L7N_T1_AD6N_35
J1
DDR3_DQ [13]
IO_L10P_T1_AD15P_35
J5
DDR3_DQ [14]
IO_L7P_T1_AD6P_35
K1
DDR3_DQ [15]
IO_L12P_T1_MRCC_35
H4
DDR3_DQ [16]
IO_L18N_T2_35
L4
DDR3_DQ [17]
IO_L16P_T2_35
M3
DDR3_DQ [18]
IO_L14P_T2_SRCC_35
L3
DDR3_DQ [19]
IO_L17N_T2_35
J6
DDR3_DQ [20]
IO_L14N_T2_SRCC_35
K3
DDR3_DQ [21]
IO_L17P_T2_35
K6
DDR3_DQ [22]
IO_L13N_T2_MRCC_35
J4
DDR3_DQ [23]
IO_L18P_T2_35
L5
DDR3_DQ [24]
IO_L20N_T3_35
P1
DDR3_DQ [25]
IO_L19P_T3_35
N4
DDR3_DQ [26]
IO_L20P_T3_35
R1
DDR3_DQ [27]
IO_L22N_T3_35
N2
DDR3_DQ [28]
IO_L23P_T3_35
M6
DDR3_DQ [29]
IO_L24N_T3_35
N5
DDR3_DQ [30]
IO_L24P_T3_35
P6
DDR3_DQ [31]
IO_L22P_T3_35
P2
DDR3_DM0
IO_L4N_T0_35
D2
DDR3_DM1
IO_L8N_T1_AD14N_35
G2
DDR3_DM2
IO_L16N_T2_35
M2
DDR3_DM3
IO_L23N_T3_35
M5
DDR3_A[0]
IO_L11N_T1_SRCC_34
AA4
DDR3_A[1]
IO_L8N_T1_34
AB2
DDR3_A[2]
IO_L10P_T1_34
AA5
DDR3_A[3]
IO_L10N_T1_34
AB5
DDR3_A[4]
IO_L7N_T1_34
AB1
DDR3_A[5]
IO_L6P_T0_34
U3
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ARTIX-7 FPGA Development Board AX7203 User Manual
DDR3_A[6] DDR3_A[7] DDR3_A[8] DDR3_A[9] DDR3_A[10] DDR3_A[11] DDR3_A[12] DDR3_A[13] DDR3_A[14] DDR3_BA[0] DDR3_BA[1] DDR3_BA[2] DDR3_S0 DDR3_RAS DDR3_CAS DDR3_WE DDR3_ODT DDR3_RESET DDR3_CLK_P DDR3_CLK_N DDR3_CKE
IO_L5P_T0_34 IO_L1P_T0_34 IO_L2N_T0_34 IO_L2P_T0_34 IO_L5N_T0_34 IO_L4P_T0_34 IO_L4N_T0_34 IO_L1N_T0_34 IO_L6N_T0_VREF_34 IO_L9N_T1_DQS_34 IO_L9P_T1_DQS_34 IO_L11P_T1_SRCC_34 IO_L8P_T1_34 IO_L12P_T1_MRCC_34 IO_L12N_T1_MRCC_34 IO_L7P_T1_34 IO_L14N_T2_SRCC_34 IO_L15P_T2_DQS_34 IO_L3P_T0_DQS_34 IO_L3N_T0_DQS_34 IO_L14P_T2_SRCC_34
W1 T1 V2 U2 Y1 W2 Y2 U1 V3 AA3 Y3 Y4 AB3 V4 W4 AA1 U5 W6 R3 R2 T5
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.6: QSPI Flash
The FPGA core board AC7200 is equipped with one 128MBit QSPI FLASH, and the model is W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a boot device for the system to store the boot image of the system. These images mainly include FPGA bit files, ARM application code, core application code and other user data files. The specific models and related parameters of QSPI FLASH are shown .
Position U8
Model N25Q128
Capacity 128M Bit
Factory Numonyx
QSPI FLASH Specification
QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of the FPGA
chip. The clock pin is connected to CCLK0 of BANK0, and other data and chip
select signals are connected to D00~D03 and FCS pins of BANK14 respectively.
Shows the hardware connection of QSPI Flash.
QSPI Flash Schematic QSPI Flash pin assignments:
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ARTIX-7 FPGA Development Board AX7203 User Manual
Net Name QSPI_CLK QSPI_CS QSPI_DQ0 QSPI_DQ1 QSPI_DQ2 QSPI_DQ3
FPGA PIN Name CCLK_0
IO_L6P_T0_FCS_B_14 IO_L1P_T0_D00_MOSI_14 IO_L1N_T0_D01_DIN_14
IO_L2P_T0_D02_14 IO_L2N_T0_D03_14
FPGA P/N L12 T19 P22 R22 P21 R21
QSPI on the Core Board
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.7: LED Light on Core Board
There are 3 red LED lights on the AC7200 FPGA core board, one of which is the
power indicator light (PWR), one is the configuration LED light (DONE), and
one is the user LED light. When the core board is powered, the power indicator
will illuminate; when the FPGA is configured, the configuration LED will
illuminate. The user LED light is connected to the IO of the BANK34, the user
can control the light on and off by the program. When the IO voltage connected
to the user LED is high, the user LED is off. When the connection IO voltage
is low, the user LED will be lit. The schematic diagram of the LED light
hardware connection is shown:
LED lights on core board Schematic
LED lights on the Core Board User LEDs Pin Assignment
Signal Name LED1
FPGA Pin Name IO_L15N_T2_DQS_34
FPGA Pin Number W5
Description User LED
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.8: Reset Button
There is a reset button on the AC7200 FPGA core board. The reset button is
connected to the normal IO of the BANK34 of the FPGA chip. The user can use
this reset button to initialize the FPGA program. When the button is pressed
in the design, the signal voltage input to IO is low, and the reset signal is
valid; when the button is not pressed, the signal input to IO is high. The
schematic diagram of the reset button connection is shown:
Reset Button Schematic
Reset button on the Core Board Reset button pin assignment
Signal Name RESET_N
ZYNQ Pin Name IO_L17N_T2_34
ZYNQ Pin Number T6
Description FPGA system reset
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.9: JTAG Interface
The JTAG test socket J1 is reserved on the AC7200 core board for JTAG download
and debugging when the core board is used alone. Figure is the schematic part
of the JTAG port, which involves TMS, TDI, TDO, TCK. , GND, +3.3V these six
signals.
JTAG Interface Schematic The JTAG interface J1 on AC7200 FPGA core board uses
a 6-pin 2.54mm pitch single-row test hole. If you need to use the JTAG
connection to debug on the core board, you need to solder a 6-pin single-row
pin header. shows the JTAG interface J1 on the AC7200 FPGA core board.
JTAG Interface on Core Board
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.10: Power Interface on the Core Board
In order to make the AC7200 FPGA core board work alone, the core board is
reserved with the 2PIN power interface (J3). When the user supplies power to
the core board through 2PIN power interface (J3), it cannot be powered through
the carrier board. Otherwise, current conflict may occur.
Power Interface on the Core Board
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.11: Board to Board Connectors
The core board has a total of four high-speed board to board connectors. The
core board uses four 80-pin inter-board connectors to connect to the carrier
board. The IO port of the FPGA is connected to the four connectors by
differential routing. The pin spacing of the connectors is 0.5mm, insert to
the board to board connectors on the carrier board for high-speed data
communication.
The core board has a total of four high-speed board to board connectors. The
core board uses four 80-pin inter-board connectors to connect to the carrier
board. The IO port of the FPGA is connected to the four connectors by
differential routing. The pin spacing of the connectors is 0.5mm, insert to
the board to board connectors on the carrier board for high-speed data
communication.
Board to Board Connectors CON1 The 80-pin board to board connectors CON1,
which are used to connect
with the VCCIN power supply (+5V) and ground on the carrier board, extend the
normal IOs of the FPGA. It should be noted here that 15 pins of CON1 are
connected to the IO port of BANK34, because the BANK34 connection is connected
to DDR3. Therefore, the voltage standard of all IOs of this BANK34 is 1.5V.
Pin Assignment of Board to Board Connectors CON1
CON1 Pin PIN1 PIN3 PIN5 PIN7 PIN9
Signal Name
VCCIN VCCIN VCCIN VCCIN GND
FPGA Pin Voltage Level
–
+5V
–
+5V
–
+5V
–
+5V
–
Ground
CON1 Pin PIN2 PIN4 PIN6 PIN8 PIN10
Signal Name
VCCIN VCCIN VCCIN VCCIN
GND
FPGA Pin Voltage Level
–
+5V
–
+5V
–
+5V
–
+5V
–
Ground
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71
NC NC NC NC GND B13_L5_P B13_L5_N B13_L7_P B13_L7_P GND B13_L3_P B13_L3_N B34_L23_P B34_L23_N GND B34_L18_N B34_L18_P B34_L19_P B34_L19_N GND XADC_VN XADC_VP NC NC GND B16_L1_N B16_L1_P B16_L4_N B16_L4_P GND B16_L6_N
Y13 AA14 AB11 AB12 AA13 AB13 Y8 Y7 AA6 Y6 V7 W7 M9 L10 F14 F13 E14 E13 D15
Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 1.5V 1.5V Ground 1.5V 1.5V 1.5V 1.5V Ground ADC ADC Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V
PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72
NC NC B13_L4_P B13_L4_N GND B13_L1_P B13_L1_N B13_L2_P B13_L2_N GND B13_L6_P B13_L6_N B34_L20_P B34_L20_N GND B34_L21_N B34_L21_P B34_L22_P B34_L22_N GND NC B34_L25 B34_L24_P B34_L24_N GND NC NC NC NC GND NC
AA15 AB15 Y16 AA16 AB16 AB17 W14 Y14 AB7 AB6 V8 V9 AA8 AB8 –
3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 1.5V 1.5V Ground 1.5V 1.5V 1.5V 1.5V Ground
U7
1.5V
W9
1.5V
Y9
1.5V
–
Ground
–
–
–
–
–
–
–
–
–
Ground
–
–
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ARTIX-7 FPGA Development Board AX7203 User Manual
Board to Board Connectors CON2 The 80-pin female connection header CON2 is
used to extend the normal
IO of the BANK13 and BANK14 of the FPGA. The voltage standards of both BANKs
are 3.3V. Pin Assignment of Board to Board Connectors CON2
CON1 Pin
Signal Name
PIN1 B13_L16_P
PIN3 B13_L16_N
PIN5 B13_L15_P
PIN7 B13_L15_N
PIN9
GND
PIN11 B13_L13_P
PIN13 B13_L13_N
PIN15 B13_L12_P
PIN17 B13_L12_N
PIN19
GND
PIN21 B13_L11_P
PIN23 B13_L11_N
PIN25 B13_L10_P
PIN27 B13_L10_N
PIN29
GND
PIN31 B13_L9_N
PIN33 B13_L9_P
PIN35 B13_L8_N
PIN37 B13_L8_P
PIN39
GND
PIN41 B14_L11_N
PIN43 B14_L11_P
PIN45 B14_L14_N
PIN47 B14_L14_P
FPGA Pin W15 W16 T14 T15 V13 V14 W11 W12 Y11 Y12 V10 W10 AA11 AA10 AB10 AA9 V20 U20 V19 V18
Voltage Level 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V
CON1 Pin PIN2 PIN4 PIN6 PIN8 PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48
Signal Name
B14_L16_P B14_L16_N B13_L14_P B13_L14_N
GND B14_L10_P B14_L10_N B14_L8_N B14_L8_P
GND B14_L15_N B14_L15_P B14_L17_P B14_L17_N
GND B14_L6_N B13_IO0 B14_L7_N B14_L7_P
GND B14_L4_P B14_L4_N B14_L9_P B14_L9_N
FPGA Pin Voltage
Level
V17
3.3V
W17
3.3V
U15
3.3V
V15
3.3V
–
Ground
AB21
3.3V
AB22
3.3V
AA21
3.3V
AA20
3.3V
–
Ground
AB20
3.3V
AA19
3.3V
AA18
3.3V
AB18
3.3V
–
Ground
T20
3.3V
Y17
3.3V
W22
3.3V
W21
3.3V
–
Ground
T21
3.3V
U21
3.3V
Y21
3.3V
Y22
3.3V
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79
GND B14_L5_N B14_L5_P B14_L18_N B14_L18_P
GND B13_L17_P B13_L17_N B14_L21_N B14_L21_P
GND B14_L22_P B14_L22_N B14_L24_N B14_L24_P
B14_IO0
R19 P19 U18 U17
T16 U16 P17 N17
P15 R16 R17 P16 P20
Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V 3.3V
PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72 PIN74 PIN76 PIN78 PIN80
GND B14_L12_N B14_L12_P B14_L13_N B14_L13_P
GND B14_L3_N B14_L3_P B14_L20_N B14_L20_P
GND B14_L19_N B14_L19_P B14_L23_P B14_L23_N B14_IO25
W20 W19 Y19 Y18
V22 U22 T18 R18
R14 P14 N13 N14 N15
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V 3.3V
Board to Board Connectors CON3 The 80-pin connector CON3 is used to extend the
normal IO of the
BANK15 and BANK16 of the FPGA. In addition, four JTAG signals are also
connected to the carrier board via the CON3 connector. The voltage standards
of BANK15 and BANK16 can be adjusted by an LDO chip. The default installed LDO
is 3.3V. If you want to output other standard levels, you can replace it with
a suitable LDO. Pin Assignment of Board to Board Connectors CON3
CON1 Pin PIN1 PIN3 PIN5 PIN7
Signal Name
B15_IO0 B16_IO0 B15_L4_P B15_L4_N
FPGA Pin J16 F15 G17 G18
Voltage Level
CON1 Pin
3.3V PIN2
3.3V PIN4
3.3V PIN6
3.3V
PIN8
Signal Name
B15_IO25 B16_IO25 B16_L21_N B16_L21_P
FPGA Pin Voltage Level
M17
3.3V
F21
3.3V
A21
3.3V
B21
3.3V
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71
GND B15_L2_P B15_L2_N B15_L12_P B15_L12_N
GND B15_L11_P B15_L11_N B15_L1_N B15_L1_P
GND B15_L5_P B15_L5_N B15_L3_N B15_L3_P
GND B15_L19_P B15_L19_N B15_L20_P B15_L20_N
GND B15_L14_P B15_L14_N B15_L21_P B15_L21_N
GND B15_L23_P B15_L23_N B15_L22_P B15_L22_N
GND B15_L24_P
G15 G16 J19 H19
J20 J21 G13 H13
J15 H15 H14 J14
K13 K14 M13 L13
L19 L20 K17 J17 L16 K16 L14 L15 M15
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V
PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72
GND B16_L23_P B16_L23_N B16_L22_P B16_L22_N
GND B16_L24_P B16_L24_N B15_L8_N B15_L8_P
GND B15_L7_N B15_L7_P B15_L9_P B15_L9_N
GND B15_L15_N B15_L15_P B15_L6_N B15_L6_P
GND B15_L13_N B15_L13_P B15_L10_P B15_L10_N
GND B15_L18_P B15_L18_N B15_L17_N B15_L17_P
GND B15_L16_P
E21 D21 E22 D22
G21 G22 G20 H20
H22 J22 K21 K22
M22 N22 H18 H17
K19 K18 M21 L21
N20 M20 N19 N18
M18
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN73 B15_L24_N
M16
3.3V
PIN74 B15_L16_N
L18
3.3V
PIN75
NC
–
PIN76
NC
–
PIN77 FPGA_TCK
V12
3.3V
PIN78
FPGA_TDI
R13
3.3V
PIN79 FPGA_TDO
U13
3.3V
PIN80 FPGA_TMS
T13
3.3V
Board to Board Connectors CON4 The 80-Pin connector CON4 is used to extend the
normal IO and GTP
high-speed data and clock signals of the FPGA BANK16. The voltage standard of
the IO port of BANK16 can be adjusted by an LDO chip. The default installed
LDO is 3.3V. If the user wants to output other standard levels, it can be
replaced by a suitable LDO. The high-speed data and clock signals of the GTP
are strictly differential routed on the core board. The data lines are equal
in length and kept at a certain interval to prevent signal interference. Pin
Assignment of Board to Board Connectors CON4
CON1 Pin PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29
Signal Name
NC NC
FPGA Pin Voltage Level –
–
CON1 Pin NC NC
NC
–
NC
NC
–
NC
GND NC
–
Ground PIN10
–
PIN12
NC
–
PIN14
GND
–
Ground PIN16
MGT_TX3_P
D7 Differential PIN18
MGT_TX3_N
C7 Differential PIN20
GND
–
Ground PIN22
MGT_RX3_P D9 Differential PIN24
MGT_RX3_N
C9 Differential PIN26
GND
– Ground
PIN28
MGT_TX1_P
D5 Differential PIN30
Signal Name FPGA Pin Voltage
Level
–
NC
–
NC
–
NC
–
NC
GND
–
Ground
MGT_TX2_P
B6 Differential
MGT_TX2_N
A6 Differential
GND
–
Ground
MGT_RX2_P
B10 Differential
MGT_RX2_N
A10 Differential
GND
–
Ground
MGT_TX0_P
B4 Differential
MGT_TX0_N
A4 Differential
GND
–
Ground
MGT_RX0_P
B8 Differential
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79
MGT_TX1_N GND
MGT_RX1_P MGT_RX1_N
GND B16_L5_P B16_L5_N B16_L7_P B16_L7_N
GND B16_L9_P B16_L9_N B16_L11_P B16_L11_N
GND B16_L13_P B16_L13_N B16_L15_P B16_L15_N
GND B16_L17_P B16_L17_N B16_L19_P B16_L19_N
NC
C5 D11 C11 E16 D16 B15 B16 A15 A16 B17 B18 C18 C19 F18 E18 A18 A19 D20 C20 –
Differential Ground
Differential Differential
Ground 3.3V 3.3V 3.3V 3.3V
Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V
3.3V
PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72 PIN74 PIN76 PIN78 PIN80
MGT_RX0_N GND
MGT_CLK1_P MGT_CLK1_N
GND B16_L2_P B16_L2_N B16_L3_P B16_L3_N
GND B16_L10_P B16_L10_N B16_L12_P B16_L12_N
GND B16_L14_P B16_L14_N B16_L16_P B16_L16_N
GND B16_L18_P B16_L18_N B16_L20_P B16_L20_N
NC
A8 Differential
–
Ground
F10 Differential
E10 Differential
–
Ground
F16
3.3V
E17
3.3V
C14
3.3V
C15
3.3V
–
Ground
A13
3.3V
A14
3.3V
D17
3.3V
C17
3.3V
–
Ground
E19
3.3V
D19
3.3V
B20
3.3V
A20
3.3V
–
Ground
F19
3.3V
F20
3.3V
C22
3.3V
B22
3.3V
–
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.12: Power Supply
The AC7200 FPGA core board is powered by DC5V via carrier board, and it is
powered by the J3 interface when it is used alone. Please be careful not to
supply power by the J3 interface and the carrier board at the same time to
avoid damage. The power supply design diagram on the board is shown in.
Power Supply on core board schematic
The development board is powered by +5V and converted to +3.3V, +1.5V, +1.8V, +1.0V four-way power supply through four DC/DC power supply chip TLV62130RGT. The output current can be up to 3A per channel. VCCIO is generated by one LDOSPX3819M5-3-3. VCCIO mainly supplies power to BANK15 and BANK16 of FPGA. Users can change the IO of BANK15,16 to different voltage standards by replacing their LDO chip. 1.5V Generates the VTT and VREF voltages required by DDR3 via TI’s TPS51200. The 1.8V power supply MGTAVTT MGTAVCC for the GTP transceiver is generated by TI’s TPS74801 chip. The functions of each power distribution are shown in the following table:
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ARTIX-7 FPGA Development Board AX7203 User Manual
Power Supply +1.0V +1.8V +3.3V +1.5V
VREF,VTT(+0.75V) MVCCIP(+3.3V) MGTAVTT(+1.2V)
MGTVCCAUX(+1.8V)
Function FPGA Core Voltage FPGA auxiliary voltage, TPS74801 power supply VCCIO
of Bank0,Bank13 and Bank14 of FPGA,QSIP FLASH, Clock Crystal DDR3, Bank34 and
Bank35 of FPGA
DDR3 FPGA Bank15, Bank16 GTP Transceiver Bank216 of FPGA GTP Transceiver
Bank216 of FPGA
Because the power supply of Artix-7 FPGA has the power-on sequence requirement, in the circuit design, we have designed according to the power requirements of the chip, and the power-on is 1.0V->1.8V->(1.5 V, 3.3V, VCCIO) and 1.0V-> MGTAVCC -> MGTAVTT, the circuit design to ensure the normal operation of the chip.
Part 2.13: Structure Diagram
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3: Carrier board
Part 3.1: Carrier board Introduction
Through the previous function introduction, you can understand the function of
the carrier board part
1-channel PCIe x4 high speed data transmission interface 2-channel
10/100M/1000M Ethernet RJ-45 interface 1-channel HDMI video input interface
1-channel HDMI video Output interface 1-channel USB Uart Communication
interface 1 SD Card Slot XADA Interface EEPROM 2-channel 40-pin expansion
ports JTAG debugging interface 2 independent keys 4 user LED lights
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.2: Gigabit Ethernet Interface
The AX7203 FPGA development board provides users with 2-channel
Gigabit network communication service through the Micrel KSZ9031RNX
Ethernet PHY chip. The KSZ9031RNX chip supports 10/100/1000 Mbps
network transmission rate and communicates with the FPGA through the GMII
interface. KSZ9031RNX supports MDI/MDX adaptation, various speed
adaptations, Master/Slave adaptation, and support for MDIO bus for PHY
register management.
The KSZ9031RNX will detect the level status of some specific IOs to
determine their working mode after powered on. Table 3-1-1 describes the
default setup information after the GPHY chip is powered on.
Configuration Pin Instructions
Configuration value
PHYAD[2:0] CLK125_EN
SELRGV AN[1:0] RX Delay TX Delay
MDIO/MDC Mode PHY Address 3.3V, 2.5V, 1.5/1.8V voltage selection Auto-
negotiation configuration
RX clock 2ns delay TX clock 2ns delay RGMII or GMII selection
PHY Address 011 3.3V
(10/100/1000M) adaptive Delay Delay GMII
Table 3-2-1: PHY chip default configuration value
When the network is connected to Gigabit Ethernet, the data transmission of
FPGA and PHY chip KSZ9031RNX is communicated through the GMII bus, the
transmission clock is 125Mhz. The receive clock E_RXC is provided by the PHY
chip, the transmit clock E_GTXC is provided by the FPGA, and the data is
sampled on the rising edge of the clock.
When the network is connected to 100M Ethernet, the data transmission of FPGA
and PHY chip KSZ9031RNX is communicated through the GMII bus, the transmission
clock is 25Mhz. The receive clock E_RXC is provided by the PHY chip, the
transmit clock E_GTXC is provided by the FPGA, and the data is
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ARTIX-7 FPGA Development Board AX7203 User Manual sampled on the rising edge
of the clock.
Figure 3-2-1: Gigabit Ethernet Interface Schematic
Figure 3-3-2: Gigabit Ethernet interface on the Carrier board
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gigabit Ethernet Chip PHY1 pin assignments are as follows
Signal Name E1_GTXC E1_TXD0 E1_TXD1 E1_TXD2 E1_TXD3 E1_TXEN E1_RXC E1_RXD0 E1_RXD1 E1_RXD2 E1_RXD3 E1_RXDV E1_MDC E1_MDIO E1_RESET
FPGA Pin Number E18 C20 D20 A19 A18 F18 B17 A16 B18 C18 C19 A15 B16 B15 D16
Description PHY1 RGMII transmit clock
PHY1 Transmit Data bit0 PHY1 Transmit Data bit1 PHY1 Transmit Data bit2 PHY1
Transmit Data bit3 PHY1 Transmit Enable Signal PHY1 RGMII Receive Clock PHY1
Receive Data Bit0 PHY1 Receive Data Bit1 PHY1 Receive Data Bit2 PHY1 Receive
Data Bit3 PHY1 receive data valid signal PHY1 Management Clock PHY1 Management
Data
PHY1 Reset Signal
Gigabit Ethernet Chip PHY2 pin assignments are as follows
Signal Name E2_GTXC E2_TXD0 E2_TXD1 E2_TXD2 E2_TXD3 E2_TXEN E2_RXC E2_RXD0 E2_RXD1 E2_RXD2 E2_RXD3 E2_RXDV E2_MDC E2_MDIO E2_RESET
FPGA Pin Number A14 E17 C14 C15 A13 D17 E19 A20 B20 D19 C17 F19 F20 C22 B22
Description PHY2 RGMII transmit clock
PHY2 Transmit Data bit0 PHY2 Transmit Data bit1 PHY2 Transmit Data bit2 PHY2
Transmit Data bit3 PHY2 Transmit Enable Signal PHY2 RGMII Receive Clock PHY2
Receive Data Bit0 PHY2 Receive Data Bit1 PHY2 Receive Data Bit2 PHY2 Receive
Data Bit3 PHY2 receive data valid signal PHY2 Management Clock PHY2 Management
Data
PHY2 Reset Signal
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.3: PCIe x4 Interface
The AX7203 FPGA development board provides an industrial-grade high-speed data
transfer PCIe x4 interface. The PCIE card interface conforms to the standard
PCIe card electrical specifications and can be used directly on the x4 PCIe
slot of a normal PC.
The transmit and receive signals of the PCIe interface are directly connected
to the GTP transceiver of the FPGA. The four channels of TX and RX signals are
connected to the FPGA in differential signals, and the single channel
communication rate can be up to 5G bit bandwidth. The PCIe reference clock is
provided to the AX7203 FPGA development board by the PCIe slot of the PC with
a reference clock frequency of 100Mhz.
The design diagram of the PCIe interface of the AX7203 FPGA development board
is shown in Figure 3-3-1, where the TX transmit signal and the reference clock
CLK signal are connected in AC coupled mode.
Figure 3-3-1: PCIex4 schematic
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-3-2: PCIex4 on the Carrier board
PCIex4 Interface Pin Assignment:
Signal Name
FPGA Pin
PCIE_RX0_P
D11
PCIE_RX0_N
C11
PCIE_RX1_P
B8
PCIE_RX1_N
A8
PCIE_RX2_P
B10
PCIE_RX2_N
A10
PCIE_RX3_P
D9
PCIE_RX3_N
C9
PCIE_TX0_P
D5
PCIE_TX0_N
C5
PCIE_TX1_P
B4
PCIE_TX1_N
A4
PCIE_TX2_P
B6
PCIE_TX2_N
A6
PCIE_TX3_P
D7
PCIE_TX3_N
C7
PCIE_CLK_P
F10
PCIE_CLK_N
E10
Description PCIE Channel 0 Data Receive Positive PCIE Channel 0 Data Receive
Negative PCIE Channel 1 Data Receive Positive PCIE Channel 1 Data Receive
Negative PCIE Channel 2 Data Receive Positive PCIE Channel 2 Data Receive
Negative PCIE Channel 3 Data Receive Positive PCIE Channel 3 Data Receive
Negative PCIE Channel 0 Data Transmit Positive PCIE Channel 0 Data Transmit
Negative PCIE Channel 1 Data Transmit Positive PCIE Channel 1 Data Transmit
Negative PCIE Channel 2 Data Transmit Positive PCIE Channel 2 Data Transmit
Negative PCIE Channel 3 Data Transmit Positive PCIE Channel 3 Data Transmit
Negative
PCIE Reference Clock Positive PCIE Reference Clock Negative
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.4: HDMI output interface
HDMI output interface, select Silion Image’s SIL9134 HDMI (DVI) encoding chip,
support up to 1080P@60Hz output, support 3D output.
The IIC configuration interface of SIL9134 is also connected to the IO of the
FPGA. The SIL9134 is initialized and controlled by FPGA programming. The
hardware connection of the HDMI output interface is shown in Figure 3-4-1.
Figure 3-4-1: HDMI Output Schematic
Figure 3-4-1: HDMI Output on the Carrier board
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ARTIX-7 FPGA Development Board AX7203 User Manual
HDMI Input Pin Assignment:
Signal Name 9134_nRESET
9134_CLK 9134_HS 9134_VS 9134_DE 9134_D[0] 9134_D[1] 9134_D[2] 9134_D[3]
9134_D[4] 9134_D[5] 9134_D[6] 9134_D[7] 9134_D[8] 9134_D[9] 9134_D[10]
9134_D[11] 9134_D[12] 9134_D[13] 9134_D[14] 9134_D[15] 9134_D[16] 9134_D[17]
9134_D[18] 9134_D[19] 9134_D[20] 9134_D[21] 9134_D[22] 9134_D[23]
FPGA Pin J19 M13 T15 T14 V13 V14 H14 J14 K13 K14 L13 L19 L20 K17 J17 L16 K16 L14 L15 M15 M16 L18 M18 N18 N19 M20 N20 L21 M21
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.5: HDMI Input interface
HDMI output interface, select Silion Image’s SIL9013 HDMI decoder chip,
support up to 1080P@60Hz input and support data output in different formats.
The IIC configuration interface of the SIL9013 is connected to the IO of the
FPGA. The SIL9013 is initialized and controlled through FPGA programming. The
hardware connection of the HDMI input interface is shown in Figure 3-5-1.
Figure 3-5-1: HDMI Input Schematic
Figure 3-5-2: HDMI Input on the Carrier board
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ARTIX-7 FPGA Development Board AX7203 User Manual
HDMI Input Pin Assignment:
Signal Name 9013_nRESET
9013_CLK 9013_HS 9013_VS 9013_DE 9013_D[0] 9013_D[1] 9013_D[2] 9013_D[3]
9013_D[4] 9013_D[5] 9013_D[6] 9013_D[7] 9013_D[8] 9013_D[9] 9013_D[10]
9013_D[11] 9013_D[12] 9013_D[13] 9013_D[14] 9013_D[15] 9013_D[16] 9013_D[17]
9013_D[18] 9013_D[19] 9013_D[20] 9013_D[21] 9013_D[22] 9013_D[23]
FPG Pin Number H19 K21 K19 K18 H17 H18 N22 M22 K22 J22 H22 H20 G20 G22 G21 D22 E22 D21 E21 B21 A21 F21 M17 J16 F15 G17 G18 G15 G16
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.6: SD Card Slot
The SD card (Secure Digital Memory Card) is a memory card based on the
semiconductor flash memory process. It was completed in 1999 by the Japanese
Panasonic-led concept, and the participants Toshiba and SanDisk of the United
States conducted substantial research and development. In 2000, these
companies launched the SD Association (Secure Digital Association), which has
a strong lineup and attracted a large number of vendors. These include IBM,
Microsoft, Motorola, NEC, Samsung, and others. Driven by these leading
manufacturers, SD cards have become the most widely used memory card in
consumer digital devices.
The SD card is a very common storage device. The extended SD card supports SPI
mode and SD mode. The SD card used is a MicroSD card. The schematic diagram is
shown in Figure 3-6-1.
Figure 3-6-1: SD Card Schematic
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-6-2: SD Card Slot on the Carrier board
SD card slot pin assignment:
Signal Name SD_CLK SD_CMD SD_CD_N SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3
SD Mode
FPGA PIN AB12 AB11 F14 AA13 AB13 Y13 AA14
Part 3.7: USB to Serial Port
The AX7203 FPGA development board includes the USB-UAR chip of Silicon Labs
CP2102GM. The USB interface uses the MINI USB interface. It can be connected
to the USB port of the upper PC for serial data communication with a USB
cable. The schematic diagram of the USB Uart circuit design is shown in Figure
3-7-1:
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ARTIX-7 FPGA Development Board AX7203 User Manual Figure 3-7-1: USB to serial port schematic
Figure 3-7-2: USB to serial port on the Carrier board
Two LED indicators (LED3 and LED4) are set for the serial port signal, and the
silkscreen on the PCB is TX and RX, indicating that the serial port has data
transmission or reception, as shown in the following Figure 3-3-3
Figure 3-7-3: Serial Port communication LED Indicators Schematic
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ARTIX-7 FPGA Development Board AX7203 User Manual
USB to serial port pin assignment:
Signal Name UART1_RXD UART1_TXD
FPGA PIN P20 N15
Part 3.8: EEPROM 24LC04
AX7013 carrier board contains an EEPROM, model 24LC04, and has a capacity of
4Kbit (22568bit). It consists of two 256-byte blocks and communicates via
the IIC bus. The onboard EEPROM is to learn how to communicate with the IIC
bus. The I2C signal of the EEPROM is connected to the BANK14 IO port on the
FPGA side. Figure 3-8-1 below shows the design of the EEPROM
Figure 3-8-1: EEPROM Schematic
Figure 3-8-2: EEPROM on the Carrier board
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ARTIX-7 FPGA Development Board AX7203 User Manual
EEPROM Pin Assignment
Net Name EEPROM_I2C_SCL EEPROM_I2C_SDA
FPGA PIN F13 E14
Part 3.9: Expansion Header
The carrier board is reserved with two 0.1inch spacing standard 40-pin
expansion ports J11 and J13, which are used to connect the ALINX modules or
the external circuit designed by the user. The expansion port has 40 signals,
of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle
ground and 34 IOs. Do not directly connect the IO directly to the 5V device to
avoid burning the FPGA. If you want to connect 5V equipment, you need to
connect level conversion chip.
A 33 ohm resistor is connected in series between the expansion port and the
FPGA connection to protect the FPGA from external voltage or current. The
circuit of the expansion port (J11) is shown in Figure 3-9-1.
Figure 3-9-1: Expansion header J11 schematic
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ARTIX-7 FPGA Development Board AX7203 User Manual
The figure 3-9-2 detailed the J4 expansion port on the carrier board. The Pin1
and Pin2 of the expansion port are already marked on the board.
Figure 3-9-2: Expansion header J11 on the Carrier board
J11 Expansion Header Pin Assignment
Pin Number
FPGA Pin
Pin Number
FPGA Pin
1
GND
2
+5V
3
P16
4
R17
5
R16
6
P15
7
N17
8
P17
9
U16
10
T16
11
U17
12
U18
13
P19
14
R19
15
V18
16
V19
17
U20
18
V20
19
AA9
20
AB10
21
AA10
22
AA11
23
W10
24
V10
25
Y12
26
Y11
27
W12
28
W11
29
AA15
30
AB15
31
Y16
32
AA16
33
AB16
34
AB17
35
W14
36
Y14
37
GND
38
GND
39
+3.3V
40
+3.3V
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-9-3: Expansion header J13 schematic
The figure 3-9-4 detailed the J13 expansion port on the carrier board. The
Pin1 and Pin2 of the expansion port are already marked on the board.
Figure 3-9-4: Expansion header J13 on the carrier board
J13 Expansion Header Pin Assignment
Pin Number
FPGA Pin
1
GND
3
W16
5
V17
7
U15
Pin Number 2 4 6 8
FPGA Pin +5V W15 W17 V15
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ARTIX-7 FPGA Development Board AX7203 User Manual
9
AB21
10
AB22
11
AA21
12
AA20
13
AB20
14
AA19
15
AA18
16
AB18
17
T20
18
Y17
19
W22
20
W21
21
T21
22
U21
23
Y21
24
Y22
25
W20
26
W19
27
Y19
28
Y18
29
V22
30
U22
31
T18
32
R18
33
R14
34
P14
35
N13
36
N14
37
GND
38
GND
39
+3.3V
40
+3.3V
Part 3.10: JTAG Interface
A JTAG interface is reserved on the AX7203 FPGA carrier board for downloading
FPGA programs or firmware to FLASH. In order to prevent damage to the FPGA
chip caused by hot plugging, a protection diode is added to the JTAG signal to
ensure that the voltage of the signal is within the range accepted by the FPGA
to avoid damage of the FPGA chip.
Figure 3-10-1: JTAG Interface Schematic
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-10-2: JTAG Interface on the carrier board
Be careful not to hot swap when JTAG cable is plugged and unplugged.
Part 3.11: XADC interface (not installed by default)
The AX7203 carrier board has an extended XADC connector interface, and the
connector uses a 2×8 0.1inch pitch double-row pin. The XADC interface extends
three pairs of ADC differential input interfaces to the 12-Bit 1Msps analog-
to-digital converter of the FPGA. One pair of differential interfaces is
connected to the dedicated differential analog input channel VP/VN of the
FPGA, and the other two pairs are differentially connected to the auxiliary
analog input channels (analog channel 0 and analog channel 9). Figure 3-11-1
shows an anti-aliasing filter designed for three differential XADC inputs.
Figure 3-11-1: Anti-Aliasing filter Schematic
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-11-2: XADC Connector Schematic
Figure 3-11-3: XADC Connector on the Carrier board
XADC Pin Assignment
XADC Interface
FPGA Pin Input amplitude
Description
12 56 910
VP_0 : L10 VN_0 : M9 AD9P : J15 AD9N : H15 AD0P : H13 AD0N : G13
Peak to peak 1V FPGA-specific XADC input channel
Peak to peak 1V Peak to peak 1V
FPGA-assisted XADC input channel 9 (can be used as normal IO)
FPGA-assisted XADC input channel 0 (can be used as normal IO)
Part 3.12: keys
The AX7203 FPGA carrier board contains two user keys KEY1~KEY2. All keys are
connected to the normal IO of the FPGA. The key is active low. When the key is
pressed, the IO input voltage of the FPGA is low. When no key is pressed, The
IO input voltage of the FPGA is high. The circuit of the key part is shown in
Figure 3-12-1.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-12-1: key Schematic
Figure 3-13-2: Two keys on the Carrier board
keys Pin Assignment
Net Name KEY1 KEY2
FPGA PIN J21 E13
Part 3.13: LED Light
There are seven red LEDs on the AX7203 FPGA carrier board, one of which is the
power indicator (PWR), two are USB Uart data receiving and transmitting
indicators, and four are users LED lights (LED1~LED4). When the board is
powered on, the power indicator will light up; User LED1~LED4 are connected to
the normal IO of the FPGA. When the IO voltage connected to the user LED is
configured low level, the user LED lights up. When the connected IO voltage is
configured as high level, the user LED will be extinguished. The
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ARTIX-7 FPGA Development Board AX7203 User Manual
schematic diagram of the user LEDs hardware connection is shown in Figure
3-13-1.
Figure 3-13-1: The User LEDs Schematic
Figure 3-13-2: The User LEDs on the Carrier board
Pin assignment of user LED lights
Signal Name LED1 LED2 LED3 LED4
FPGA PIN B13 C13 D14 D15
Part 3.14: Power Supply
The power input voltage of the AX7203 FPGA development board is DC12V. The
development board also supports power from the PCIe interface and supports
direct power supply from the ATX chassis power supply (12V).
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-14-1: Power supply method for AX7203 FPGA Board The FPGA carrier
board converts the +12V voltage into +5V, +3.3V, +1.8V and +1.2V four-way
power supply through the 4-channel DC/DC power supply chip MP1482. In
addition, the +5V power supply on the FPGA carrier board supplies power to the
AC7100B FPGA core board through the inter-board connector. The power supply
design on the expansion is shown in Figure 3-14-2.
Figure 3-14-2: Power supply Schematic on the Carrier board
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ARTIX-7 FPGA Development Board AX7203 User Manual Figure 3-14-3: Power Supply Circuit on the Carrier board
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