ALINX AN5640 5MP Monocular Camera Module User Manual

AN5640 5MP Monocular Camera Module

Camera Module AN5640 User Manual

The Camera Module AN5640 is a camera module that uses CMOS chip image sensor OV5640 from OmniVision Corporation of the United States. It supports auto focus function and has DVP and MIPI interfaces. Images are transmitted through the DVP interface and the FPGA connection. The module interface is DVP interface and it supports image sizes of 5 megapixels. The photosensitive chip is OV5640 with an optical size of 1/4. The module content includes OV5640 power supply circuit, flash drive circuit. It has manual focus, automatic exposure control (AEC), automatic white balance (AWB) functions. It supports output formats such as RAW RGB, RGB565/555/444, CCIR656, YUV422/420, YCbCr422, and compression. The maximum image transfer rate is QSXGA (2592×1944): 15 fps 1080 30 fps 1280×960: 45 fps 720p: 60 fps VGA (640×480): 90 fps QVGA (320×240): 120 fps.

Part 1.2 – Chip OV5640 power-on requirements
The power-on steps of the chip OV5640 are as follows:

1. ResetB is pulled low, reset AN5640, PWDN is pulled high.
2. Both DOVDD and AVDD are powered up simultaneously, which is implemented in the power supply design of the module.
3. After 5ms of AVDD reaching stable, pull PWDN to low.
4. After 1ms of PWDN go low, pull high ResetB.
5. After 20ms, initialize OV5640 by SCCB initialization.

Part 1.3 – Register Configuration of CMOS Chip OV5640
The register configuration of the OV5640 is configured through the I2C interface of the FPGA (or other CPU). The user needs to configure the correct register value to let the OV5640 output the image format needed. In our example, we configure the OV5640 as the image format of the 720P (1280×720) video output image and the RGB565 frame rate of 30fps. To facilitate debugging, the user can configure registers to enable internal test images of the OV5640,such as color bars and color squares. The data format of the OV5640’s camera output is configured in the following 0x4300 registers. In our example, the OV5640 is configured as an RGB565 output format. There are many more registers on the OV5640, but many register users do not need to understand, the configuration of The registers can be configured according to the OV5640 application guide. If you want to know more about the register information, you can refer to the register description in the OV5640 datasheet.

Camera Module AN5640 General Description

The camera module AN5640, use CMOS chip image sensor OV5640 from OmniVision Corporation of the United States, which supporting auto focus function. The CMOS OV5640 chip supports DVP and MIPI interfaces. On the OV5640 module, images are transmitted through the DVP interface and the FPGA connection. Figure 1-1 detailed the AN5640 module product photo.

Figure 1-1: AN5640 module product photo

AN5640 Camera Module Detail Parameter

• Module Interface: DVP interface

• support for images sizes: 5 megapixel

• Photosensitive chip: OV5640

• optical size of 1/4″

• Module content: OV5640 power supply circuit, flash drive circuit

• automatic image control functions: Manual focus, automatic exposure control (AEC), automatic white balance (AWB)

• support for output formats: RAW RGB, RGB565/555/444, CCIR656, YUV422/420, YCbCr422, and compression

• maximum image transfer rate: QSXGA (2592×1944): 15 fps
  1080 30 fps
  1280×960: 45 fps
  720p: 60 fps
  VGA (640×480): 90 fps QVGA (320×240): 120 fps

• Working temperature: -30~70°C, stable working temperature is 0~50°C

Chip OV5640 power-on requirements

• t0:>=0ms. Delay from DOVDD stable to AVDD stable
• t2:>=5ms. Delay from AVDD stable to sensor power up stable
• t3:>=1ms. Delay from sensor power up stable to Reset# pull high
• t4:>=20ms. Delay from Reset pull high to SCCB initialization

The power-on steps of the chip OV5640 are as follows:

• Step 1: ResetB is pulled low, reset AN5640, PWDN is pulled high
• Step 2: Both DOVDD and AVDD are powered up simultaneously, which is implemented in the power supply design of the module.
• Step 3: After 5ms of AVDD reaching stable, pull PWDN to low.
• Step 4: After 1ms of PWDN go low, pull high ResetB
• Step 5: After 20ms, initialize OV5640 by SCCB initialization:

Register Configuration of CMOS Chip OV5640
The register configuration of the OV5640 is configured through the I2C interface of the FPGA (or other CPU). The user needs to configure the correct register value to let the OV5640 output the image format we need. In our example, we configure the OV5640 as the image format of the 720P (1280×720) video output image and the RGB565 frame rate of 30fps.
To facilitate debugging, the user can configure registers to enable internal test images of the OV5640, such as color bars and color squares.

Color bar

• write_i2c(0x503d, 0x80);
• write_i2c(0x4741, 0x00);

Color square

• write_i2c(0x503d, 0x82);
• write_i2c(0x4741, 0x0);

The data format of the OV5640’s camera output is configured in the following 0x4300 registers. In our example, the OV5640 is configured as an RGB565 output format.

There are many more registers on the OV5640, but many register users do not need to understand, the configuration of the registers can be configured according to the OV5640 application guide. If you want to know more about the register information, you can refer to the register description in the OV5640 datasheet.

Hardware Connection

The following ALINX AX301 FPGA development board is an example to introduce the hardware connection of the camera module AN5640 and ALINX serial FPGA development kit. The 18-pin female headers of camera module AN5640 detailed in future 2-1.

Figure 2-1: 8-pin Female header of Camera Module AN5640

On the AX301 FPGA development board, there is a 16-pin CAMERA interface (J5). When the OV5640 module is connected to the development board, simply insert the module into the CAMERA interface on the development board. Pin1 of the module is aligned with Pin1 of the CAMERA interface on the development board (square pad is 1 pin). Figure 2-2 detailed the camera module connected with AX301 FPGA board.

Figure 2-2: The Camera Module Connected with AX301 FPGA Board

After the connection, the pin correspondence between the OV5640 and the FPGA of the development board AX301 is as follows:

If it is the development board of AX515, AX530 or other ALINX serial FPGA Board, because there is no camera interface on the development board, we need to connect the camera module with our adapter board and insert the adapter board into the expansion port of the development board (AX515 and AX530 are expansion port J3; AX822 is the expansion port J15), then insert the camera module into the expansion board. Figure 2-3 detailed the camera module connected with AX515 FPGA board.

Figure 2-3: The Camera Module Connected with AX515 FPGA Board

AN5640 VGA Display Experiment
In this experiment, the AX301 development board is taken as an example. The 1024*720 video image of OV5640 is output to the VGA display. After the program is powered on, the register of the OV5640 is set, and the image of the acquisition camera is stored in the SDRAM. The image data is then taken out of the SDRAM and displayed on the VGA display.

Programming
In the program, the SDRAM memory space is divided into two areas (Bank0 and Bank3), and the SDRAM is read and written in different Bank spaces. When Bank0 is writing the image captured by the camera, VGA reads the data display of Bank3; after the Bank0 finish to write an image, the space of reading and writing is exchanged, Bank3 starts to write the image captured by the camera, and Bank0 is the image for reading out the VGA output.

In addition, the image obtained from the OV5640 camera is 1024 x 720 image size, and the VGA display can only display 1024×768 image data. We need to add black background data to the extra 48 lines in the VGA display program.
The OV5640 VGA display routine consists of a top-level module sdram_ov5640_vga.v, a power-on waiting program power_on_delay.v, a register configuration program reg_config.v, a camera data acquisition program CMOS_Capture.v, a VGA display and SDRAM control program sdram_vga_top. v, a system control module system_ctrl.v.

The completed engineering architecture is shown in the figure below:

The function description of each module, detailed as below:

1. Power-on waiting program：power_on_delay.v
   Because the OV5640 chip has power-on timing requirements, this program is waiting for a period of time after the FPGA is powered on and then enabling the OV5640 register to meet the timing requirements of the OV5640.

2. OV5640 register configuration module：reg_config.v
   After power-on the FPGA, the register configuration program of the OV5640 calls the I2C communication program to set the parameters of the register of OV5640 chip. Here the images output by the OV5640 chip is set to RGB565 format, and the numbers of image is 1280*720.

3. Camera Image Acquisition Program：COMS_Capture.v
   The camera image acquisition program converts the 8-bit image from the OV5640 module into a 16-bit data width and generates a write signal for the SDRAM. In addition, the program generates a frame_valid signal to indicate that an image acquisition is completed, and informs the read and write space exchange of Bank0 and Bank3 of SDRAM.

4. Sdram Control and Read/Write Program: sdram_top.v
   The sdram_top module and three submodules (sdram_ctrl.v, sdram_cmd.v, sdram_wr_data.v) implement sdram initialization, user interface read and write command parsing, sdram burst read and write, self-refresh and pre-charge operation control and etc.
   The sdram_ctrl module implements SDRAM initialization, 60ms self-refresh, user read and write request command parsing, and uses status machines and counters to generate status bits for different SDRAM operations.
   The sdram_cmd module is based on the state machine init_state and work_state generated in the sdram_ctrl module, to generate various SDRAM control or burst read and write commands.
   Sdram_wr_data module is SDRAM read and write bidirectional data control module, When writing SDRAM, the data is transferred to the SDRAM data bus, and when the SDRAM is read, the data on the SDRAM bus is transferred to the user interface.

5. FIFO Control Program Module: dcfifo_ctrl.v
   The Dcfifo_ctrl.v module is used to control the read FIFO, write FIFO, SDRAM read and write commands and read and write addresses. In this experiment, the data written to the SDRAM is first stored in the write FIFO, and the data read from the SDRAM is first stored in the read FIFO.A DDR burst write request is generated when the amount of data in the write FIFO is greater than the set write burst length (128)The Sdram read request is generated when the amount of data in the read FIFO is less than the set read burst length (128 ).

6. VGA Display Program: lcd_driver.vThe vga_disp.v module implements image display of a VGA display, and generates line synchronization, column synchronization, and timing of image data signals according to the VGA timing standard. VGA clock frequency: Take 1024×768@59.94MHz (60Hz) as an example. Each field corresponds to 806 line periods, of which 768 is the display line. Each display line includes 1344 points of clock, of which 1024 points are valid display areas. It can be seen that the clock frequency of VGA is required: 806134460 is about 65MHz. Figure 3-5 and figured 3-6 detailed the timing diagram of VGA:In addition, because the video image output by OV5640 is 1024×720 image size, but the VGA display is 1024×768 image, in order to make the video image in the middle of the VGA display, black image data has been inserted in the first 24 lines and the last 24 lines of the VGA image

7. SDRAMBank exchange program: sdbank_switch.
   The Bank exchange program implements SDRAM read and SDRAM write in different Bank operations. When Bank0 writes the image captured by the camera, VGA reads Bank3 data display; after Bank0 writes an image finished, SDRAM reads and writes space exchange, Bank3 starts to write the image captured by the camera, and Bank0 reads the image output by the VGA.

8. System Control Program: system_ctrl.v
   Generate SDRAM clock (100Mhz) and VGA image clock (65Mhz), and the program also generates a reset signal for the entire system.
   Part 3.2. OV5640 VGA display experiment
   After writing the program, assign the pin of the FPGA and recompile it to start the OV5640 VGA display experiment. The development board connect with the camera module and VGA interface to connect VGA display, then download sof file to FPGA, you can see 1024×768 video image on VGA monitor. Figure 3-8 and Figure 3-9 detailed the video image effect.

LCD Display Experiment

This experiment demonstrates the video image of the OV5640 with an ALINX 7-inch LCD display, which is displayed on a 7-inch LCD screen. In the experiment, taking the AX301 development board as an example, the OV5640’s 800*480 image size video image is output to the LCD for display. After the program is powered on, the OV5640 register is set first, and then the image of the acquisition camera is stored in the SDRAM. The image data is taken out from the SDRAM and displayed on the LCD display.

Programming
The programming ideas and methods are basically the same as the OV5640 VGA display example. Just explain the difference between the OV5640 LCD display and the OV5640 VGA display experiment.

1. LCD driver program: lcd_driver.v
   The 7-inch LCD display has an image size of 800×480 and an image refresh rate of 60hz. The LCD driver displays the image of the LCD screen and generates line synchronization, column synchronization, DE and image data signal timing according to the data sheet of the LCD screen. The display timing requirements of the LCD screen are as follows:Please refer to the LCD datasheet for specific timing requirements.

2. System Control Program: system_ctrl.v 7-inch LCD clock frequency is 25Mhz

3. OV5640 Register Configurator Program: reg_config.v Configure the image output of the OV5640 to be 800×480 pixel size

OV5640LCD Display Experiment
After writing the program, assign the pin of the FPGA, and after recompilation, we can start the OV5640 LCD display experiment. The FPGA development board connected with the camera module OV5640 and 7” LCD screen with LCD interface (P3), then after downloading the sof file to the FPGA, we can see the 800×480 video image on the LCD screen.

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References

• ALINX 芯驿电子科技（上海）有限公司

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