ALINX ACU3EG ZYNQ UltraScale Plus FPGA Core Board User Manual

ACU3EG ZYNQ UltraScale Plus FPGA Core Board
User Manual
Version Record

Part 1: AXU2CGA/B Introduction

The AXU2CGA/B Board is characterized by its small size and extensive peripherals. The main chip is Xilinx’s Zynq UltraScale+ MPSoCs CG family chip, the model is XCZU2CG-1SFVC784E. The PS side of AXU2CGA is mounted with 2 slices of DDR4 (total 1GB, 32bit) and 1 slice of 256Mb QSPI FLASH. The PS side of AXU2CGB is equipped with 4 DDR4 (total 2GB, 64bit), one 8GB eMMC FLASH memory chip and one 256Mb QSPI FLASH.
Peripheral interfaces include 1 MINI DP interface, 4 USB3.0 interfaces, 1 Gigabit Ethernet interface, 1 USB serial port, 1 PCIE interface, 1 TF card interface, 2 40-pin expansion ports, 2 MIPI Interface, KEYs and LEDs.
The board schematic is as Figure 1-1:

Part 2: ZYNQ Chip

The PS system of the XCZU2CG-1SFVC784E chip integrates two ARM Cortex™-A53 processors with a speed of up to 1.2Ghz and supports Level 2 Cache; it also contains two Cortex-R5 processors with a speed of up to 500Mhz. The XCZU2CG Chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L, and LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0, Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, GPIO, and other interfaces. The PL end contains a wealth of programmable logic units, DSP and internal RAM. The overall block diagram of the XCZU2CG chip is shown in the Figures 2-1:

The main parameters of the PS system are as follows:

• ARM dual-core Cortex™-A53 processor, speeds up to 1.2GHz, each CPU 32KB level 1 instruction and data cache, 1MB level 2 cache, shared by 2 CPUs
• ARM dual-core Cortex-R5 processor, speeds up to 500MHz, each CPU 32KB level 1 instruction and data cache, and 128K tightly coupled memory
• External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3 interface
• Static storage interface, support NAND, 2xQuad-SPI FLASH
• High-speed connection interface, support PCIe Gen2 x4, 2xUSB3.0, SATA 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet
• Common connection interface: 2xUSB2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
• Power management: support the division of Full/Low/PL/Battery four parts of the power
• Encryption algorithm: support RSA, AES, and SHA
• System monitoring: 10-bit 1Mbps AD sampling for temperature and voltage detection
• The main parameters of the PL logic part are as follows:
• Logic Cells: 103K
• flip-flops: 94K
• Lookup table (LUTs) : 47K；
• Block RAM: 5.3Mb
• Clock Management Unit (CMTs) : 3
• Multiplier 18x25MACCs: 240

Part 3: DDR4 DRAM

There are two Micron DDR4 chips on the PS side of the AXU2CGA board, which form a 32-bit data bus bandwidth and a total capacity of 1GB. There are 4 Micron DDR4 chips on the PS side of the AXU2CGB board, which form a 64-bit data bus bandwidth and a total capacity of 2GB. The maximum operating speed of DDR4 SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps). The specific configuration of DDR4 SDRAM is shown below.
Among them, U71 and U72 are only AXU2CGB mounted.

Table 3-1: DDR4 SDRAM Configuration
The hardware connection of DDR4 on the PS side is shown in Figure 3-1:

AXU2CGA PS side DDR4 SDRAM Pin Assignment:

AXU2CGB  PS side DDR4 SDRAM data pin assignment is the same as
AXU2CGA,  additional data signal assignment is as follows:

Part 4: QSPI Flash

The AXU2CGA/B board has a 256MBit Quad-SPI FLASH chip, the model is MT25QU256ABA1EW9-0SIT. QSPI FLASH is connected to the GPIO port of BANK500 in the PS part of the ZYNQ chip. Figure 4-1 shows the part of QSPI Flash in the schematic.

Configure Chip Pin Assignment:

Part 5: eMMC Flash (Only for AXU2CGB)

There is an eMMC FLASH chip with a capacity of 8GB on the AXU2CGB board. The eMMC FLASH is connected to the GPIO port of the BANK500 of the PS part of ZYNQ UltraScale+. Figure 5-1 is the eMMC Flash schematic.

Configure Chip Pin Assignment:

Part 6: EEPROM

The AXU2CGA/B development board has a piece of EEPROM onboard, the model number is 24LC04. The I2C signal of the EEPROM is connected to the MIO port of the ZYNQ PS side. Figure 6-1 is EEPROM schematic:

EEPROM Pin Assignment:

Part 7: DP Display Interface

The AXU2CGA/B board has a MINI-type DisplayPort output display interface, which is used for video image display, and supports up to 4K x 2K@30Fps output. The TX signals of LANE0 and LANE1 of ZU2CG PS MGT are connected to the DP connector in a differential signal mode. The DisplayPort auxiliary channel is connected to the MIO pin of the PS. The schematic diagram of the DP output interface is shown in Figure 7-1:

The DisplayPort interface ZYNQ pin assignment is as follows:

Signal Name| ZYNQ Pin Number| ZYNQ Pin Number| Description
---|---|---|---
GT0_DP_TX_P| PS_MGTTXP3_505| B23| Low bits of DP Data Transmit Positive
GT0_DP_TX_N| PS_MGTTXN3_505| B24| Low bits of DP Data Transmit Negative
GT1_DP_TX_P| PS_MGTTXP2_505| C25| High bits of DP Data Transmit Positive
GT1_DP_TX_N| PS_MGTTXN2_505| C26| High bits of DP Data Transmit Negative
505_DP_CLKP| PS_MGTREFCLK2P_50 5| C21| DP Reference Clock Positive
505_DP_CLKP| PS_MGTREFCLK2N_50 5| C22| DP Reference Clock Negative
DP_AUX_OUT| PS_MIO27| J15| DP Auxiliary Data Output
DP_AUX_IN| PS_MIO30| F16| DP Auxiliary Data Input
DP_OE| PS_MIO29| G16| DP Auxiliary Data Output Enable
DP_HPD| PS_MIO28| K15| DP Insertion Signal Detection

Part 8: USB 3.0 Interface

There are 4 USB3.0 interfaces on the AXU2CGA/B board, the interface is HOST working mode (Type A), and the data transmission speed is up to 5.0Gb/s. The USB3.0 interfaces connect external USB PHY chip and USB3.0 HUB chip through ULPI interface to realize high-speed USB3.0 data communication.
The USB Schematic is shown in Figure 8-1:

USB Pin Assignment:

Part 9: Gigabit Ethernet Interface

There is 1 Gigabit Ethernet interface on AXU2CGA/B, and the Ethernet interface is on BANK502 of PS connected through the GPHY chip. The GPHY chip uses the KSZ9031RNXIC Ethernet PHY chip from Micrel, and the PHY Address is 001. Figure 9-1 is a schematic diagram of the connection of the Ethernet PHY chip on the ZYNQ PS side:

The Gigabit Ethernet pin assignments are as follows:

Part 10: USB to Serial Port

There is a Uart to USB interface on the AXU2CGA/B board for system debugging. The conversion chip uses the USB-UAR chip of Silicon Labs CP2102, and the USB interface uses the MINI USB interface. It can be connected to the USB port of the PC with a USB cable for independent power supply of the core board and serial data communication. The schematic diagram of the USB Uart circuit design is shown in Figure 10-1:

USB to serial port ZYNQ pin assignment:

Part 11: SD Card Slot Interface

The AXU2CGA/B board contains a Micro SD card interface. The SDIO signal is connected to the IO signal of BANK501. The SD card connector schematic is shown in Figure 11-1.

SD card slot pin assignment:

Part 12: PCIE Interface

There is a PCIE x1 slot on the AXU2CGA/B board for connecting PCIE peripherals, and the PCIE communication speed is up to 5Gbps. PCIE signal is directly connected to LANE0 of BANK505 PS MGT transceiver. The schematic diagram of PCIE x 1 design is shown in Figure 12-1:

PCIE Interface ZYNQ Pin Assignment

Part 13: 40-Pin Expansion Header

The AXU2CGA/B board is reserved with two 0.1-inch standard pitch 40-pin expansion ports J12 and J15, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channel ground, and 34 IOs. Do not directly connect the IO directly to the 5V device to avoid burning the FPGA. If you want to connect 5V equipment, you need to connect the level conversion chip.
The IO port of the J15 expansion port is connected to the ZYNQ chip BANK25 and BANK26, and the level standard is 3.3V. The schematic diagram of the design is shown in Figure 13-1:

J12 Expansion Header ZYNQ Pin Assignment

J15 Expansion Header ZYNQ Pin Assignment

Part 14: MIPI Camera Interface

There are 2 MIPI interfaces on the AXU2CGA/B board for connecting MIPI cameras. The differential signal of MIPI is connected to the HP IO of BANK64 and 65, and the level standard is +1.2V; the control signal of MIPI is connected to BANK24, and the level standard is +3.3V. The schematic diagram of the MIPI port design is shown in Figure 14-1:

MIPI Interface J23 Pin Assignment

PIN| Signal Name| ZYNQ Pin Name| ZYNQ Pin Number| Description
---|---|---|---|---
1| GND| –| –| Ground
2| MIPI1_LAN0_N| IO_L2N_64| AE8| MIPI Data 0 Signal N
3| MIPI1_LAN0_P| IO_L2P_64| AE9| MIPI Data 0 Signal P
4| GND| –| –| Ground
---|---|---|---|---
5| MIPI1_LAN1_N| IO_L3N_64| AC8| MIPI Data 1 Signal N
6| MIPI1_LAN1_P| IO_L3P_64| AB8| MIPI Data 1 Signal P
7| GND| –| –| Ground
8| MIPI1_CLK_N| IO_L1N_64| AD9| MIPI Clock Signal N
9| MIPI1_CLK_P| IO_L1P_64| AC9| MIPI Clock Signal P
10| GND| –| –| Ground
11| CAM1_GPIO| IO_L2N_24| AH14| Control Signal IO
12| CAM1_CLK| IO_L3P_24| AG13| Control Signal Clock
13| CAM1_SCL| IO_L3N_24| AH13| Control Signal SCL
14| CAM1_SDA| IO_L4P_24| AE13| Control Signal SDA
15| VCC_3V3| –| –| 3.3V Power Supply

MIPI Interface J24 Pin Assignment

PIN| Signal Name| ZYNQ Pin Name| ZYNQ Pin Number| Description
---|---|---|---|---
1| GND| –| –| Ground
2| MIPI2_LAN0_N| IO_L2N_65| V9| MIPI Data 0 Signal N
3| MIPI2_LAN0_P| IO_L2P_65| U9| MIPI Data 0 Signal P
4| GND| –| –| Ground
5| MIPI2_LAN1_N| IO_L3N_65| V8| MIPI Data 1 Signal N
6| MIPI2_LAN1_P| IO_L3P_65| U8| MIPI Data 1 Signal P
7| GND| –| –| Ground
8| MIPI2_CLK_N| IO_L1N_65| Y8| MIPI Clock Signal N
9| MIPI2_CLK_P| IO_L1P_65| W8| MIPI Clock Signal P
10| GND| –| –| Ground
11| CAM2_GPIO| IO_L5P_24| AD15| Control Signal IO
12| CAM2_CLK| IO_L6P_24| AC14| Control Signal Clock
13| CAM2_SCL| IO_L5N_24| AD14| Control Signal SCL
14| CAM2_SDA| IO_L6N_24| AC13| Control Signal SDA
15| VCC_3V3| –| –| 3.3V Power Supply

Part 15: JTAG Debug Port

The 10-pin JTAG interface is reserved on the AXU2CGA/B board for downloading ZYNQ UltraScale+ programs or firmware programs to FLASH. The pin definition of JTAG is shown in the figure below

Part 16: DIP Switch Configuration

There is a 4-digit DIP switch SW1 on the FPGA development board to configure the startup mode of the ZYNQ system. The AXU2CGA/B system development platform supports 4 startup modes. The 4 startup modes are JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode. After the ZU3EG chip is powered on, it will detect the level of (PS_MODE0~3) to determine the startup mode. The user can select different startup modes through the DIP switch SW1 on the expansion board. The SW1 startup mode configuration is shown in the following table 16-1 .

Table 16-1: SW1 startup mode configuration

Part 17: LEDs

There are 4 user indicator lights, 4 user control KEYs, and a reset KET on the AXU2CGA/B board. 4 user indicators and 4 user KEYs are all connected to the IO of BANK24. The schematic diagram of the LED light hardware connection is shown in Figure 17-1:

LED and Key Pin Assignment:

Part 18: System Clock

The board provides reference clocks for the RTC circuit, PS system, and PL logic parts. The RTC clock is 32.768, the PS system clock is 33.3333Mhz, and the PL end clock is 25Mhz. The schematic diagram of the clock circuit design is shown in Figure 18-1:

Clock Pin Assignment

The level of PL_REF_CLK is +1.8V.

Part 19: ALINX Customized Fan Interface

The fan is powered by 12V, and the speed can be adjusted through the FAN_PWM signal. This board will come with a heatsink in fault, if you need this fan, purchase it separately.

Part 20: Power Input

The power input of AXU2CGA/B is an adapter with DC12V and current 2A. The power interface is shown in the figure below

Part 21: Board Size Dimension

References

• ALINX 芯驿电子科技（上海）有限公司

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