ALINX AN5642 Dual Lens Camera Module User Manual

ALINX AN5642 Dual Lens Camera Module

Dual Lens Cameral Module General Description

The dual-lens camera module AN5642, uses 2 pieces of CMOS chip image sensor OV5640 from OmniVision Corporation of the United States, which supports two independent or simultaneous display functions. The CMOS OV5640 chip supports DVP and MIPI interfaces. On the OV5642 module, images are transmitted through the DVP interface and the FPGA connection. Figure 1-1 details the AN5642 module product photo.

AN5642 Dual Lens Module Detail Parameter

• AN5642 dual-lens camera module detail parameters are listed below:
• Module Interface: 40-pin 0.1 spacing female header, 2-way camera with separate DVP interface
• Spacing： The distance between the 2-way cameras is 40mm
• support for images sizes: 5 megapixel
• Photosensitive chip: 2 pieces of OV5640 optical size of 1/4″
• Module content: OV5640 power supply circuit and clock
• automatic image control functions: Manual focus, automatic exposure control (AEC), automatic white balance (AWB)
• support for output formats: RAW RGB, RGB565/555/444, CCIR656, YUV422/420, YCbCr422, and compression
• maximum image transfer rate:
• QSXGA (2592×1944): 15 fps 1080 30 fps
• 1280×960: 45 fps
• 720p: 60 fps
• VGA (640×480): 90 fps
• QVGA (320×240): 120 fps
• Working temperature: -30~70°C, stable working temperature is 0~50°C

Chip OV5640 power-on requirements

• t0: >=0ms. Delay from DOVDD stable to AVDD stable
• t2: >=5ms. Delay from AVDD stable to sensor power up stable
• t3: >=1ms. Delay from sensor power up stable to Reset# pull high
• t4: >=20ms. Delay from Reset pull high to SCCB initialization

The power-on steps of the chip OV5640 are as follows:

• Step 1: ResetB is pulled low, reset AN5640, and PWDN is pulled high
• Step 2: Both DOVDD and AVDD are powered up simultaneously, which is implemented in the power supply design of the module.
• Step 3: After 5ms of AVDD reaching stable, pull PWDN to low.
• Step 4: After 1ms of PWDN goes low, pull high ResetB
• Step 5: After 20ms, initialize OV5640 by SCCB initialization:

Register Configuration of CMOS Chip OV5640

The register configuration of the OV5640 is configured through the I2C interface of the FPGA (or other CPU). The user needs to configure the correct register value to let the OV5640 output the image format we need. In our example, we configure the OV5640 as the image format of the 720P (1280×720) video output image and the RGB565 frame rate of 30fps. To facilitate debugging, the user can configure registers to enable internal test images of the OV5640, such as color bars and color squares.

Color bar

• write_i2c(0x503d, 0x80);
• write_i2c(0x4741, 0x00);

Color square

• write_i2c(0x503d, 0x82);
• write_i2c(0x4741, 0x0);

The data format of the OV5640’s camera output is configured in the following 0x4300 registers. In our example, the OV5640 is configured as an RGB565 output format.

There are many more registers on the OV5640, but many register users do not need to understand, the configuration of the registers can be configured according to the OV5640 application guide. If you want to know more about the register information, you can refer to the register description in the OV5640 datasheet.

Hardware Connection

The following ALINX AX516 development board is an example to introduce the hardware connection of the dual lens camera module AN5642 and ALINX serial FPGA development kit. The 40-pin female headers of module plug into the expansion board of FPGA development kit. Figure 2-1 detailed the 40-pin female headers of module.

The 40-pin female header of camera module detailed as below:

CMOSx_D0~D9 is the video image captured by the camera OV5640. If the input selects the RGB format, only the upper 8 bits D2~D9 are needed. CMOSx_PCLK is the pixel clock signal, and the rising edge of the clock collects data. CMOSx_HREF is a line valid signal. When the signal is high, one line of data is valid. CMOSx_VSYNC is a column sync signal. When configured in VGA mode (640*480), the timing of the CMOS camera output is shown below:

The connection between the camera module and the development board is relatively simple. Just plug the camera module directly into the expansion port of the development board. When inserting, you need to pay attention to the alignment of the PIN1 pin. Figure 2-3 is a schematic diagram of the connection between the AN5642 module and the AX516 development board (if the AX515 or AX530 development board needs to be plugged into the J3 port ).

inocular switching display experiment

In this experiment, the image of the 2-way camera is displayed on the VGA display, and the 2-way video image is switched by the button KEY1 on the development board. The size of each video image displayed on the VGA display is 720P.

Programming

The logic block diagram of the FPGA program design is shown in Figure 3-1 below:

After power-on, the FPGA program first configures the binocular camera register through the I2C bus, and configures the OV5640 camera to work in 720P 30-frame video output. After the data output by the 2-way camera is sent to the FPGA, the camera signal selection module is used to select one of the videos to enter the camera data acquisition module. The camera data acquisition module converts the video image into 32-bit or 64-bit wide data and stores it in the write FIFO. When the data in the write FIFO reaches a certain amount, a burst write signal is generated to the DDR read/write control module, and the DDR read/write control module will write a certain length of data from the write FIFO and writes it to the DDR chip. If the data in the read FIFO is less than a certain amount, a burst read signal will be generated to the DDR read/write control module, and the DDR read/write control module will read a certain length of data from the DDR into the read FIFO. The VGA display module reads the data in the read FIFO and displays the video image onto the VGA display. The completed engineering architecture is shown in the figure below (Take AX516 as an example):

The function description of each module is detailed as below:

1. Power-on waiting program： power_on_delay.v Because the OV5640 chip has power-on timing requirements, this program
2. OV5640 register configuration module： reg_config.v After power-on the FPGA, the register configuration program of the OV5640 calls the I2C communication program to set the parameters of the registers of the two OV5640 chips. Here the output of the image by the two OV5640 chips are set to RGB565 format, and the number of images is 1280*720.
3. Camera Signal Selection Module： cmos_select.v The program detects the button Key1, and if the button KEY1 is pressed once, it switches to the signal of the other camera. The default is to select to capture CMOS1 video images.
4. Camera Image Acquisition Module： COMS_Capture.v The camera image acquisition program converts the 8-bit image from the OV5640 module into a 32-bit or 64-bit data width and produces a FIFO write signal. Because the camera RGB565 format output, an image requires 16 bits of data, it needs to be divided into two 8-bit output, which occupies 2 clocks. So if it is a 720P image, a row of data needs to have 1280 * 2 PCLK clocks.
5. FIFO Control Program Module: dcfifo_ctrl.vWhen storing the captured video image in the DDR or reading the video image from the DDR to the VGA display module, the data needs to be cached. So we initialized two FIFOs in the Dcfifo_ctrl.v module, a data write FIFO to buffer the data collected from the camera, and a data read FIFO to store the data read from the DDR. In this experiment, the data written to the DDR is first stored in the write FIFO, and the data read from the DDR is first stored in the read FIFO.
   • A DDR burst write request is generated when the amount of data in the write FIFO is greater than the set write burst length (128)
   • The Sdram read request is generated when the amount of data in the read FIFO is less than the set read burst length (128).
6. DDR Read and Write Control Module: mem_ctrl.v The function of the mem_burst_v2 program is to convert the external burst read request and write request into the required signals and timing of the Local Bus of the DDR IP interface. This makes the user not need to care about the complex timing of the DDR interface, making it easy and convenient to read and write DDR. The mem_burst_v2 module completes the control of DDR with the DDR IP generated by XILINX/Altera software. The port signal of the circle in figure 3-6 below is the signal of the user terminal. By controlling these signals, the data of DDR can be read and written.
   • Through the DDR read and write control module, DDR read and write operations become very simple. For example, when performing a Burst read on DDR, set a read request (rd_burst_req is high), and set the read burst length rd_burst_len and the read address rd_burst_addr. Waiting for the rd_burst_data_valid signal to be high indicates that the data is valid, reading the data, and after reading the burst length data, the rd_burst_finish signal goes high.
7. DDR Controller Module： ddr3_top.v The DDR controller module and its submodules are generated by the IP provided by Xilinx or Altera. For details on how to generate the DDR controller, please refer to the corresponding development board (DDR read and write routines).
8. VGA Display Program: vga_disp.v The vga_disp.v module implements the image display of a VGA display and generates line synchronization, column synchronization, and timing of image data signals according to the VGA timing standard. VGA clock frequency: Take 1280×768@79.5MHz (60Hz) as an example. Each field corresponds to 798 line periods, of which 1280 is the display line. Each display line includes 1664 points of the clock, of which 1280 points are valid display areas. It can be seen that the clock frequency of VGA is required: 166479860 is about 79.5MHz. Figure 3-7 and figured 3-8 detailed the timing diagram of VGA:
   • In addition, because the video image output by OV5640 is 1280×720 image size, but the VGA display is 1280×768 image, in order to make the video image in the middle of the VGA display, the image is not displayed in the first 24 lines and the last 24 lines of the VGA image. (Default is black):
9. ddr Bank Exchange Progrm: bank_switch.v Bank exchange program realizes ddr read and ddr write respectively operate in different Bank operations. For example, when Bank0 writes the image captured by the camera, VGA reads the data display of Bank3; After Bank0 writes a video image, it switches to DDR to write the next frame image. Bank1 writes the next frame of an image. After one frame of VGA is displayed, the display of the next frame will be read from bank0 of DDR. This is displayed and stored in different BANKs to avoid image distortion.
10. System Control Program: system_ctrl.v The camera’s clock (24 MHz) and VGA’s image clock (79.5Mhz) are generated, and the program also generates a reset signal for the entire system.

OV5642 VGA binocular display experiment

After writing the program, assign the Pin of the FPGA, and after recompilation, we can start the camera VGA display experiment. The development board connects with the camera module OV5642 and VGA interface to connect VGA display, then downloads the sof file to the FPGA, we can see 1280×768 video images on the VGA display. The default VGA display shows the video image of the camera CMOS1. We just press the development board button KEY1, and the VGA display will display the CMOS2 video image. Figure 3-9 and Figure 3-10 detailed the video image effect.

If the captured video image is found to be unclear, the user can rotate the corresponding camera lens to adjust the focus.

OV5642 binocular display simultaneously

In this experiment, the video images of the two cameras are simultaneously displayed on the VGA display, the CMOS1 camera is displayed on the left side of the VGA display, and the CMOS2 camera is displayed on the right side of the VGA display. The resolution of the VGA output is unchanged at 1280768. The resolution of the CMOS1 camera and the CMOS2 camera output are 640480.

Programming

Because there are two cameras for simultaneous input and storage and two camera displays, we need to add another read data FIFO and write data FIFO as the video storage of another camera. In addition, we added multiple port arbitrage programs for DDR read and write in the program (ddr multiple port read arbitration program and ddr multiple port write arbitration program). The logical block diagram of the FPGA program design is shown below:

The completed engineering architecture is shown in the figure below (Take AX516 as an example):

Regarding most of the programs being the same as the previous binocular switching display experiment, we will only explain the multi-port ddr read arbitration module and the multi-port ddr write arbitration module below:

1. Multi-port DDR read arbitration module: mem_read_arbi.v In the program, the four ports of the input are polled in turn., from ch0~ch3, if ch0 has a read request and the read burst length is not 0, then enter the read state of ch0, output the burst read request of ch0; otherwise continue to query ch1, the same if ch1 has a read request and the read burst length is not 0, it enters the read state of ch1, outputs a burst read request of ch1, and sequentially queries to ch3. Because the read request for each port ch0~ch3 will remain valid until the request is answered, there will be no read requests being lost.
2. Multi-port ddr write arbitration module: mem_write_arbi.v The principle of the multi-port ddr write arbitration module is the same as that of the multi-port read arbitration module, and it is also a method of polling in turn.

OV5642 binocular display simultaneously

Experiment
After writing the program, assign the Pin of the FPGA, and after recompilation, we can start the OV5642 binocular display simultaneously experiment. The development board connects with the camera module OV5642 and the VGA port to connect the VGA monitor, and then downloads the sof file to the FPGA. We can see the video images displayed by the two cameras simultaneously on the VGA monitor. Figure 4-3 detailed the OV5642 video image binocular display effect.

Users can also modify the program by themselves, so that the two cameras display different video image sizes, such as CMOS1 display 1280720, CMOS2 display 640480, and then display the picture-in-picture effect on the VGA display (Refer to Figure 4-1). Here will not introduce about how to achieve. That reserved for everyone to study and learn.

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References

• ALINX 芯驿电子科技（上海）有限公司

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