Philips NXP NE555 Semiconductors Datasheet (HTML)
- June 12, 2024
- NXP
Table of Contents
Philips NXP NE555 Semiconductors Datasheet (HTML)
DESCRIPTION
The 555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free-running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200mA.
FEATURES
- Turn-off time less than 2µs
- Max. operating frequency greater than 500kHz
- Timing from microseconds to hours
- Operates in both astable and monostable modes
- High output current
- Adjustable duty cycle
- TTL compatible
- Temperature stability of 0.005% per °C
PIN CONFIGURATIONS
APPLICATIONS
- Precision timing
- Pulse generation
- Sequential timing
- Time delay generation
- Pulse width modulation
ORDERING INFORMATION
DESCRIPTION | TEMPERATURE RANGE | ORDER CODE | DWG # |
---|---|---|---|
8-Pin Plastic Small Outline (SO) Package | 0 to +70°C | NE555D | 0174C |
8-Pin Plastic Dual In-Line Package (DIP) | 0 to +70°C | NE555N | 0404B |
8-Pin Plastic Dual In-Line Package (DIP) | -40°C to +85°C | SA555N | 0404B |
8-Pin Plastic Small Outline (SO) Package | -40°C to +85°C | SA555D | 0174C |
8-Pin Hermetic Ceramic Dual In-Line Package (CERDIP) | -55°C to +125°C | ||
SE555CFE | |||
8-Pin Plastic Dual In-Line Package (DIP) | -55°C to +125°C | SE555CN | 0404B |
14-Pin Plastic Dual In-Line Package (DIP) | -55°C to +125°C | SE555N | 0405B |
8-Pin Hermetic Cerdip | -55°C to +125°C | SE555FE | |
14-Pin Ceramic Dual In-Line Package (CERDIP) | 0 to +70°C | NE555F | 0581B |
14-Pin Ceramic Dual In-Line Package (CERDIP) | -55°C to +125°C | SE555F | 0581B |
14-Pin Ceramic Dual In-Line Package (CERDIP) | -55°C to +125°C | SE555CF | 0581B |
BLOCK DIAGRAM
EQUIVALENT SCHEMATIC
NOTE: Pin numbers are for 8-Pin package
ABSOLUTE MAXIMUM RATINGS
SYMBOL | PARAMETER | RATING | UNIT |
---|
VCC
| Supply voltage SE555
NE555, SE555C, SA555
| ****
+18
+16
| ****
V V
PD| Maximum allowable power dissipation1| 600| mW
TA| Operating ambient temperature range NE555
SA555
SE555, SE555C
| ****
0 to +70
-40 to +85
-55 to +125
| ****
°C
°C
°C
TSTG| Storage temperature range| -65 to +150| °C
TSOLD| Lead soldering temperature (10sec max)| +300| °C
NOTES:
- The junction temperature must be kept below 125°C for the D package and below 150°C for the FE, N, and F packages. At ambient temperatures above 25°C, where this limit would be derated by the following factors:
- D package 160°C/W
- FE package 150°C/W
- N package 100°C/W
- F package 105°C/W
DC AND AC ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = +5V to +15 unless otherwise specified.
NOTES:
- Supply current when output is high typically 1mA less.
- Tested at VCC=5V and VCC=15V.
- This will determine the max value of RA+RB, for 15V operation, the max total R=10MΩ, and for 5V operation, the max. total R=3.4MΩ.
- Specified with trigger input high.
- Time measured from a positive going input pulse from 0 to 0.8×VCC into the threshold to the drop from high to low of the output. The trigger is tied to the threshold.
TYPICAL PERFORMANCE CHARACTERISTICS
SYMBOL| PARAMETER| TEST CONDITIONS| SE555|
NE555/SE555C| UNIT
---|---|---|---|---|---
Min| Typ| Max| Min| Typ| Max
VCC| Supply voltage| | 4.5| | 18| 4.5| | 16| V
ICC| Supply current (low
state)1
| VCC=5V, RL=¥
VCC=15V, RL=¥
| | 3
10
| 5
12
| | 3
10
| 6
15
| mA
mA
tM
DtM/DT
DtM/DVS
| Timing error (monostable) Initial accuracy2
Drift with temperature
Drift with supply voltage
| RA=2kW to 100kW C=0.1mF| |
0.5
30
0.05
|
2.0
100
0.2
| |
1.0
50
0.1
|
3.0
150
0.5
|
%
ppm/°C
%/V
tA
DtA/DT
DtA/DVS
| Timing error (astable) Initial accuracy2
Drift with temperature
Drift with supply voltage
| RA, RB=1kW to 100kW C=0.1mF VCC=15V| |
4
0.15
|
6
500
0.6
| |
5
0.3
|
13
500
1
|
%
ppm/°C
%/V
VC| Control voltage level| VCC=15V
VCC=5V
| 9.6
2.9
| 10.0
3.33
| 10.4
3.8
| 9.0
2.6
| 10.0
3.33
| 11.0
4.0
| V
V
VTH
|
Threshold voltage
| VCC=15V
VCC=5V
| 9.4
2.7
| 10.0
3.33
| 10.6
4.0
| 8.8
2.4
| 10.0
3.33
| 11.2
4.2
| V
V
ITH| Threshold current3| | | 0.1| 0.25| | 0.1| 0.25| mA
VTRIG| Trigger voltage| VCC=15V
VCC=5V
| 4.8
1.45
| 5.0
1.67
| 5.2
1.9
| 4.5
1.1
| 5.0
1.67
| 5.6
2.2
| V
V
ITRIG| Trigger current| VTRIG=0V| | 0.5| 0.9| | 0.5| 2.0| mA
VRESET| Reset voltage4| VCC=15V, VTH =10.5V| 0.3| | 1.0| 0.3| | 1.0| V
IRESET| Reset current
Reset current
| VRESET=0.4V
VRESET=0V
| | 0.1
0.4
| 0.4
1.0
| | 0.1
0.4
| 0.4
1.5
| mA
mA
| | VCC=15V| | | | | | |
| | ISINK=10mA| 0.1| 0.15| 0.1| 0.25| V
| | ISINK=50mA| 0.4| 0.5| 0.4| 0.75| V
VOL| Output voltage (low)| ISINK=100mA| 2.0| 2.2| 2.0| 2.5| V
| | ISINK=200mA| 2.5| | 2.5| | V
| | VCC=5V| | | | |
| | ISINK=8mA| 0.1| 0.25| 0.3| 0.4| V
| | ISINK=5mA| 0.05| 0.2| 0.25| 0.35| V
VOH
|
Output voltage (high)
| VCC=15V ISOURCE=200mA ISOURCE=100mA VCC=5V
ISOURCE=100mA
|
13.0
3.0
|
12.5
13.3
3.3
| |
12.75
2.75
|
12.5
13.3
3.3
| |
V V
V
tOFF| Turn-off time5| VRESET=VCC| | 0.5| 2.0| | 0.5| 2.0| ms
tR| Rise time of output| | | 100| 200| | 100| 300| ns
tF| Fall time of output| | | 100| 200| | 100| 300| ns
| Discharge leakage current| | | 20| 100| | 20| 100| nA
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Trigger Pulse Width Requirements and Time Delays
Due to the nature of the trigger circuitry, the timer will trigger on the
negative going edge of the input pulse. For the device to time out properly,
it is necessary that the trigger voltage level be returned to some voltage
greater than one-third of the supply before the time-out period. This can be
achieved by making either the trigger pulse sufficiently short or by AC
coupling into the trigger. By AC coupling the trigger, see Figure 1, a short
negative going pulse is achieved when the trigger signal goes to the ground.
AC coupling is most frequently used in conjunction with a switch or a signal
that goes to the ground which initiates the timing cycle. Should the trigger
be held low, without AC coupling, for a longer duration than the timing cycle
the output will remain in a high state for the duration of the low trigger
signal, without regard to the threshold comparator state. This
is due to the predominance of Q15 on the base of Q16, controlling the state of
the bi-stable flip-flop. When the trigger signal then returns to a high level,
the output will fall immediately. Thus, the output signal will follow the
trigger signal in this case.
Another consideration is the “turn-off time”. This is the measurement of the amount of time required after the threshold reaches 2/3 VCC to turn the output low. To explain further, Q1 at the threshold input turns on after reaching 2/3 VCC, which then turns on Q5, which turns on Q6. Current from Q6 turns on Q16 which turns Q17 off. This allows the current from Q19 to turn on Q20 and Q24 to give an output low. These steps cause the 2µs max. delay as stated in the datasheet. Also, a delay comparable to the turn-off time is the trigger release time. When the trigger is low, Q10 is on and turns on Q11 which turns on Q15. Q15 turns off Q16 and allows Q17 to turn on. This turns off the current to Q20 and Q24, which results in output high. When the trigger is released, Q10 and Q11 shut off, Q15 turns off, Q16 turns on and the circuit then follows the same path and time delay explained as “turn off time”. This trigger release time is very important in designing the trigger pulse width so as not to interfere with the output signal as explained previously.
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