Microsemi UG0939 White Balance IP User Guide
- June 10, 2024
- Microsemi
Table of Contents
Microsemi UG0939 White Balance IP
Product Information – White Balance IP
The White Balance IP is a product developed by Microsemi for adjusting the colors of an image or video to make it look more natural. It is a configurable IP core that can be integrated into various FPGA-based systems. The key features of this product are:
- Configurable color adjustment parameters
- Supports various families of FPGAs
- Compatible with different input and output formats
To use this product, you need to configure the following parameters:
- White point
- Black point
- Color gain
- Color offset
Usage Instructions
To use the White Balance IP, follow these steps:
- Configure the white balance parameters according to your requirements.
- Connect the input video source to the input port of the IP core.
- Connect the output port of the IP core to the display or storage device.
- Start the FPGA system.
The IP core will adjust the colors of the input video according to the configured white balance parameters and provide the output on the connected device.
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Revision History
The revision history describes the changes that were implemented in the
document. The changes are listed by revision, starting with the most current
publication.
Revision 1.0
The first publication of this document.
Introduction
White balance is the process of adjusting the color temperature so that the
white objects which appear white in person are rendered as white. A scene can
be lit by a light source of any temperature. A human eye adjusts to various
color temperatures and detects white as white, where as a camera captures the
light as it seen by the sensor.
As the color temperature rises, the color distribution becomes cooler. This
may not seem intuitive but results from the fact that shorter wavelengths
contain the light of higher energy. Such as 5000 K produces roughly neutral
light, whereas 3000 K and 9000 K produce light spectrums, which shift to
contain more orange and blue wavelengths, respectively. The temperature of
commonly available light sources is described in the table below.
The white balance IP allows to set the temperature manually from user input to
achieve white balance. The IP supports a temperature range of 1000 to 26500
Kelvin.
This section describes the inputs and outputs and configuration parameters of
the Image Scaler IP.
Key Features
- Supports temperature range of 1000-26500 Kelvin.
- LUT based white balance
- Supports 8,10,12,14, and 16 data width
Supported Families
- PolarFire® SoC
- PolarFire®
- RTG4™
- IGLOO®2
- SmartFusion®2
Inputs and Outputs
Figure 1 • Inputs and Outputs The following table lists the input and
output ports of the White Balance IP.
Table 2 • Input and Output Ports
Configuration Parameters
The following table lists the configuration parameters used in the hardware
implementation of the White balance. These parameters are generic and can be
varied based on the application requirement.
Testbench
A testbench is provided to check the functionality of the White balance IP. To ensure that the testbench works correctly, the configuration parameters listed in Table 4 must be configured at the beginning of the testbench file.
License
White balance IP clear RTL is license locked and the obfuscated RTL available
for free.
Obfuscated
Complete RTL code is provided for the core, allowing the core to be
instantiated with the SmartDesign tool. Simulation, synthesis, and layout can
be performed within Libero® System-on-Chip (SoC). The RTL code for the core is
obfuscated.
RTL
Complete RTL source code is provided for the core.
The following steps describe how to simulate the core using the testbench. The
packaged testbench will correct the white balance of an input image.
-
In the Design Flow window, expand Create Design. Right-click Create SmartDesign testbench and click Run, as shown in the following figure.
Figure 2 • Design Flow SmartDesign testbench is created, and a canvas appears to the right of the Design Flow pane. -
In the Libero SoC Catalog (View > Windows > Catalog), expand Solutions-Video, and drag the White balance IP core onto the SmartDesign testbench canvas. Figure 3 • Libero SoC Catalog
-
Select the default component name and click OK.
-
In the White balance Configurator GUI window, update the G_DATA_WIDTH and click OK.
Figure 4 • Configurator -
On the Design Hierarchy tab, right-click White_Balance_C0 and click Set As Root.
-
Select all the ports on the White_Balance_C0 instance, right-click, and select Promote to Top Level, as shown in the following figure.
Figure 5 • White_Balance_C0 Instance
Figure 6 • SmartDesign Toolbar -
Click Generate Component from the SmartDesign toolbar.
-
Go to the Files tab and select simulation > Import Files…, as shown in the following figure.
Figure 7 • Import Files -
Import the Input Image file “CFA_RGB_in.txt” from the following path:
..\\component\Microsemi\SolutionCore\White_Balance\1.0.0\Stimulus. To import a different file, browse the folder that contains the required file, and click Open. The imported file is listed under simulation, as shown in the following figure
Figure 8 • Simulation
-
On the Stimulus Hierarchy tab, right-click white_balance_test testbench file and click Open Interactively from Simulate Pre-Synth Design.
Figure 9 • Stimulus Hierarchy
The ModelSim tool appears with the test bench
file loaded onto it, as shown in the following figure.
If the
simulation is interrupted because of the runtime limit in the DO file, use the
run -all command to complete the simulation. By default, the output image file
is placed in the Files/simulation directory and uses the CFA_RGB_out.txt.
Simulation Results
Timing Diagram
The following is the timing diagram for White Balance IP showing video data
and output image.
Input Image
Output Image
Resource Utilization
White Balance is implemented on PolarFire FPGA (MPF500T -1FCG1152I package).
The following table shows the resource utilization report after synthesis.
Note: G_DATA_WIDTH = 8