Microsemi UG0856 PolarFire FPGA Video Kit User Guide
- June 9, 2024
- Microsemi
Table of Contents
Microsemi UG0856 PolarFire FPGA Video Kit
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Revision History
Revision 2.0
Added a footnote in FMC HPC Connector (J14).
Revision 1.0
The first publication of this document.
Getting Started
The Microchip PolarFire® FPGA Video Kit (POLARFIRE VIDEO KIT), which is RoHS- compliant, enables you to evaluate the PolarFire MPF300TS-1FCG1152I FPGA for the following interfaces:
- MIPI CSI-2 RX interface
- HDMI2.0
- HDMI1.4
- DDR4 memory
- FMC HPC with 8 Transceiver lanes
- UART Interface to the FTDI device
- SPI Interface to the SPI Flash device
Kit Contents
The following table lists the contents of the PolarFire Video Kit.
Block Diagram
The following figure shows the block diagram of the video kit.
Board Overview
The following figure shows a labeled image of the video board highlighting its
components.
Board Callout
The
following table lists the components of the video board.
Board Components
**Hardware Settings
**
This section provides information about jumper settings, switches, LEDs, and DIP switches on the PolarFire video board.
Jumper Settings
Connect the jumpers according to the settings specified in the following
table. 
LEDs
The following table lists the power supply LEDs.
Power Sources
The PolarFire video board uses Microchip power supply devices. For more
information about these power supply devices, see:
https://www.microchip.com/design-centers/power-management/dc-dc-converters-
regulators.
The following table lists the key power supplies required for normal operation
of the PolarFire video board.
The
following figure shows the power supply scheme used in the PolarFire video
board.
Power Supply Scheme
The following table lists the suggested Microchip power regulators for
PolarFire FPGA voltage rails.
Power Regulators1
- These regulators are not pin compatible with the existing video kit schematics. Use these regulators for new board designs.
Board Components and Operations
This section describes the key components of the PolarFire Video board and
important board operations.
Memory Interface
The following figure shows the memory interface scheme.
As
shown in Figure 4, page 9, Four 4 Gb DDR4 SDRAM chips are used as flexible
volatile memory for user applications. The DDR4 interface is implemented in
the HSIO Bank 0 and Bank 7.
The DDR4 SDRAM specifications are as follows:
- MT40A256M16GE-083E:B
- Quantity: Four chips are connected in Fly-by topology
- Density: 16 Gb
- Data rate: DDR4 64-bit at 166 MHz clock rate
The PolarFire video board design uses the DDR4 and POD12 standards for the DDR4 interface. The default board assembly for the DDR4 standard uses RC terminations.
SPI Serial Flash
The following figure shows the SPI Flash and its interface with the PolarFire
device. 
The SPI flash specifications for the PolarFire device are:
- Density: 1 Gb
- Voltage: 2.7 V to 3.6 V (MT25QL01GBBB8ESF-0SIT)
- Frequency: 90 MHz
- Quantity = 1
- SPI mode support: Modes 0 and 3
HDMI1.4 Interface
One HDMI1.4 Transmitter is connected to the PolarFire device to support the
HDMI1.4 standard as shown in the following figure.
The
HDMI interface is implemented in Bank6.
The HDMI1.4 transmitter specifications for the PolarFire device are:
- Part Number of the HDMI Transmitter: ADV7511KSTZ
- Operating frequency: up to 225 MHz
MIPI- RX Connector (CSI-2 Application)
The video board supports a dual Camera image sensor daughter card that can be
connected using the CSI-2 RX interface (J5) for CSI-2 RX applications. The
daughter card includes two IMX334 cameras. Each image sensor supports a four-
lane MIPI interface. The daughter card is connected to the video board via the
board to board connector as shown in Figure 7, page 10. The MIPI output
signals are connected to Bank 2.
The image sensor supports maximum 1782 Mbps.
MIPI-RX Connection
MIPI-TX Connector (DSI Application)
The video board supports the MIPI transmitter X4 lanes and clock for DSI
application, as shown in Figure 8, page 11. MIPI TX signals are interfaced to
the LCD display. An adaptor board for the LCD display can be connected through
the J26 connector on the video board. This adaptor board contains the LCD
mating connector and the auxiliary circuit required for the display. For more
information, see the video board schematics.
MIPI-TX Connection (DSI Application)
MIPI-TX connector (CSI-2 Application)
The video board supports the MIPI X4 lanes and clock for the CSI-2 transmitter
application, . For testing, the video board can be can be interfaced with
Nvidia’s Jetson TX1\TX2 development board using a mating connector cable.
Note: Jetson board is not part of the kit.
MIPI-TX and RX PCB Loopback
The video board supports the on-board PCB trace loopback of MIPI X4 lanes and
clock.
MIPI-TX and RX Loopback
**Transceivers
**
The PolarFire MPF300TS-1FCG1152I device has 4 XCVR blocks and each block
contains 4 transceiver lanes. These lanes can be accessed through the HDMI2.0
and FMC connectors on the board. The following sections describe these blocks
and the lanes used.
XCVR0 Block
Lanes 0, 1, and 2 of the XCVR0 block are looped back.
XCVR0 Interface
XCVR1 and XCVR3 Blocks
XCVR1 and XCVR3 blocks have four lanes each. These lanes are connected to the
FMC HPC connector and the signals are routed on the PCB as follows:
- Lanes 0 to 7 are directly routed to the FMC HPC connector.
- TX pad > trace > via (to bottom layer) > trace > FMC HPC connector pad
- RX pad > trace > via (to Top layer) > trace > PolarFire device pad
The XCVR1 and XCVR3 reference clock is routed directly from the HPC connector
to the PolarFire device.the XCVR1 and XCVR3 and their interfaces.
XCVR2 Block XCVR1 and XCVR3 Interface
The lanes of the XCVR2 block are connected to HDMI2.0 TX and RX chips via the
line drivers chips. This interface can operate up to 6 Gbps.
XCVR2 Interface
XCVR
Reference Clock
the clock sources for XCVR blocks.
- XCVR 1A, 3A reference clocks are sources from FMC HPC connector(J14).
- XCVR 2B reference clock is sourced from the on-board 148.5 MHz oscillator.
- XCVR 2A reference clock is sourced from the on-board HMDI2.0 TX device.
Programming
The PolarFire device is programmed using the on-board FlashPro5 programmer or
through the JTAG Header. For more information about programming, see the video
board schematics.
The following section describes the FTDI and JTAG Header programming schemes
used on the board.
FTDI and JTAG Header Scheme
The PolarFire device can be programmed using the on-board JTAG Header or FTDI.
By default, the FTDI programming mode is enabled. The programming mode can be
changed based on the Jumper settings. For more information.
The following figure shows how the JTAG Header interfaces with the PolarFire
Device.
JTAG Header Interface
Note: By default, the FTDI programming mode is enabled. Remove J28 jumper to
enable programming through JTAG header.
50 MHz Oscillator
A 50 MHz clock oscillator with an accuracy of +/-50 ppm is available on the
board. This clock oscillator is connected to the FPGA fabric to provide a
system reference clock. An on-chip PolarFire PLL can be configured to generate
a wide range of high-precision clock frequencies.
The package and pin details of the 50 MHz oscillator are as follows:
- Pin Number: AL26
- Pin Name: HSIO72PB1/CCC_NE_CLKIN_N_11
shows the 50 MHz clock oscillator interface.
Device Reset
As shown in Figure 17, page 16, DEVRST_N (SW5 push button) is an input-only
reset switch that allows assertion of a full reset of the chip at any time.
The DEVRST_N signal is an active-low signal.
User Reset
As shown in Figure 18, page 16, the user reset (SW3 push button) is an input-
only reset switch that allows assertion of a reset of the fabric logic. User
Interface
LEDs and push-button switches are available on the board for the user
interface.
User LEDs
Four active-high LEDs are connected to the PolarFire device. Table 7, page 17
lists the on-board label of these switches, the associated PolarFire pin
number, name, and Bank.
User LED Interface
Push-Button Switches
Two push-button tactile switches are connected to the PolarFire device.
Table 8, page 17 lists the on-board label of these switches, the associated
PolarFire pin number, name, and Bank.
Push-Button Interface
Slide Switches (DPDT)
The SW4 slide switch powers the device ON or OFF.
DIP Switches (SPST)
The SW6 DIP switch includes 8 connections to the PolarFire device. Table 9,
page 18 lists on-board label of these switches, the associated PolarFire pin
number, name, and Bank.
shows
how the DIP switch interfaces with the PolarFire device.
DIP Switch Interface
FMC
HPC Connector (J14)
An HPC (J14) FMC connector is available for future expansion of interfaces.
This FMC is partially populated LPC connector1. The PolarFire Bank4, XCVR1,
and XCVR3 signals are routed to the FMC connector (J14) for user application
development. For more information, see the video board schematics.
Board Components Placement
Figure 22, page 19 shows the top view of the placement of board components.
Silkscreen Top View
- On the FMC, CLK1_M2C_P and CLK1_M2C_N pins are No Connect (NC). While selecting the LPC base FMC card to connect with MPF300-VIDEO-KIT, ensure that the CLK1_M2C_P and CLK1_M2C_N pins are not driven or used from the FMC module.
Silkscreen Bottom View
Documents / Resources
|
Microsemi UG0856 PolarFire FPGA Video
Kit
[pdf] User Guide
UG0856 PolarFire FPGA Video Kit, UG0856, PolarFire FPGA Video Kit, FPGA Video
Kit, Video Kit
---|---
References
- Microsemi | Semiconductor & System Solutions | Power Matters
- microsemi.com/index.php?option=com_docman&task=doc_download&gid=1244033
- DC-DC Converters and Voltage Regulators | Microchip Technology
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