TOSHIBA TLP5214A Smart Gate Driver Coupler Inverter Applications User Guide

TOSHIBA TLP5214A Smart Gate Driver Coupler Inverter Applications

Introduction

Operational stability and reliability are key characteristics of FA devices such as AC servos and general-purpose inverters, as well as inverters used in power conditioners for solar and wind power systems.
Overcurrent and noise in inverter circuits may cause a system malfunction with the potential for equipment damage. The typical ways to protect the IGBT and power MOSFET are: (a) current monitoring with a current transformer (CT); (b) current monitoring with a current sensing resistor; and (c) IGBT saturation voltage monitoring. While each of these has its advantages and disadvantages, approach (c) is the lowest cost solution and has the fastest operating speed and lowest power loss.
The TLP5214A has a built-in IGBT non-saturation (VCE(SAT)) detector suitable for IGBT saturation monitoring as per approach (c), active mirror clamping and fault signal feedback. These functions provide superior performance and stability (compared to existing products) particularly with respect to instantaneous pulse noise during switching and non-saturation. The TLP5214A also helps to minimize design effort in peripheral circuit design, reduction outside components, and reduce PCB area. Thus the device suits for a driver coupler for middle power IGBT and power MOSFET direct drive devices. In addition the device guarantees minimum isolation voltage of 5,000Vrms, so it is equally suitable for many types of industrial machinery and equipment.
This Design Guide is based on a typical application involving an inverter circuit featuring the TLP5214A. TLP5214A product information including performance characteristics is provided on the datasheet and in the application note.
For detail of the TLP5214A →

Target applications

• IGBT/power MOSFET gate drive for FA devices, general-purpose inverters and controllers for AC motors and brushless DC motors

Typical inverter application

Note: Optically coupled isolation amplifier TLP7820 is used for motor phase current detection

Application circuit examples and bill of materials

 Inverter circuits

Figures 2.1 and 2.2 show examples of inverter circuits for the TLP5214A. The Design Guide (this document) gives two circuit designs, one is with mirror clamping and no negative supply, and the other is with negative supply but no mirror clamping. Table 2.1 shows the two designs.

Table 2.2 shows the relevant output specifications.

Due to affection between output drive frequency and the length of the cable, adjust and check the frequency with final product.

(a) Block diagram for inverter circuit 1

(b) U-Phase diagram for inverter circuit 1

(c) V-phase diagram for inverter circuit 1

(d) W-phase diagram for inverter circuit 1

(e) MCU elements in inverter circuit 1

Inverter circuit 1 using TLP5214A (RD021-SCEMATIC1-01)

(a) Block diagram for inverter circuit 2

(b) U-phase diagram for inverter circuit 2

(c) V-phase diagram for inverter circuit 2

(d) W-phase diagram for inverter circuit 2

(e) MCU elements in inverter circuit 2

 Bill of materials

Tables 2.3 and 2.4 are the bill of materials of the TLP5214A inverter circuits shown in Figures 2.1 and 2.2.
Bill of material for TLP5214A inverter circuit 1 (RD021-SCEMATIC1-01)

No.| Label| Qty| Value| Product code| Manufacturer| Description| Package name| Standard dimensions in mm (inches)
---|---|---|---|---|---|---|---|---
1| IC1,IC2,IC7,IC8,

IC13,IC14

| 6| –| TC7SZ14F| TOSHIBA| Buffer| SMV| 2.9×2.8
2| IC3,IC9,IC15| 3| –| OPA237| Texas

Instruments

| Op Amp| 8SOIC| 6×4.9
3| IC4,IC5,IC10,

IC11,IC16,IC17

| 6| –| TLP5214A| TOSHIBA| Photocoupler| SO16L| 10.3×10.0
4| IC6.IC12,IC18| 3| –| TLP7820| TOSHIBA| Isolation Amplifier| SO8L| 11×5.8
5| IC19| 1| –| MCU| –| MCU| –| –
6| Q1,Q2,Q3,Q4, Q5,Q6| 6| –| GT30J341| TOSHIBA| IGBT| TO-

3P(N)

| 20×15.5

7

| D1,D6,D7,D8, D13,D14,D15, D20,D21| ****

9

| ****

–

| CMF05| TOSHIBA| Diode| M-FLAT| 2.4×4.7

8

| D2,D3,D9,D10, D16,D17| ****

6

| ****

–

| CUZ8V2| TOSHIBA| Zener Diode| USC| 2.5×1.25
9| D4,D5,D11,D12,

D18,D19

| 6| –| CUS05F30| TOSHIBA| Diode| USC| 2.5×1.25

10

| R1,R2,R20,R23, R24,R42,R45, R46,R64| 9| 10kΩ| | | 100 mW ±5%| 1608| 1.6 x 0.8 (0603)

11

| R3,R8,R9,R10, R25,R30,R31, R32,R47,R52, R53,R54| 12| 10kΩ| | | 100 mW ±0.5%| 1608| 1.6 x 0.8 (0603)

12

| R4,R5,R6,R7, R26,R27,R28, R29,R48,R49,

R50,R51

| ****

12

| ****

160Ω

| | | ****

100 mW ±5%

| ****

1608

| ****

1.6 x 0.8 (0603)

13| R11,R12,R33,

R34,R55,R56

| 6| 1kΩ| | | 100 mW ±5%| 1608| 1.6 x 0.8 (0603)

14

| R13,R16,R17, R35,R38,R39, R57,R60,R61| 9| 100Ω| | | 250 mW ±5%| 2012| 2.0 x 1.2 (0805)
15| R14,R15,R36,

R37,R58,R59

| 6| 10Ω| | | 100 mW ±5%| 1608| 1.6 x 0.8

(0603)

16| R18,R19,R40,

R41,R62,R63

| 6| 1kΩ| | | 100 mW ±1%| 1608| 1.6 x 0.8

(0603)

17| R21,R43,R65| 3| 10kΩ| | | 100 mW ±1%| 1608| 1.6 x 0.8

(0603)

18| R22,R44,R66| 3| 20mΩ| WSHP2818 R0200FEB| Vishay| 10 W ±1%| –| 7.1 x 4.6
19| C1,C2,C3,C6,C7, C10,C18,C22, C23,C24,C27, C28,C31,C39, C43,C44,C45, C48,C49,C52,

C60

| 21| 100nF| | | Ceramic, 50 V, ±10%| 1608| 1.6 x 0.8 (0603)
20| C4,C21,C25,

C42,C46,C63

| 6| 1nF| | | Ceramic, 50 V, ±10%| 1608| 1.6 x 0.8

(0603)

21| C5,C8,C26,C29,

C47,C50

| 6| 68pF| | | Ceramic, 50 V, ±10%| 1005| 1.0 x 0.5

(0402)

22| C9,C30,C51| 3| 10μF| | | Ceramic, 25 V, ±10%| 1608| 1.6 x 0.8

(0603)

23

| C11,C12,C14, C15,C32,C33, C35,C36,C53, C54,C56,C57| 12| 1μF| | | Ceramic, 50 V, ±10%| 2012| 2.0 x 1.2 (0805)
24| C13,C34,C55| 3| 10μF| | | Ceramic, 6.3 V, ±10%|  2012| 2.0 x 1.2 (0805)
25| C19,C20,C40,

C41,C61,C62

| 6| 120pF| | | Ceramic, 50 V, ±10%| 1608| 1.6 x 0.8 (0603)

Bill of material for TLP5214A inverter circuit 2 (RD021-SCEMATIC2-01)

No.

| ****

Label

| ****

Qty

| ****

Value

| ****

Product code

| ****

Manufacturer

| ****

Description

| Package name| Standard dimensions in

mm (inches)

---|---|---|---|---|---|---|---|---
1| IC1,IC2,IC7,IC8,

IC13,IC14

| 6| –| TC7SZ14F| TOSHIBA| Buffer| SMV| 2.9×2.8
2| IC3,IC9,IC15| 3| –| OPA237| Texas

Instruments

| Op Amp| 8SOIC| 6×4.9
3| IC4,IC5,IC10,

IC16,IC17

| 6| –| TLP5214A| TOSHIBA| Photocoupler| SO16L| 10.3×10.0
4| IC6,IC12,IC18| 3| –| TLP7820| TOSHIBA| Isolation Amplifier| SO8L| 11×5.8
5| IC19| 1| –| MCU| –| MCU| –| –
6| Q1,Q2,Q3,Q4,

Q5,Q6

| 6| –| GT30J341| TOSHIBA| IGBT| TO-3P(N)| 20×15.5

7

| D1,D6,D7,D8, D13,D14,D15,

D20,D21

| ****

9

| ****

–

| ****

CMF05

| ****

TOSHIBA

| ****

Diode

| ****

M-FLAT

| ****

2.4×4.7

8| D2,D3,D9,D10,

D16,D17

| 6| –| CUZ8V2| TOSHIBA| Zener Diode| USC| 2.5×1.25
9| D4,D5,D11,

D12,D18,D19

| 6| –| CUS05F30| TOSHIBA| Diode| USC| 2.5×1.25

10

| R1,R2,R20,R23, R24,R42,R45,

R46,R64

|

9

|

10kΩ

| | |

100 mW ±5%

|

1608

| 1.6 x 0.8

(0603)

11

| R3,R8,R9,R10, R25,R30,R31, R32,R47,R52,

R53,R54

|

12

|

10kΩ

| | |

100 mW ±0.5%

|

1608

|

1.6 x 0.8

(0603)

12

| R4,R5,R6,R7, R26,R27,R28, R29,R48,R49,

R50,R51

|

12

|

160Ω

| | |

100 mW ±5%

|

1608

|

1.6 x 0.8

(0603)

13| R11,R12,R33,

R34,R55,R56

| 6| 1kΩ| | | 100 mW ±0.5%| 1608| 1.6 x 0.8

(0603)

14

| R13,R16,R17, R35,R38,R39,

R57,R60,R61

|

9

|

100Ω

| | |

250 mW ±5%

|

2012

| 2.0 x 1.2

(0805)

15| R14,R15,R36,

R37,R58,R59

| 6| 10Ω| | | 100 mW ±5%| 1608| 1.6 x 0.8

(0603)

16| R18,R19,R40,

R41,R62,R63

| 6| 1kΩ| | | 100 mW ±1%| 1608| 1.6 x 0.8

(0603)

17| R21,R43,R65| 3| 10kΩ| | | 100 mW ±1%| 1608| 1.6 x 0.8

(0603)

18| R22,R44,R66| 3| 20mΩ| WSHP2818 R0200FEB| Vishay| 10 W ± 1%| –| 7.1 x 4.6

19

| C1,C2,C3,C6, C7,C10,C18, C22,C23,C24, C27,C28,C31, C39,C43,C44, C45,C48,C49, C52,C60|

21

|

100nF

| | |

Ceramic, 50 V, ±10%

|

1608

|

1.6 x 0.8

(0603)

20| C4,C21,C25,

C42,C46,C63

| 6| 1nF| | | Ceramic, 50 V, ±10%| 1608| 1.6 x 0.8

(0603)

21| C5,C8,C26,C29,

C47,C50

| 6| 68pF| | | Ceramic, 50 V,

±10%

| 1005| 1.0 x 0.5

(0402)

22| C9,C30,C51| 3| 10μF| | | Ceramic, 25 V,

±10%

| 1608| 1.6 x 0.8

(0603)

23

| C11,C12,C14, C15,C32,C33, C35,C36,C53, C54,C56,C57|

12

|

1μF

| | |

Ceramic, 50 V, ±10%

|

2012

|

2.0 x 1.2

(0805)

24| C13,C34,C55| 3| 10μF| | | Ceramic, 6.3 V, ±10%| 2012| 2.0 x 1.2

(0805)

For the detail of the TLP5214A →Click Here
For the detail of the TLP7820 →Click Here
For the detail of the GT30J341 →Click Here
For the detail of the CMF05 →Click Here
For the detail of the CUZ8V2 →Click Here
For the detail of the CUS05F30 →Click Here
For the detail of the TC7SZ14F  →Click Here

Inverter circuit design guide

This section explains the key design consideration for an inverter circuit using the TLP5214A.

Blanking time

Blanking time (tBLANK) is the time until overcurrent protection is enabled. The TLP5214A outputs a gate drive current from VOUT in response to input signal, and DESAT is initiated at the same time. For products where the power device takes a long time to turn on, DESAT detects the voltage level and enters shutdown mode while the collector-emitter voltage (VCE) is still decreasing. The tBLANK value can be adjusted the time taken for voltage detection to occur, however it is important not to exceed the IGBT short- circuit withstand capability (IGBT time until failure in the presence of overcurrent).
tBLANK is related to blanking capacitor (CBLANK), DESAT threshold voltage (VDESAT), blanking capacitor charging current (ICHG) and DESAT leading edge blanking time (tDESAT(LEB)) by the following equation:

Where VDESAT and ICHG are constants (standard values are 6.5 V and 240 µA respectively), and tDESAT(LEB) is 1.1μs (Typ.). Regarding Figure 3.1, it has GT30J341 (Discrete IGBT) which has 5μs (tsc) value, tBLANK must be set not exceeding this value. If we use CBLANK = 120 pF, then:

A higher CBLANK value would change the slope of the DESAT terminal voltage, meaning a longer time for overcurrent protection to be enabled shown in Figure 3.2. The CBLANK value should be set to a tBLANK time that is within the short- circuit withstand capability period for the power device without causing overcurrent detection errors. Figure 3.2 shows the relation between tBLANK and CBLANK. Note that in actual circuits, tBLANK is also affected by not only CBLANK but also factors such as the parasitic capacitance of diodes on the DESAT line.

IGBT short-circuit threshold voltage

The DESAT terminals monitor the collector-emitter voltage VCE of the external IGBT during IF input. The DESAT protection circuit activates when the terminal voltage VDESAT exceeds 6.5 V (Typ.). The monitored VCE value is different from the actual IGBT VCE one due to monitoring through diode and resister. Figure 3.3 shows how to adjust the short-circuit threshold voltage when diodes are used. If Vth(IGBT) is defined the short-circuit threshold voltage based on the IGBT voltage, we can use multiple diodes connection to the DESAT terminals as shown in Figure 3.3, considering the IGBT safe operating range, the voltage drop for VF during multiple elements will force Vth(IGBT) down to a new value (New Vth(IGBT)) as per the equation below. It is important to choose diodes with high tolerant and fast reverse recovery time.

For circuits shown in Fifure2.1 and Figure2.2, GT30J341 IGBT (VGE(OFF) = 5.5 V), a single CMF05 diode (VF = 2.7 V @ 50 µA) and 100 Ω RDESAT are used. Therefore we have:
ℎ() = 6.5 − (1 × 2.7 () + 100() × 50() ≒ .

Figure 3.3 Modifying the short-circuit threshold voltage

Control signal waveform shaping

In case of the control board and motor control board are separated, the longer distance to the TLP5214A may cause generating inductance and other impacts during wiring and the input signal slope is potentially changed.
In Figure 3.4, it has an additional hysteresis buffer circuit before the TLP5214A input terminal to shape the input signal waveform.

Current control shunt resistor

In Figure 2.1 and Figure 2.2, they use the TLP7820 for motor control in a three shunt current detection configuration that measures three-phase current on the controller side. Details of the current detection circuit design are given in the TLP7820 document (RD013-RGUIDE-02).
For detail of reference guide for TLP7820 current detection circuit → Click here

Thermal design

In order to supply electric charge to (or withdraw it from) the power device gate over a short period, the gate driver photocoupler has to generate (or absorb) large amounts of output current quickly during switching. With this reason, photocoupler switching loss and heat must also be considered. Switching loss is determined by many factors including the photocoupler drive frequency, drive voltage, gate capacity and gate resistance of power device. The loss of photo detection side accounts for the bulk of the photocoupler losses. Those losses generate heat, so most of the heat is at the photo detection side. Peripheral circuit design must take care of the maximum rated junction temperature for the light receiving chip and LED chip in the photocoupler.

The following definitions are used in this document.

• Pall: total power loss in photocoupler Po,all: power loss in light receiving chip PD: power loss on LED side
• IF: LED forward current
• VF: LED forward voltage Po,DC: current consumption during DC operation
• Po(bias:on) : DC current consumption with LED on
• Po(bias:off) : DC current consumption with LED off
• Po,sw: power consumption during switching
• duty: photocoupler duty ratio Esw: electrostatic energy during switching
• ICCH: H level supply current
• ICCL: L level supply current
• VCC: positive supply voltage on output side
• fsw : switching frequency
• Rg : gate resistance
• Ron,H: photocoupler output resistance (high)
• Ron,L: photocoupler output resistance (low)
• Cg: gate capacity (Qg = Cg x VCC equivalent)
• Iop,worst: maximum value of peak output current
• Tj,LED: LED chip junction temperature*
• Tj,Photo: light receiving chip junction temperature*
• Rth(j-a),LED: thermal resistance of LED chip**
• Rth(j-a),Photo: thermal resistance of light receiving chip**

Figure 3.5 shows the calculation model (which applies equally to TLP5214A).

The procedure for determining power loss in the photocoupler light receiving chip is given below. The power loss in the light receiving chip during switching operation is the sum of power consumption during DC operation and switching loss.

1. Power loss in light receiving chip
   

2. Power consumption during DC operation

3. Power consumption during switching The amount of electrostatic energy Esw stored and/or released in a switching operation Cg is defined by:
   Given that  of the Cg electrostatic energy Esw is consumed by Rg, Ron,H and Ron,L per second, the power consumption during switching Po,sw is calculated as:
   

4. The following equations can be used to calculate the peak output current and the maximum  value of the estimated peak output current of the photocoupler output stage MOSFET on- resistance Iop,worst (note that peak output current will generally be lower in practice, since a photocoupler output stage MOSFET on-resistance is also present).

This value is used to determine the characteristics curve for the photocoupler output stage on-resistance.
We substitute the resistance value into the Po,sw equation to find the switching power consumption.

5. Light-receiving DC loss
   

6. Peak output current

Photocoupler output stage on-resistance
If we substitute 1.5 A into the VO-Iop characteristics curve for TLP5214A (Figure 3.6) we get [VOH-VCC](@ Iop,worst) = -1.2 V and VOL(@ Iop,worst) = 1.0 V, which gives us on-resistances values as follows:

Figure 3.6 Estimating the photocoupler output stage MOSFET on-resistance from the VO-Iop curve

Loss in the light receiving chip is given by the following equation:

LED power loss is given by the following equation:

Total photocoupler power consumption Pall is calculated as follows:

A simplified estimate of the junction temperatures in this example (Tj,LED and Tj,Photo), ignoring thermal interference between the LED and light-receiving chip, is shown below. This gives us an idea of the usable range in terms of thermal considerations.

Thermal resistance is different from the material of the substrate, the land pattern and the layer structure. Also, the photocoupler output terminal capacitance includes the parasitic capacitance of the substrate. So the above calculation should be considered no more than a general guide.
Note
When the TLP5214A enters protection mode the FAULT output LED on the feedback side lights and the FAULT terminal output switches from high to low to indicate an IGBT error. If protection mode is continued, the FAULT output LED on the secondary side also lights and a current of approximately 10 mA starts flowing between the VCC2 and VE terminals, increasing the power loss on the secondary side. When protection mode activate, the system must be shut down and reboot immediately (see Figures 3.7 and 3.8).

Ex) VCC2 = 30 V, FAULT mode engaged
If feedback LED current = 10 mA and the voltage at the light-receiving chip on the secondary side is 28 V (not including LED voltage drop), then power loss in the light-receiving chip is 28 V x 10 mA = 280 mW. If we take into account thermal resistance on the light-receiving chip side of the TLP5214A, the temperature increase is 0.07 x 280 = 19.6°C. This could be an issue in a hot operating environment.

Internal circuit diagram (operation path during fault)

TLP5214A timing chart (protection engaged)

Product overview

General

The TLP5214A is an advanced, highly integrated 4.0A output current IGBT gate drive photocoupler housed in a long creepage and clearance SO16L package.

•  Peak output current: ±4.0 A (max.)
• Operating temperature range: -40 to +110°C
•  Supply current: 3.8 mA (max.)
• Power supply voltage: 15 to 30 V
•  Threshold input current: 6 mA (max.)
• Propagation delay (tpLH / tpHL): 150 ns (max.)
• DESAT leading edge blanking time: 1.1 µs (typ.)
• Common mode transient immunity: ±35 kV/µs (min.)
• Isolation voltage: 5,000 Vrms (min.)
• Safety standardsd
  UL approved: UL1577, File No. E67349
  c-UL approved: CSA (Component Acceptance Service) No. 5A, File No. E67349 Option (D4) VDE: DIN EN60747-5-5, EN60065 or EN60950-1, EN62368-1 * CQC: GB4943.1 and GB8898 Japan Factory (Pending)
• When a EN60747-5-5 approved type is needed, please designate “Option(D4)”

Appearance and terminal configuration

General appearance and markings

TLP5214A appearance and markings

Terminal

No.

| Name| I/O| Description| Internal circuit configuration
---|---|---|---|---
1| VS| GND| GND on input side| Tr.(Open collector)
2| VCC1| IN| Positive supply on input side| Tr./Photo Di
3| FAULT| OUT| IGBT short (non-saturation) fault feedback; outputs L when IGBT non-saturation detected| Tr.(Open collector)
4| VS| GND| GND on input side| Tr.(Open collector)
5| CATHODE| GND| LED cathode on input side| LED
6| ANODE| IN| LED anode on input side| LED
7| ANODE| IN| LED anode on input side| LED
8| CATHODE| GND| LED cathode on input side| LED
9| VEE| IN| Negative supply on output side; connect to VE if using positive supply (VCC2) only| DMOS/CMOS
10| VCLAMP| IN| Active mirror clamp terminal; connect to IGBT gate (or to VEE if unused)| DMOS
11| VOUT| OUT| Output for IGBT turn-on/turn-off| DMOS
12| VEE| IN| Negative supply on output side; connect to VE if using positive supply (VCC2) only| DMOS/CMOS
13| VCC2| IN| Positive supply on output side| DMOS/CMOS
14| DESAT| IN| IGBT   short  (non-saturation)  detection  terminal; monitors VCE through high-voltage FRD| CMOS
15| VLED| IN| Feedback LED test terminal; leave OPEN for user use| LED/CMOS
16| VE| GND| Supply common on output side| –

Figure 4.2 TLP5214A terminals

Internal circuit block diagram

Note: 1 µF bypass capacitor required between pins 9 (VEE) and 13 (VCC2) and between pins 13 and 16 (VE).
Figure 4.3 TLP5214A internal circuit block diagram

Truth table

IF

| UVLO

（VCC2-VE）

| DESAT

(14 pin DESAT terminal input)

| FAULT

(3 pin FAULT terminal output)

| ****

VO

---|---|---|---|---
OFF| Not Active（>VUVL +）O| Not Active| High| Low
ON| Not Active（>VUVL +）O| Lo（<VDESATth）| High| High
ON| Not Active（>VUVL +）O| High>VDESATth）| Low（FAULT）| Low
ON| Active（<VUVLO ）| Not Active| High| Low
OFF|

• Active（<VUVLO ）

| Not Active| High| Low

Terms of Use

This terms of use is made between Toshiba Electronic Devices and Storage Corporation (“We”) and customers who use documents and data that are consulted to design electronics applications on which our semiconductor devices are mounted (“this Reference Design”). Customers shall comply with this terms of use. Please note that it is assumed that customers agree to any and all this terms of use if customers download this Reference Design. We may, at its sole and exclusive discretion, change, alter, modify, add, and/or remove any part of this terms of use at any time without any prior notice. We may terminate this terms of use at any time and for any reason. Upon termination of this terms of use, customers shall destroy this Reference Design. In the event of any breach thereof by customers, customers shall destroy this Reference Design, and furnish us a written confirmation to prove such destruction.

1. Restrictions on usage

2. This Reference Design is provided solely as reference data for designing electronics applications. Customers shall not use this Reference Design for any other purpose, including without limitation, verification of reliability.

3. This Reference Design is for customer’s own use and not for sale, lease or other transfer.

4. Customers shall not use this Reference Design for evaluation in high or low temperature, high humidity, or high electromagnetic environments.

5. This Reference Design shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations.

6. Limitations

7. We reserve the right to make changes to this Reference Design without notice.

8. This Reference Design should be treated as a reference only. We are not responsible for any incorrect or incomplete data and information.

9. Semiconductor devices can malfunction or fail. When designing electronics applications by referring to this Reference Design, customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of semiconductor devices could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Customers must also refer to and comply with the latest versions of all relevant our information, including without limitation, specifications, data sheets and application notes for semiconductor devices, as well as the precautions and conditions set forth in the “Semiconductor Reliability Handbook”.

10. When designing electronics applications by referring to this Reference Design, customers must evaluate the whole system adequately. Customers are solely responsible for all aspects of their own product design or applications. WE ASSUME NO LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR APPLICATIONS.

11. No responsibility is assumed by us for any infringement of patents or any other intellectual property rights of third parties that may result from the use of this Reference Design. No license to any intellectual property right is granted by this terms of use, whether express or implied, by estoppel or otherwise.

12. THIS REFERENCE DESIGN IS PROVIDED “AS IS”. WE (a) ASSUME NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (b) DISCLAIM ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO THIS REFERENCE DESIGN, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.

13. Export Control
    Customers shall not use or otherwise make available this Reference Design for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). This Reference Design may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of this Reference Design are strictly prohibited except in compliance with all applicable export laws and regulations.

14.  Governing Laws
    This terms of use shall be governed and construed by laws of Japan.

References

• GT30J341 | Toshiba Electronic Devices & Storage Corporation | Asia-English
• CMF05 | Toshiba Electronic Devices & Storage Corporation | Asia-English
• CUS05F30 | Toshiba Electronic Devices & Storage Corporation | Asia-English
• TC7SZ14F | Toshiba Electronic Devices & Storage Corporation | Asia-English
• TLP5214A | Toshiba Electronic Devices & Storage Corporation | Asia-English
• TLP7820 | Toshiba Electronic Devices & Storage Corporation | Asia-English
• CMF05 | 東芝デバイス＆ストレージ株式会社 | 日本
• Application Circuit (Current sensing) of the TLP7820 Isolation Amplifier | Toshiba Electronic Devices & Storage Corporation | Asia-English

Read User Manual Online (PDF format)

Read User Manual Online (PDF format)  >>

Download This Manual (PDF format)

Download this manual  >>