ATMEL AT90CAN32-16AU 8bit AVR Microcontroller User Guide

ATMEL AT90CAN32-16AU 8bit AVR Microcontroller User Guide

8-bit   Microcontroller with 32K/64K/128K Bytes of ISP Flash and CAN Controller

AT90CAN32
AT90CAN64
AT90CAN128

Summary

Rev. 7679HS–CAN–08/08

Features

• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
  • 133 Powerful Instructions – Most Single Clock Cycle Execution
  • 32 x 8 General Purpose Working Registers + Peripheral Control Registers
  • Fully Static Operation
  • Up to 16 MIPS Throughput at 16 MHz
  • On-chip 2-cycle Multiplier
• Non volatile Program and Data Memories
  • 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128)
  • Endurance: 10,000 Write/Erase Cycles
  • Optional Boot Code Section with Independent Lock Bits
  • Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes
  • In-System Programming by On-Chip Boot Program (CAN, UART, …)
  • True Read-While-Write Operation
  • 1K/2K/4K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64/128)
  • 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128)
  • Up to 64K Bytes Optional External Memory Space
  • Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
  • Boundary-scan Capabilities According to the JTAG Standard
  • Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits
  • Extensive On-chip Debug Support
• CAN Controller 2.0A & 2.0B – ISO 16845 Certified (1)
  • 15 Full Message Objects with Separate Identifier Tags and Masks
  • Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes
  • 1Mbits/s Maximum Transfer Rate at 8 MHz
  • Time stamping, TTC & Listening Mode (Spying or Autobaud)
• Peripheral Features
  • Programmable Watchdog Timer with On-chip Oscillator
  • 8-bit Synchronous Timer/Counter-0
  • 10-bit Prescaler
  • External Event Counter
  • Output Compare or 8-bit PWM Output
  • 8-bit Asynchronous Timer/Counter-2
  • 10-bit Prescaler
  • External Event Counter
  • Output Compare or 8-Bit PWM Output
  • 32Khz Oscillator for RTC Operation
  • Dual 16-bit Synchronous Timer/Counters-1 & 3
  • 10-bit Prescaler
  • Input Capture with Noise Canceler
  • External Event Counter
  • 3-Output Compare or 16-Bit PWM Output
  • Output Compare Modulation
  • 8-channel, 10-bit SAR ADC
  • 8 Single-ended Channels
  • 7 Differential Channels
  • 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x
  • On-chip Analog Comparator
  • Byte-oriented Two-wire Serial Interface
  • Dual Programmable Serial USART
  • Master/Slave SPI Serial Interface
  • Programming Flash (Hardware ISP)
• Special Microcontroller Features
  • Power-on Reset and Programmable Brown-out Detection
  • Internal Calibrated RC Oscillator
  • 8 External Interrupt Sources
  • 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby
  • Software Selectable Clock Frequency
  • Global Pull-up Disable
• I/O and Packages
  • 53 Programmable I/O Lines
  • 64-lead TQFP and 64-lead QFN
• Operating Voltages: 2.7 – 5.5V
• Operating temperature: Industrial (-40°C to +85°C)
• Maximum Frequency: 8 MHz at 2.7V, 16 MHz at 4.5V

Note: 1. Details on section 19.4.3 on page 242.

Description

Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128

AT90CAN32, AT90CAN64 and AT90CAN128 are hardware and software compatible. They differ only in memory sizes as shown in Table 1-1.

Table 1-1. Memory Size Summary

Part Description

The AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM, 2K/4K/4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN controller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differential input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and five software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While- Write operation. By combining an 8-bit RISC CPU with In-System Self- Programmable Flash on a monolithic chip, the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The AT90CAN32/64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

Block Diagram

Figure 1-1. Block Diagram

Pin Configurations

Figure 1-2. Pinout AT90CAN32/64/128 – TQFP

(1) NC = Do not connect (May be used in future devices)

(2) Timer2 Oscillator

Figure 1-3. Pinout AT90CAN32/64/128 – QFN

(1) NC = Do not connect (May be used in future devices)

(2) Timer2 Oscillator

Note: The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

1.6.3 Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 74.

1.6.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 76.

1.6.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the AT90CAN32/64/128 as listed on page 78.

1.6.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 80.

1.6.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 83.

1.6.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pullup resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

1.6.9 Port G (PG4..PG0)

Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 88.

1.6.10 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128.

1.6.11 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

1.6.12 XTAL2

Output from the inverting Oscillator amplifier.

1.6.13 AVCC

AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally connected to Vcc, even if the ADC is not used. If the ADC is used, it should be connected to Vcc through a low-pass filter.

1.6.14 AREF

This is the analog reference pin for the A/D Converter.

About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

Register Summary

Notes:

1. Address bits exceeding PCMSB (Table 25-11 on page 341) are don’t care.
2. Address bits exceeding EEAMSB (Table 25-12 on page 341) are don’t care.
3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
4. I/O Registers within the address range 0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
5. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 6. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 – 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Ordering Information

Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

Packaging Information

TQFP64

64 PINS THIN QUAD FLAT PACK

QFN64

NOTES: QFN STANDARD NOTES

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M. – 1994.

2. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

3. MAX. PACKAGE WARPAGE IS 0.05mm.

4. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.

5. PIN #1 ID ON TOP WILL BE LASER MARKED.

6. THIS DRAWING CONFORMES TO JEDEC REGISTERED OUTLINE MO-220.

7. A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.
   L MINUS L1 TO BE EQUAL TO OR GREATER THAN 0.30 mm

8. THE TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED THE TERMINAL #1 IDENTIFIER BE EITHER A MOLD OR MARKED FEATURE

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7679HS–CAN–08/08

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