ATMEL ATmega8515 8-bit Microcontroller with 8K Bytes In-System Programmable Flash User Guide

ATMEL ATmega8515 8-bit Microcontroller with 8K Bytes In-System

Programmable Flash

Features

• High-performance, Low-power AVR® 8-bit Microcontroller
• RISC Architecture
• 130 Powerful Instructions – Most Single Clock Cycle Execution
• 32 x 8 General Purpose Working Registers
• Fully Static Operation
• Up to 16 MIPS Throughput at 16 MHz
• On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
• 8K Bytes of In-System Self-programmable Flash
• Endurance: 10,000 Write/Erase Cycles
• Optional Boot Code Section with Independent Lock bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
• 512 Bytes EEPROM
• Endurance: 100,000 Write/Erase Cycles
• 512 Bytes Internal SRAM
• Up to 64K Bytes Optional External Memory Space
• Programming Lock for Software Security
• Peripheral Features
• One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
• One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
• Three PWM Channels
• Programmable Serial USART
• Master/Slave SPI Serial Interface
• Programmable Watchdog Timer with Separate On-chip Oscillator
• On-chip Analog Comparator
• Special Microcontroller Features
• Power-on Reset and Programmable Brown-out Detection
• Internal Calibrated RC Oscillator
• External and Internal Interrupt Sources
• Three Sleep Modes: Idle, Power-down and Standby
• I/O and Packages
• 35 Programmable I/O Lines
• 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
• Operating Voltages
• 2.7 – 5.5V for ATmega8515L
• 4.5 – 5.5V for ATmega8515
• Speed Grades
• 0 – 8 MHz for ATmega8515L
• 0 – 16 MHz for ATmega8515

Pin Configurations

Figure 1. Pinout ATmega8515

Overview

The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8515 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, an External memory interface, 35 general purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with compare modes, Internal and External interrupts, a Serial Programmable USART, a programmable Watchdog Timer with internal Oscillator, a SPI serial port, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and Interrupt system to continue functioning. The Power-down mode saves the Register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-chip ISP Flash allows the Program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While- Write operation. By combining an 8-bit RISC CPU with In-System Self- programmable Flash on a monolithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega8515 is supported with a full suite of program and system development tools including: C Compilers, Macro assemblers, Program debugger/simulators, In-circuit Emulators, and Evaluation kits.

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

AT90S4414/8515 and ATmega8515 Compatibility

The ATmega8515 provides all the features of the AT90S4414/8515. In addition, several new features are added. The ATmega8515 is backward compatible with AT90S4414/8515 in most cases. However, some incompatibilities between the two microcontrollers exist. To solve this problem, an AT90S4414/8515 compatibility mode can be selected by programming the S8515C Fuse. ATmega8515 is 100% pin compatible with AT90S4414/8515, and can replace the AT90S4414/8515 on current printed circuit boards. However, the location of Fuse bits and the electrical characteristics differs between the two devices.

AT90S4414/8515 Compatibility Mode

Programming the S8515C Fuse will change the following functionality:

• The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 53 for details.
• The double buffering of the USART Receive Registers is disabled. See “AVR USART vs. AVR UART – Compatibility” on page 137 for details.
• PORTE(2:1) will be set as output, and PORTE0 will be set as input.

Pin Descriptions

• VCC Digital supply voltage
• GND Ground.

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri- stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega8515 as listed on

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega8515 as listed on

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8515 as listed

Port E(PE2..PE0)

Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega8515 as listed

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 18 on page 46. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more details.

Register Summary

Notes

1. Refer to the USART description for details on how to access UBRRH and UCSRC.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

Instruction Set Summary

Ordering Information

Note

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities..
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

Packaging Information

COMMON DIMENSIONS (Unit of Measure = mm)

Notes

1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.

COMMON DIMENSIONS (Unit of Measure = mm)

Notes

1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010″).

COMMON DIMENSIONS (Unit of Measure = mm)

Notes

1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010″(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004″ (0.102 mm) maximum.

Errata

The revision letter in this section refers to the revision of the ATmega8515 device.

ATmega8515(L) Rev. C and D

1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable the Analog Comparator before the first conversion.

Datasheet Revision History

Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision.

Rev. 2512J-10/06

1. Updated TOP/BOTTOM description for all Timer/Counters Fast PWM mode.
2. Updated “Errata”

Rev. 2512I-08/06

1. Updated “Ordering Information”

Rev. 2512H-04/06

1. Added “Resources”
2. Updated cross reference in “Phase Correct PWM Mode”
3. Updated “Timer/Counter Interrupt Mask Register – TIMSK(1)”
4. Updated “Serial Peripheral Interface – SPI”
5. Removed obsolete section of “Calibration Byte”
6. Updated Table 10 on page 38, Table 52 on page 120, Table 94 on page 196 and Table 96

Rev. 2512G-03/05

1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”.
2. Updated “Electrical Characteristics”
3. Updated “Ordering Information”

Rev. 2512E-09/03

1. Updated “Calibrated Internal RC Oscillator”

Rev. 2512E-09/03

1. Removed “Preliminary” from the datasheet.
2. Updated Table 18 on page 46 and “Absolute Maximum Ratings” and “DC Characteristics” in “Electrical Characteristics”
3. Updated chapter “ATmega8515 Typical Characteristics”

Rev. 2512D-02/03

1. Added “EEPROM Write During Power-down Sleep Mode”
2. Improved the description in “Phase Correct PWM Mode”
3. Corrected OCn waveforms in Figure 53
4. Added note under “Filling the Temporary Buffer (page loading)” on page 173 about writing to the EEPROM during an SPM page load.
5. Updated Table 93
6. Updated “Packaging Information”

Rev. 2512C-10/02

1. Added “Using all Locations of External Memory Smaller than 64 KB”
2. Removed all TBD.
3. Added description about calibration values for 2, 4, and 8 MHz.
4. Added variation in frequency of “External Clock”
5. Added note about VBOT, Table 18
6. Updated about “Unconnected pins”
7. Updated “16-bit Timer/Counter1” on page 97, Table 51 on page 119 and Table 52
8. Updated “Enter Programming Mode” on page 184, “Chip Erase” on page 184, Figure 77 on page 187, and Figure 78 on
9. Updated “Electrical Characteristics” on page 197, “External Clock Drive” on page 199, Table 96 on page 199 and Table 97 on page 200, “SPI Timing Characteristics” on page 200 and Table 98
10. Added “Errata”

Rev. 2512B-09/02

1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

Rev. 2512A-04/02

1. Initial.

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