Atmel 8-bit AVR Microcontroller with 2/4/8K Bytes In-System Programmable Flash User Manual

Atmel 8-bit AVR Microcontroller with 2/4/8K Bytes In-System Programmable

Flash

Features

• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
• 120 Powerful Instructions – Most Single Clock Cycle Execution
• 32 x 8 General Purpose Working Registers
• Fully Static Operation
• Non-volatile Program and Data Memories
• 2/4/8K Bytes of In-System Programmable Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
• 128/256/512 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
• 128/256/512 Bytes Internal SRAM
• Programming Lock for Self-Programming Flash Program and EEPROM Data Security

Peripheral Features

• 8-bit Timer/Counter with Prescaler and Two PWM Channels
• 8-bit High Speed Timer/Counter with Separate Prescaler
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
• USI – Universal Serial Interface with Start Condition Detector
• 10-bit ADC

4 Single Ended Channels

2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)

Temperature Measurement

Programmable Watchdog Timer with Separate On-chip Oscillator

On-chip Analog Comparator

Special Microcontroller Features

debugWIRE On-chip Debug System

In-System Programmable via SPI Port

External and Internal Interrupt Sources

Low Power Idle, ADC Noise Reduction, and Power-down Modes

Enhanced Power-on Reset Circuit

Programmable Brown-out Detection Circuit

Internal Calibrated Oscillator

I/O and Packages

Six Programmable I/O Lines

8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)

Operating Voltage
– 1.8 – 5.5V for ATtiny25V/45V/85V
– 2.7 – 5.5V for ATtiny25/45/85

Speed Grade
– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 – 5.5V, 0 – 10 MHz @ 2.7 – 5.5V
– ATtiny25/45/85: 0 – 10 MHz @ 2.7 – 5.5V, 0 – 20 MHz @ 4.5 – 5.5V

Industrial Temperature Range

Low Power Consumption

Active Mode:

1 MHz, 1.8V: 300 µA

Power-down Mode:

Pin Configurations

Pinout ATtiny25/45/85

Pin Descriptions

VCC: Supply voltage.
GND: Ground.
Port B (PB5:PB0):  Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny25/45/85 as listed
On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15.

RESET:  Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 21-4 on page 165. Shorter pulses are not guaranteed to generate a reset.

The reset pin can also be used as a (weak) I/O pin.

Overview

The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode saves the register con- tents, disabling all chip functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re- programmed In-System through an SPI serial interface, by a conventional non- volatile memory programmer or by an On-chip boot code running on the AVR core.

The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Com- pilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.

About Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map.

Capacitive Touch Sensing

Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcon- trollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.

Touch sensing is easily added to any application by linking the QTouch Library and using the Application Program- ming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor.

The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of implementation, refer to the QTouch Library User Guide – also available from the Atmel website.

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

AVR CPU Core

Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure cor- rect program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Architectural Overview

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File– in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format, but there are also 32-bit instructions.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before sub- routines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Reg- ister File, 0x20 – 0x5F.

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit- functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the “Instruction Set Description” for detailed information.

Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required perfor- mance and flexibility, the following input/output schemes are supported by the Register File:

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.Most of the instructions operating on the Register File have direct access to all registers, and most of them are sin- gle cycle instructions.

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3.

In the different addressing modes these address registers have functions as fixed displacement, automatic incre- ment, and automatic decrement (see the instruction set reference for details).

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or inter- rupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

SPH and SPL — Stack Pointer Register

Bit| 15| 14| 13| 12| 11| 10| 9| 8|
---|---|---|---|---|---|---|---|---|---
0x3E| SP15| SP14| SP13| SP12| SP11| SP10| SP9| SP8| SPH
0x3D| SP7| SP6| SP5| SP4| SP3| SP2| SP1| SP0| SPL
| 7| 6| 5| 4| 3| 2| 1| 0|
Read/Write| R/W| R/W| R/W| R/W| R/W| R/W| R/W| R/W|
Read/Write| R/W| R/W| R/W| R/W| R/W| R/W| R/W| R/W|
Initial Value| RAMEND| RAMEND| RAMEND| RAMEND| RAMEND| RAMEND| RAMEND| RAMEND|
Initial Value| RAMEND| RAMEND| RAMEND| RAMEND| RAMEND| RAMEND| RAMEND| RAMEND|

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 4-5.  Single Cycle ALU Operation

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 48. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user soft- ware can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not nec- essarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG        ; store SREG value

cli        ; disable interrupts during timed sequence

sbi EECR, EEMPE        ; start EEPROM write

sbi EECR, EEPE

out SREG, r16        ; restore SREG value (I-bit)

C Code Example
char cSREG;

cSREG = SREG; / store SREG value /

/ disable interrupts during timed sequence /

_CLI();

EECR |= (1<<EEMPE); / start EEPROM write /

EECR |= (1<<EEPE);

SREG = cSREG; / restore SREG value (I-bit) /

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend- ing interrupts, as shown in this example.

Assembly Code Example

sei        ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example
_SEI(); / set Global Interrupt Enable /

_SLEEP(); / enter sleep, waiting for interrupt /

/ note: will enter sleep before any pending interrupt(s) /

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start- up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

AVR Memories

This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

In-System Re-programmable Flash Program Memory

The ATtiny25/45/85 contains 2/4/8K bytes On-chip In-System Reprogrammable Flash memory for program stor- age. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1024/2048/4096 x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny25/45/85 Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program memory locations. “Memory Program- ming” on page 147 contains a detailed description on Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire Program memory address space (see the LPM – Load Program memory instruction description).

Figure 5-1.        Program Memory Map

SRAM Data Memory

Figure 5-2 shows how the ATtiny25/45/85 SRAM Memory is organized.

The lower 224/352/607 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and the last 128/256/512 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indi- rect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z- register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in “Gen- eral Purpose Register File” on page 10.

Figure 5-2.        Data Memory Map

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3.

Figure 5-3.        On-chip Data SRAM Access Cycles EEPROM Data Memory

The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For details see “Serial Downloading” on page 151.

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC  is likely to rise or fall slowly on

Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See“Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 5-1 on page 21. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations.

Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advan- tage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after Power-up).

Erase

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 5-1 on page 21). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations.

Write

To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (program- ming time is given in Table 5-1 on page 21). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations.

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on page 31.

The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi        r16, (0<<EEPM1)|(0<<EEPM0)

out        EECR, r16

; Set up address (r18:r17) in address register

out  EEARH, r18

out  EEARL, r17

; Write data (r19) to data register

out EEDR, r19

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example
void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/ Wait for completion of previous write / while(EECR & (1<<EEPE))

;

/ Set Programming mode /

EECR = (0<<EEPM1)|(0<<EEPM0);

/ Set up address and data registers / EEAR = ucAddress;

EEDR = ucData;

/ Write logical one to EEMPE /

EECR |= (1<<EEMPE);

/ Start eeprom write by setting EEPE /

EECR |= (1<<EEPE);

}

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out  EEARH, r18

out  EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in        r16,EEDR

ret

C Code Example
unsigned char EEPROM_read(unsigned char ucAddress)

{

/ Wait for completion of previous write /

while(EECR & (1<<EEPE))

;

/ Set up address register / EEAR = ucAddress;

/ Start eeprom read by writing EERE /

EECR |= (1<<EERE);

/ Return data from data register /

return EEDR;

}

Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the

needed detection level, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

I/O Memory

The I/O space definition of the ATtiny25/45/85 is shown in “Register Summary” on page 200.

All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 – 0x1F are directly bit- accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

Register Description

EEARH – EEPROM Address Register

0x1F| –| –| –| –| –| –| –| EEAR8| EEARH
Read/Write| R| R| R| R| R| R| R| R/W
Initial Value| 0| 0| 0| 0| 0| 0| 0| X/0

Bits 7:1 – Res: Reserved Bits

These bits are reserved for future use and will always read as zero.

Bits 0 – EEAR8: EEPROM Address

This is the most significant EEPROM address bit of ATtiny85. In devices with less EEPROM, i.e.  ATtiny25/ATtiny45, this bit is reserved and will always read zero. The initial value of the EEPROM Address Regis- ter (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed.

EEARL – EEPROM Address Register

Bit

Bit 7 – EEAR7: EEPROM Address

This is the most significant EEPROM address bit of ATtiny45. In devices with less EEPROM, i.e. ATtiny25, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed.

Bits 6:0 – EEAR[6:0]: EEPROM Address

These are the (low) bits of the EEPROM Address Register. The EEPROM data bytes are addressed linearly in the range 0…(128/256/512-1). The initial value of EEAR is undefined and a proper value must be therefore be written before the EEPROM may be accessed.

EEDR – EEPROM Data Register

For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the

EEPROM at the address given by EEAR.

5.5.4        EECR – EEPROM Control Register

|
---|---
Bit        7        6        5| 4| 3| 2| 1| 0|
0x1C –| –| EEPM1| | EEPM0| EERIE| EEMPE| EEPE| EERE| EECR
Read/Write        R        R        R/W| R/W| R/W| R/W| R/W| R/W|
Initial Value        0        0        X| X| 0| 0| X| 0|

Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.

Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny25/45/85 and will always read as zero.

Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writ- ing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 5-1. EEPROM Mode Bits

Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero dis- ables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming.

Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.

Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before start- ing the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

System Clock and Clock Options

Clock Systems and their Distribution

CPU Clock

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such mod- ules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

I/O Clock – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

Flash Clock – clkFLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

Internal PLL for Fast Peripheral Clock Generation – clkPCK

The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. By default, the PLL uses the output of the internal, 8.0 MHz RC oscillator as source. Alternatively, if bit LSM of PLLCSR is set the PLL will use the output of the RC oscillator divided by two. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for Timer/Counter1 or as a system clock. See Figure 6-2. The frequency of the fast peripheral clock is divided by two when LSM of PLLCSR is set, resulting in a clock frequency of 32 MHz. Note, that LSM can not be set if PLLCLK is used as system clock.

Figure 6-2.     PCK Clocking System.

The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst case) and remains oscillating at the maximum fre- quency. It should be noted that the PLL in this case is not locked any longer with the RC oscillator clock. Therefore, it is recommended not to take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the correct operating range.

The internal PLL is enabled when:

The PLLE bit in the register PLLCSR is set.

The CKSEL fuse is programmed to ‘0001’.

The CKSEL fuse is programmed to ‘0011’.

The PLLCSR bit PLOCK is set when PLL is locked. Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.

Internal PLL in ATtiny15 Compatibility Mode

Since ATtiny25/45/85 is a migration device for ATtiny15 users there is an ATtiny15 compatibility mode for back- ward compatibility. The ATtiny15 compatibility mode is selected by programming the CKSEL fuses to ‘0011’.

In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down to 6.4 MHz and the multiplication factor of the PLL is set to 4x. See Figure 6-3. With these adjustments the clocking system is ATtiny15-compatible and the resulting fast peripheral clock has a frequency of 25.6 MHz (same as in ATtiny15).

Figure 6-3.        PCK Clocking System in ATtiny15 Compatibility Mode.

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 6-1.  Device Clocking Options Select

Device Clocking Option| CKSEL[3:0](1)
---|---
External Clock (see page 26)| 0000
High Frequency PLL Clock (see page 26)| 0001
Calibrated Internal Oscillator (see page 27)| 0010(2)
Calibrated Internal Oscillator (see page 27)| 0011(3)
Internal 128 kHz Oscillator (see page 28)| 0100
Low-Frequency Crystal Oscillator (see page 29)| 0110
Crystal Oscillator / Ceramic Resonator (see page 29)| 1000 – 1111
Reserved| 0101, 0111

For all fuses “1” means unprogrammed while “0” means programmed.

The device is shipped with this option selected.

This will select ATtiny15 Compatibility Mode, where system clock is divided by four, resulting in a 1.6 MHz clock fre- quency. For more inormation, see “Calibrated Internal Oscillator” on page 27.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2.

Table 6-2.        Number of Watchdog Oscillator Cycles

External Clock

To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “00”.

Figure 6-4.        External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-3.

Table 6-3.        Start-up Times for the External Clock Selection

SUT[1:0]| Start-up Time from Power-down| Additional Delay from Reset| Recommended Usage
---|---|---|---
00| 6 CK| 14CK| BOD enabled
01| 6 CK| 14CK + 4 ms| Fast rising power
10| 6 CK| 14CK + 64 ms| Slowly rising power
11| Reserved

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Presale can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page 31 for details.

High Frequency PLL Clock

There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as a system clock source, by program- ming the CKSEL fuses to ‘0001’, it is divided by four like shown in Table 6-4.

Table 6-4.        High Frequency PLL Clock Operating Modes

When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-5.

Table 6-5.        Start-up Times for the High Frequency PLL Clock

SUT[1:0]| Start-up Time from Power Down| Additional Delay from Power-On Reset (VCC = 5.0V)| Recommended usage
---|---|---|---
00| 14CK + 1K (1024) CK + 4 ms| 4 ms| BOD enabled

Table 6-5. Start-up Times for the High Frequency PLL Clock

SUT[1:0]| Start-up Time from Power Down| Additional Delay from Power-On Reset (VCC = 5.0V)| Recommended usage
---|---|---|---
01| 14CK + 16K (16384) CK + 4 ms| 4 ms| Fast rising power
10| 14CK + 1K (1024) CK + 64 ms| 4 ms| Slowly rising power
11| 14CK + 16K (16384) CK + 64 ms| 4 ms| Slowly rising power

Calibrated Internal Oscillator

By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See “Calibrated Internal RC Oscillator Accu- racy” on page 164 and “Internal Oscillator Speed” on page 192 for more details. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 31 for more details.

This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6-6 on page

27. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 21-2 on page 164.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on page 31, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 21-2 on page 164.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Cali- bration Bytes” on page 150.

The internal oscillator can also be set to provide a 6.4 MHz clock by writing CKSEL fuses to “0011”, as shown in Table 6-6 below. This setting is reffered to as ATtiny15 Compatibility Mode and is intended to provide a calibrated clock source at 6.4 MHz, as in ATtiny15. In ATtiny15 Compatibility Mode the PLL uses the internal oscillator running at 6.4 MHz to generate a 25.6 MHz peripheral clock signal for Timer/Counter1 (see “8-bit Timer/Counter1 in ATtiny15 Mode” on page 95). Note that in this mode of operation the 6.4 MHz clock signal is always divided by four, providing a 1.6 MHz system clock.

Table 6-6. Internal Calibrated RC Oscillator Operating Modes

0010(1)| 8.0 MHz
0011(2)| 6.4 MHz

The device is shipped with this option selected.

This setting will select ATtiny15 Compatibility Mode, where system clock is divided by four, resulting in a 1.6 MHz clock frequency.

When the calibrated 8 MHz internal oscillator is selected as clock source the start-up times are determined by the SUT Fuses as shown in Table 6-7 below.

Table 6-7.        Start-up Times for Internal Calibrated RC Oscillator Clock

SUT[1:0]| Start-up Time from Power-down| Additional Delay from Reset (VCC = 5.0V)| Recommended Usage
---|---|---|---
00| 6 CK| 14CK(1)| BOD enabled
01| 6 CK| 14CK + 4 ms| Fast rising power
10(2)| 6 CK| 14CK + 64 ms| Slowly rising power
11| Reserved

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to ensure programming mode can be entered.
2. The device is shipped with this option selected.

In ATtiny15 Compatibility Mode start-up times are determined by SUT fuses as shown in Table 6-8 below.

Table 6-8.        Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)

SUT[1:0]| Start-up Time from Power-down| Additional Delay from Reset (VCC = 5.0V)| Recommended Usage
---|---|---|---
00| 6 CK| 14CK + 64 ms|
01| 6 CK| 14CK + 64 ms|
10| 6 CK| 14CK + 4 ms|
11| 1 CK| 14CK(1)|

Note:   If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to ensure programming mode can be entered.

In summary, more information on ATtiny15 Compatibility Mode can be found in sections “Port B (PB5:PB0)” on page 2, “Internal PLL in ATtiny15 Compatibility Mode” on page 24, “8-bit Timer/Counter1 in ATtiny15 Mode” on page 95, “Limitations of debugWIRE” on page 140, “Calibration Bytes” on page 150 and in table “Clock Prescaler Select” on page 33.

Internal 128 kHz Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “0100”.

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-9.

Table 6-9.        Start-up Times for the 128 kHz Internal Oscillator

SUT[1:0]| Start-up Time from Power-down| Additional Delay from Reset| Recommended Usage
---|---|---|---
00| 6 CK| 14CK(1)| BOD enabled
01| 6 CK| 14CK + 4 ms| Fast rising power
10| 6 CK| 14CK + 64 ms| Slowly rising power
11| Reserved

Note:    If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to ensure programming mode can be entered.

Low-Frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the Low- frequency Crystal Oscillator must be selected by setting CKSEL fuses to ‘0110’. The crystal should be connected as shown in Figure 6-5. To find suit- able load capacitance for a 32.768 kHz crysal, please consult the manufacturer’s datasheet.

When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 6-10.

Table 6-10. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

SUT[1:0]| Start-up Time from Power Down| Additional Delay from Reset (VCC = 5.0V)| Recommended usage
---|---|---|---
00| 1K (1024) CK(1)| 4 ms| Fast rising power or BOD enabled
01| 1K (1024) CK(1)| 64 ms| Slowly rising power
10| 32K (32768) CK| 64 ms| Stable frequency at start-up
11| Reserved

Note: These options should be used only if frequency stability at start-up is not important.

The Low-frequency Crystal Oscillator provides an internal load capacitance, see Table 6-11 at each TOSC pin.

Table 6-11.        Capacitance of Low-Frequency Crystal Oscillator

Crystal Oscillator / Ceramic Resonator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-5. Either a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 6-12 below. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Table 6-12.        Crystal Oscillator Operating Modes

CKSEL[3:1]| Frequency Range (MHz)| Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF)
---|---|---
100(1)| 0.4 – 0.9| –
101| 0.9 – 3.0| 12 – 22
110| 3.0 – 8.0| 12 – 22
111| 8.0 –| 12 – 22

Notes:  This option should not be used with crystals, only with ceramic resonators.

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL[3:1] as shown in Table 6-12.

The CKSEL0 Fuse together with the SUT[1:0] Fuses select the start-up times as shown in Table 6-13.

Table 6-13.        Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0| SUT[1:0]| Start-up Time from Power-down| Additional Delay from Reset| Recommended Usage
---|---|---|---|---
0| 00| 258 CK(1)| 14CK + 4 ms| Ceramic resonator, fast rising power
0| 01| 258 CK(1)| 14CK + 64 ms| Ceramic resonator, slowly rising power
0| 10| 1K (1024) CK(2)| 14CK| Ceramic resonator, BOD enabled
0| 11| 1K (1024)CK(2)| 14CK + 4 ms| Ceramic resonator, fast rising power
1| 00| 1K (1024)CK(2)| 14CK + 64 ms| Ceramic resonator, slowly rising power
1| 01| 16K (16384) CK| 14CK| Crystal Oscillator, BOD enabled
1| 10| 16K (16384) CK| 14CK + 4 ms| Crystal Oscillator, fast rising power
1| 11| 16K (16384) CK| 14CK + 64 ms| Crystal Oscillator, slowly rising power

Notes

These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency sta- bility at start-up is not important for the application.

Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source set- ting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer.

System Clock Prescaler

The ATtiny25/45/85 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 32. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 6-15 on page 33.

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock fre- quency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

Clock Output Buffer

The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not be output during reset and that the normal operation of the I/O pin will be overridden when the fuse is programmed. Internal RC Oscillator, WDT Oscillator, PLL, and external clock (CLKI) can be selected when the clock is output on CLKO. Crystal oscillators (XTAL1, XTAL2) can not be used for clock output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.

Register Description

OSCCAL – Oscillator Calibration Register

Bit| 7| 6| 5| 4| 3| 2| 1| 0|
---|---|---|---|---|---|---|---|---|---
0x31| CAL7| CAL6| CAL5| CAL4| CAL3| CAL2| CAL1| CAL0| OSCCAL
Read/Write| R/W| R/W| R/W| R/W| R/W| R/W| R/W| R/W|

Bits 7:0 – CAL[7:0]: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process varia- tions from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 21-2 on page 164. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 21-2 on page 164. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL[6:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest fre- quency in that range, and a setting of 0x7F gives the highest frequency in the range.

To ensure stable operation of the MCU the calibration value should be changed in small. A variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency

Table 6-14. Internal RC Oscillator Frequency Range

OSCCAL Value| Typical Lowest  Frequency with Respect to Nominal Frequency| Typical Highest Frequency with Respect to Nominal Frequency
---|---|---
0x00| 50%| 100%
0x3F| 75%| 150%
0x7F| 100%| 200%

CLKPR – Clock Prescale Register

Bit| 7| 6| 5| 4| 3| 2| 1| 0|
---|---|---|---|---|---|---|---|---|---
0x26| CLKPCE| –| –| –| CLKPS3| CLKPS2| CLKPS1| CLKPS0| CLKPR
Read/Write| R/W| R| R| R| R/W| R/W| R/W| R/W|

Initial Value        0        0        0        0        See Bit Description

Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

Bits 6:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 – 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 6-15.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of eight at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is

chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 6-15.        Clock Prescaler Select

Note:        The prescaler is disabled in ATtiny15 compatibility mode and neither writing to CLKPR, nor programming the CKDIV8 fuse has any effect on the system clock (which will always be 1.6 MHz).

Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choice for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

Sleep Modes

Figure 6-1 on page 23 presents the different clock systems and their distribution in ATtiny25/45/85. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and their wake up sources.

Table 7-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes

| Active Clock Domains| Oscillators| Wake-up Sources
---|---|---|---
Sleep Mode| clkCPU| clkFLASH| clkIO| clkADC| clkPCK| Main Clock Source Enabled| INT0 and Pin Change| SPM/EEPROM

Ready

|

USI Start Condition

| ADC| Other I/O| Watchdog Interrupt
Idle| | | X| X| X| X| X| X| X| X| X| X
ADC Noise Reduction| | | | X| | X| X(1)| X| X| X| | X
Power-down| | | | | | | X(1)| | X| | | X

Note: For INT0, only level interrupt.

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM[1:0] bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction or Power- down) will be activated by the SLEEP instruction. See Table 7-2 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Note: that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 49 for details.

Idle Mode

When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, USI, Timer/Counter, Watchdog, and the interrupt system to continue oper- ating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in “ACSR – Analog Comparator Control and Status Register” on page 120. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

ADC Noise Reduction Mode

When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.

Power-down Mode

When the SM[1:0] bits are written to 10, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts, the USI start condition detection and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only.

Software BOD Disable

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see Table 20-4 on page 148), the BOD is actively monitoring the supply voltage during a sleep period. In some devices it is possible to save power by dis- abling the BOD by software in Power-Down sleep mode. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.

If BOD is disabled by software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the VCC level has dropped during the sleep period.

When the BOD has been disabled, the wake-up time from sleep mode will be the same as that for wakening up from RESET. The user must manually configure the wake up times such that the bandgap reference has time to start and the BOD is working correctly before the MCU continues executing code. See SUT[1:0] and CKSEL[3:0] fuse bits in table “Fuse Low Byte” on page 149

BOD disable is controlled by the BODS (BOD Sleep) bit of MCU Control Register, see “MCUCR – MCU Control Register” on page 37. Writing this bit to one turns off BOD in Power-Down, while writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active.

Writing to the BODS bit is controlled by a timed sequence and an enable bit, see “MCUCR – MCU Control Regis- ter” on page 37.

Limitations

BOD disable functionality has been implemented in the following devices, only:

ATtiny25, revision E, and newer

ATtiny45, revision D, and newer

ATtiny85, revision C, and newer

Revisions are marked on the device package and can be located as follows:

Bottom side of packages 8P3 and 8S2

Top side of package 20M1

Power Reduction Register

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 38, provides a method to reduce power consumption by stopping the clock to individual peripherals. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. See “Supply Current of I/O modules” on page 177 for examples.

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 122 for details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 119 for details on how to configure the Analog Comparator.

Brown-out Detector

If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See “Brown-out Detec- tion” on page 41 and “Software BOD Disable” on page 35 for details on how to configure the Brown- out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on page 42 for details on the start-up time.

Watchdog Timer

If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 42 for details on how to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed

by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and

it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 57 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to VCC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to “DIDR0 – Digital Input Disable Register 0” on page 121 for details.

Register Description

MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management.

0x35| BODS| PUD| SE| SM1| SM0| BODSE| ISC01| ISC00| MCUCR
Read/Write| R| R/W| R/W| R/W| R/W| R| R/W| R/W
Initial Value| 0| 0| 0| 0| 0| 0| 0| 0

Bit 7 – BODS: BOD Sleep

BOD disable functionality is available in some devices, only. See “Limitations” on page 36.

In order to disable BOD during sleep (see Table 7-1 on page 34) the BODS bit must be written to logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First, both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.

In devices where Sleeping BOD has not been implemented this bit is unused and will always read zero.

Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is exe- cuted. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0

These bits select between the three available sleep modes as shown in Table 7-2.

Table 7-2.        Sleep Mode Select

Bit 2 – BODSE: BOD Sleep Enable

BOD disable functionality is available in some devices, only. See “Limitations” on page 36.

The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is con- trolled by a timed sequence.

This bit is unused in devices where software BOD disable has not been implemented and will read as zero in those devices.

PRR – Power Reduction Register

The Power Reduction Register provides a method to reduce power consumption by allowing peripheral clock sig- nals to be disabled.

0x20| –| –| –| –| PRTIM1| PRTIM0| PRUSI| PRADC| PRR
Read/Write| R| R| R| R| R/W| R/W| R/W| R/W
Initial Value| 0| 0| 0| 0| 0| 0| 0| 0

Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

Bit 3 – PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, opera- tion will continue like before the shutdown.

Bit 2 – PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, opera- tion will continue like before the shutdown.

Bit 1 – PRUSI: Power Reduction USI

Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation.

Bit 0 – PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. Note that the ADC clock is also used by some parts of the analog comparator, which means that the analogue comparator can not be used when this bit is high.

System Control and Reset

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vec- tor. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic. Electrical parame- ters of the reset circuitry are given in “System and Reset Characteristics” on page 165.

Figure 8-1  Reset Logic

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 25.

Reset Sources

The ATtiny25/45/85 has four sources of reset:

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT).

External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.

Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “Sys- tem and Reset Characteristics” on page 165. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level.

Figure 8-2. MCU Start-up, RESET Tied to VCC

INTERNAL RESET

Figure 8-3.        MCU Start-up, RESET Extended Externally

External Reset

An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 165) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period has expired.

Figure 8-4.        External Reset During Operation

Brown-out Detection

ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT – VHYST/2.

When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure 8-5), the Brown- out Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 8-5), the delay counter starts the MCU after the Time-out period tTOUT has expired.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in “System and Reset Characteristics” on page 165.

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to “Watchdog Timer” on page 42 for details on operation of the Watchdog Timer.

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in “System and Reset Characteristics” on page 165. To save power, the reference is not always turned on. The ref- erence is on during the following situations:

When the BOD is enabled (by programming the BODLEVEL[2:0] Fuse Bits).

When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power con- sumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

Watchdog Timer

The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-3 on page 46. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 46.

The Watchdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-1 Refer to “Timed Sequences for Changing the Con- figuration of the Watchdog Timer” on page 43 for details.

Table 8-1. WDT Configuration as a Function of the Fuse Settings of WDTON

WDTON| Safety Level| WDT Initial State| How to Disable the WDT| How to Change Time- out
---|---|---|---|---
Unprogrammed| 1| Disabled| Timed sequence| No limitations
Programmed| 2| Enabled| Always enabled| Timed sequence

Figure 8-7. Watchdog Timer

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level.

Safety Level 1:  In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:

In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regard- less of the previous value of the WDE bit.

Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared.

Safety Level 2: In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following proce- dure must be followed:

In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence.

Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

Code Example

The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example(1)

WDT_off:

wdr

; Clear WDRF in MCUSR

ldi        r16, (0<<WDRF)

out        MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional Watchdog Reset

in        r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out  WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example(1)
void WDT_off(void)

{

_WDR();

/ Clear WDRF in MCUSR / MCUSR = 0x00

/ Write logical one to WDCE and WDE / WDTCR |= (1<<WDCE) | (1<<WDE);

/ Turn off WDT / WDTCR = 0x00;

}

Note: 1. See “Code Examples” on page 6.

Register Description

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

Bit| 7| 6| 5| 4| 3| 2| 1| 0|
---|---|---|---|---|---|---|---|---|---
0x34| –| –| –| –| WDRF| BORF| EXTRF| PORF| MCUSR
Read/Write| R| R| R| R| R/W| R/W| R/W| R/W|

Initial Value        0        0        0        0        See Bit Description

Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

WDTCR – Watchdog Timer Control Register

0x21| WDIF| WDIE| WDP3| WDCE| WDE| WDP2| WDP1| WDP0| WDTCR
Read/Write| R/W| R/W| R/W| R/W| R/W| R/W| R/W| R/W
Initial Value| 0| 0| 0| 0| X| 0| 0| 0

Bit 7 – WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

Bit 6 – WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs.

If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt.

Table 8-2.        Watchdog Timer Configuration

Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43.

Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:

In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts.

Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43.

In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCUSR – MCU Status Register” on page 44 for description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

Note:        If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the initialization routine.

Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1, and 0

The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 8-3.

Table 8-3. Watchdog Timer Prescale Select

WDP3| WDP2| WDP1| WDP0| Number of WDT Oscillator Cycles| Typical Time-out at VCC = 5.0V
---|---|---|---|---|---
0| 0| 0| 0| 2K (2048) cycles| 16 ms
0| 0| 0| 1| 4K (4096) cycles| 32 ms
0| 0| 1| 0| 8K (8192) cycles| 64 ms
0| 0| 1| 1| 16K (16384) cycles| 0.125 s
0| 1| 0| 0| 32K (32764) cycles| 0.25 s
0| 1| 0| 1| 64K (65536) cycles| 0.5 s
0| 1| 1| 0| 128K (131072) cycles| 1.0 s
0| 1| 1| 1| 256K (262144) cycles| 2.0 s
1| 0| 0| 0| 512K (524288) cycles| 4.0 s
1| 0| 0| 1| 1024K (1048576) cycles| 8.0 s

Table 8-3.        Watchdog Timer Prescale Select (Continued)

WDP3| WDP2| WDP1| WDP0| Number of WDT Oscillator Cycles| Typical Time-out at VCC = 5.0V
---|---|---|---|---|---
1| 0| 1| 0| Reserved(1)
1| 0| 1| 1
1| 1| 0| 0
1| 1| 0| 1
1| 1| 1| 0
1| 1| 1| 1

Note:        1. If selected, one of the valid settings below 0b1010 will be used.

Interrupts

This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85. For a general expla- nation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12.

Interrupt Vectors in ATtiny25/45/85

The interrupt vectors of ATtiny25/45/85 are described in Table 9-1below.

Table 9-1.        Reset and Interrupt Vectors

Reset
2| 0x0001| INT0| External Interrupt Request 0
3| 0x0002| PCINT0| Pin Change Interrupt Request 0
4| 0x0003| TIMER1_COMPA| Timer/Counter1 Compare Match A
5| 0x0004| TIMER1_OVF| Timer/Counter1 Overflow
6| 0x0005| TIMER0_OVF| Timer/Counter0 Overflow
7| 0x0006| EE_RDY| EEPROM Ready
8| 0x0007| ANA_COMP| Analog Comparator
9| 0x0008| ADC| ADC Conversion Complete
10| 0x0009| TIMER1_COMPB| Timer/Counter1 Compare Match B
11| 0x000A| TIMER0_COMPA| Timer/Counter0 Compare Match A
12| 0x000B| TIMER0_COMPB| Timer/Counter0 Compare Match B
13| 0x000C| WDT| Watchdog Time-out
14| 0x000D| USI_START| USI START
15| 0x000E| USI_OVF| USI Overflow

If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.

A typical and general setup for interrupt vector addresses in ATtiny25/45/85 is shown in the program example below.

Assembly Code Example

.org 0x0000| ;Set address of next| statement
rjmp RESET| ; Address 0x0000|
rjmp INT0_ISR| ; Address 0x0001|
rjmp PCINT0_ISR| ; Address 0x0002|
rjmp TIM1_COMPA_ISR| ; Address 0x0003|
rjmp TIM1_OVF_ISR| ; Address 0x0004|
rjmp TIM0_OVF_ISR| ; Address 0x0005|
rjmp EE_RDY_ISR| ; Address 0x0006|
rjmp ANA_COMP_ISR| ; Address 0x0007|
rjmp ADC_ISR| ; Address 0x0008|
rjmp TIM1_COMPB_ISR| ; Address 0x0009|
rjmp TIM0_COMPA_ISR| ; Address 0x000A|
rjmp TIM0_COMPB_ISR| ; Address 0x000B|
rjmp WDT_ISR| ; Address 0x000C|
rjmp USI_START_ISR| ; Address 0x000D|
rjmp USI_OVF_ISR| ; Address 0x000E|
RESET:| ; Main program start|