intel Quartus Prime Design Software User Guide
- June 3, 2024
- Intel
Table of Contents
intel Quartus Prime Design Software
INTRODUCTION
The Intel® Quartus® Prime Software is revolutionary in performance and productivity for FPGA, CPLD, and SoC designs, providing a fast path to convert your concept into reality. The Intel Quartus Prime Software also supports many third-party tools for synthesis, static timing analysis, board-level simulation, signal integrity analysis, and formal verification.
| INTEL QUARTUS PRIME DESIGN SOFTWARE | AVAILABILITY |
|---|
PRO EDITION
($)
| STANDARD EDITION
($)
| LITE EDITION
(FREE)
Device Support| Intel® Agilex™ series| | P| |
Intel® Stratix® series| IV, V| | P|
10| P| |
Intel® Arria® series| II| | | P1
II, V| | P|
10| P| P|
Intel® Cyclone® series| IV, V| | P| P
10 LP| | P| P
10 GX| P2| |
Intel® MAX® series| II, V, 10| | P| P
Design Flow| Partial reconfiguration| P| P3|
Block-based design| P| |
Incremental optimization| P| |
Design Entry/Planning| IP Base Suite|
P
|
P
| Available for purchase
Intel® HLS Compiler| P| P| P
Platform Designer (Standard)| | P| P
Platform Designer (Pro)| P| |
Design Partition Planner| P| P|
Chip Planner| P| P| P
Interface Planner| P| |
Logic Lock regions| P| P|
VHDL| P| P| P
Verilog| P| P| P
SystemVerilog| P| P4| P4
VHDL-2008| P| P4|
Functional Simulation| Questa-Intel® FPGA Starter Edition software| P| P| P
Questa-Intel® FPGA Edition software| P5| P5| P 65
Compilation
(Synthesis & Place and Route)
| Fitter (Place and Route)| P| P| P
Early placement| P| |
Register retiming| P| P|
Fractal synthesis| P| |
Multiprocessor support| P| P|
Timing and Power Verification| Timing Analyzer| P| P| P
Design Space Explorer II| P| P| P
Power Analyzer| P| P| P
Power and Thermal Calculator| P6| |
In-System Debug| Signal Tap Logic Analyzer| P| P| P
Transceiver toolkit| P| P|
Intel Advanced Link Analyzer| P| P|
Operating System (OS) Support| Windows/Linux 64 bit support| P| P| P
Price| | Buy Fixed – $3,995
Float – $4,995
| Buy Fixed – $2,995
Float – $3,995
| Free
Download| | Download Now| Download Now| Download Now
Notes
- The only Arria II FPGA supported is the EP2AGX45 device.
- The Intel Cyclone 10 GX device support is available for free in the Pro Edition software.
- Available for Cyclone V and Stratix V devices only and requires a partial reconfiguration license.
- Limited language support.
- Requires an additional license.
- Integrated in the Intel Quartus Prime Software and available as a standalone tool. Only supports Intel Agilex and Intel Stratix 10 devices.
ADDITIONAL DEVELOPMENT TOOLS
Intel® FPGA SDK for OpenCLTM| •No additional licenses are required.
•Supported with the Intel Quartus Prime Pro/Standard Edition Software.
•The software installation file includes the Intel Quartus Prime Pro/Standard
Edition Software and the OpenCL software.
---|---
Intel HLS Compiler| •No additional license required.
• Now available as a separate download.
• Supported with the Intel Quartus Prime Pro Edition Software.
**** DSP Builder for Intel® FPGAs| •Additional licenses are required.
•DSP Builder for Intel FPGAs (Advanced Blockset only) is supported with the
Intel Quartus Prime Pro Edition Software for Intel Agilex, Intel Stratix 10,
Intel Arria 10, and Intel Cyclone 10 GX devices.
Nios® II Embedded Design Suite
| •No additional licenses are required.
•Supported with all editions of the Intel Quartus Prime Software.
•Includes Nios II software development tools and libraries.
Intel® SoC FPGA Embedded Development Suite (SoC EDS)| • Requires additional
licenses for Arm Development Studio for Intel® SoC FPGA (Arm DS for Intel®
SoC FPGA).
• The SoC EDS Standard Edition is supported with the Intel Quartus Prime
Lite/Standard Edition Software and the SoC EDS Pro Edition is supported with
the Intel Quartus Prime Pro Edition Software.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
INTEL QUARTUS PRIME DESIGN SOFTWARE FEATURES SUMMARY
Interface Planner| Enables you to quickly create your I/O design using real
time legality checks.
---|---
Pin planner| Eases the process of assigning and managing pin assignments for
high-density and high-pin-count designs.
Platform Designer| Accelerates system development by integrating IP functions
and subsystems (collection of IP functions) using a hierarchical approach and
a high-performance interconnect based on a network-on-a-chip architecture.
Off-the-shelf IP cores| Lets you construct your system-level design using IP
cores from Intel and from Intel’s third-party IP partners.
Synthesis| Provides expanded language support for System Verilog and VHDL
2008.
Scripting support| Supports command-line operation and Tcl scripting.
Incremental optimization| Offers a faster methodology to converge to design
sign-off. The traditional fitter stage is divided into finer stages for more
control over the design flow.
Partial reconfiguration| Creates a physical region on the FPGA that can be
reconfigured to execute different functions. Synthesize, place, route, close
timing, and generate configuration bitstreams for the functions implemented in
the region.
Block-based design flows| Provides flexibility of reusing timing-closed
modules or design blocks across projects and teams.
Intel® HyperflexTM FPGA Architecture| Provides increased core performance and
power efficiency for Intel Agilex and Intel Stratix 10 devices.
Physical synthesis| Uses post placement and routing delay knowledge of a
design to improve performance.
Design space explorer (DSE)| Increases performance by automatically iterating
through combinations of Intel Quartus Prime Software settings to find optimal
results.
Extensive cross-probing| Provides support for cross-probing between
verification tools and design source files.
Optimization advisors| Provides design-specific advice to improve performance,
resource usage, and power consumption.
Chip planner| Reduces verification time while maintaining timing closure by
enabling small, post-placement and routing design changes to be implemented in
minutes.
Timing Analyzer| Provides native Synopsys Design Constraint (SDC) support and
allows you to create, manage, and analyze complex timing constraints and
quickly perform advanced timing verification.
Signal Tap logic analyzer| Supports the most channels, fastest clock speeds,
largest sample depths, and most advanced triggering capabilities available in
an embedded logic analyzer.
System Console| Enables you to easily debug your FPGA in real time using read
and write transactions. It also enables you to quickly create a GUI to help
monitor and send data into your FPGA.
Power Analyzer| Enables you to analyze and optimize both dynamic and static
power consumption accurately.
Design Assistant| A design rules checking tool that allows you to get to
design closure faster by reducing the number of iterations needed and by
enabling faster iterations with targeted guidance provided by the tool at
various stages of compilation.
Fractal synthesis| Enables the Intel Quartus Prime Software to efficiently
pack arithmetic operations in FPGA’s logic resources resulting in
significantly improved performance.
**** EDA partners| Offers EDA software support for synthesis, functional and
timing simulation, static timing analysis, board-level simulation, signal
integrity analysis, and formal verification. To see a complete list of
partners, visit
www.intel.com/fpgaedapartners.
Getting Started Steps
- Step 1: Download the free Intel Quartus Prime Lite Edition Software at www.intel.com/quartus
- Step 2: Get oriented with the Intel Quartus Prime Software interactive tutorial After installation, open the interactive tutorial on the welcome screen.
- Step 3: Sign up for training at www.intel.com/fpgatraining
© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
References
- EDA Partners: FPGA EDA Systems | Intel
- Intel Field Programmable Gate Arrays (FPGA) Technical Training | Intel
- FPGA Design Software - Intel® Quartus® Prime