F Tile Serial Lite IV Intel FPGA IP User Guide
- June 3, 2024
- Intel
Table of Contents
F Tile Serial Lite IV Intel FPGA IP
F-Tile Serial Lite IV Intel® FPGA IP User Guide
Updated for Intel® Quartus® Prime Design Suite: 22.1 IP Version: 5.0.0
Online Version Send Feedback
UG-20324
ID: 683074 Version: 2022.04.28
Contents
Contents
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide………………………………………..
4
2. F-Tile Serial Lite IV Intel FPGA IP Overview…………………………………………………………. 6 2.1.
Release Information…………………………………………………………………………………..7 2.2. Supported
Features………………………………………………………………………………….. 7 2.3. IP Version Support
Level……………………………………………………………………………..8 2.4. Device Speed Grade
Support………………………………………………………………………..8 2.5. Resource Utilization and
Latency……………………………………………………………………9 2.6. Bandwidth
Efficiency…………………………………………………………………………………. 9
3. Getting Started………………………………………………………………………………………………. 11 3.1. Installing
and Licensing Intel FPGA IP Cores…………………………………………………… 11 3.1.1. Intel FPGA IP
Evaluation Mode…………………………………………………………. 11 3.2. Specifying the IP Parameters
and Options……………………………………………………… 14 3.3. Generated File
Structure…………………………………………………………………………… 14 3.4. Simulating Intel FPGA IP
Cores…………………………………………………………………… 16 3.4.1. Simulating and Verifying the
Design………………………………………………….. 17 3.5. Synthesizing IP Cores in Other EDA
Tools………………………………………………………. 17 3.6. Compiling the Full
Design…………………………………………………………………………..18
4. Functional Description…………………………………………………………………………………….. 19 4.1. TX
Datapath…………………………………………………………………………………………..20 4.1.1. TX MAC
Adapter………………………………………………………………………….. 21 4.1.2. Control Word (CW)
Insertion…………………………………………………………… 23 4.1.3. TX
CRC………………………………………………………………………………………28 4.1.4. TX MII
Encoder…………………………………………………………………………….29 4.1.5. TX PCS and
PMA………………………………………………………………………….. 30 4.2. RX
Datapath…………………………………………………………………………………………. 30 4.2.1. RX PCS and
PMA………………………………………………………………………….. 31 4.2.2. RX MII
Decoder…………………………………………………………………………… 31 4.2.3. RX
CRC…………………………………………………………………………………….. 31 4.2.4. RX
Deskew………………………………………………………………………………….32 4.2.5. RX CW
Removal……………………………………………………………………………35 4.3. F-Tile Serial Lite IV Intel FPGA
IP Clock Architecture…………………………………………. 36 4.4. Reset and Link
Initialization………………………………………………………………………..37 4.4.1. TX Reset and
Initialization Sequence…………………………………………………. 38 4.4.2. RX Reset and
Initialization Sequence…………………………………………………. 39 4.5. Link Rate and Bandwidth
Efficiency Calculation……………………………………………….. 40
5. Parameters……………………………………………………………………………………………………. 42
6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals……………………………………………..
44 6.1. Clock Signals………………………………………………………………………………………….44 6.2. Reset
Signals………………………………………………………………………………………… 44 6.3. MAC
Signals………………………………………………………………………………………….. 45 6.4. Transceiver
Reconfiguration Signals……………………………………………………………… 48 6.5. PMA
Signals………………………………………………………………………………………….. 49
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Contents
7. Designing with F-Tile Serial Lite IV Intel FPGA IP………………………………………………… 51
7.1. Reset Guidelines…………………………………………………………………………………….. 51 7.2. Error Handling
Guidelines…………………………………………………………………………..51
8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives………………………………………….
52 9. Document Revision History for the F-Tile Serial Lite IV Intel FPGA IP
User Guide………53
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1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
This document describes IP features, architecture description, steps to generate, and guidelines to design the F-Tile Serial Lite IV Intel® FPGA IP using the F-tile transceivers in Intel AgilexTM devices.
Intended Audience
This document is intended for the following users:
· Design architects to make IP selection during the system-level design
planning phase
· Hardware designers when integrating the IP into their system-level design
· Validation engineers during the system-level simulation and hardware
validation phases
Related Documents
The following table lists other reference documents that are related to the F-Tile Serial Lite IV Intel FPGA IP.
Table 1.
Related Documents
Reference
F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide
Intel Agilex Device Data Sheet
Description
This document provides generation, usage guidelines, and functional
description of the F-Tile Serial Lite IV Intel FPGA IP design examples in
Intel Agilex devices.
This document describes the electrical characteristics, switching
characteristics, configuration specifications, and timing for Intel Agilex
devices.
Table 2.
CW RS-FEC PMA TX RX PAM4 NRZ
Acronyms and Glossary Acronym List
Acronym
Expansion Control Word Reed-Solomon Forward Error Correction Physical Medium Attachment Transmitter Receiver Pulse-Amplitude Modulation 4-Level Non-return- to-zero
continued…
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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PCS MII XGMII
Acronym
Expansion Physical Coding Sublayer Media Independent Interface 10 Gigabit Media Independent Interface
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2. F-Tile Serial Lite IV Intel FPGA IP Overview
Figure 1.
F-Tile Serial Lite IV Intel FPGA IP is suitable for high bandwidth data communication for chip-to-chip, board-to-board, and backplane applications.
The F-Tile Serial Lite IV Intel FPGA IP incorporates media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) blocks. The IP supports data transfer speeds of up to 56 Gbps per lane with a maximum of four PAM4 lanes or 28 Gbps per lane with a maximum of 16 NRZ lanes. This IP offers high bandwidth, low overhead frames, low I/O count, and supports high scalability in both numbers of lanes and speed. This IP is also easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the F-tile transceiver.
This IP supports two transmission modes:
· Basic mode–This is a pure streaming mode where data is sent without the
startof-packet, empty cycle, and end-of-packet to increase bandwidth. The IP
takes the first valid data as the start of a burst.
· Full mode–This is a packet transfer mode. In this mode, the IP sends a burst
and a sync cycle at the start and end of a packet as delimiters.
F-Tile Serial Lite IV High Level Block Diagram
Avalon Streaming Interface TX
F-Tile Serial Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL
64n lanes bits (NRZ mode)/ 2n lanes bits (PAM4 mode)
TX MAC
CW
Adapter INSERT
MII ENCODE
Custom PCS
TX PCS
TX MII
EMIB ENCODE SCRAMBLER FEC
TX PMA
n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode)
TX Serial Interface
Avalon Streaming Interface RX
64n lanes bits (NRZ mode)/ 2n lanes bits (PAM4 mode)
RX
RX PCS
CW RMV
DESKEW
MII
& ALIGN DECODE
RX MII
EMIB
DECODE BLOCK SYNC & FEC DESCRAMBLER
RX PMA
CSR
2n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode) RX Serial Interface
Avalon Memory-Mapped Interface Register Config
Legend
Soft logic
Hard logic
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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You can generate F-Tile Serial Lite IV Intel FPGA IP design examples to learn
more about the IP features. Refer to F-Tile Serial Lite IV Intel FPGA IP
Design Example User Guide.
Related Information · Functional Description on page 19 · F-Tile Serial Lite
IV Intel FPGA IP Design Example User Guide
2.1. Release Information
Intel FPGA IP versions match the Intel Quartus® Prime Design Suite software versions until v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP has a new versioning scheme.
The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Prime software version. A change in:
· X indicates a major revision of the IP. If you update the Intel Quartus
Prime software, you must regenerate the IP.
· Y indicates the IP includes new features. Regenerate your IP to include
these new features.
· Z indicates the IP includes minor changes. Regenerate your IP to include
these changes.
Table 3.
F-Tile Serial Lite IV Intel FPGA IP Release Information
Item IP Version Intel Quartus Prime Version Release Date Ordering Code
5.0.0 22.1 2022.04.28 IP-SLITE4F
Description
2.2. Supported Features
The following table lists the features available in F-Tile Serial Lite IV
Intel FPGA IP:
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Table 4.
F-Tile Serial Lite IV Intel FPGA IP Features
Feature
Description
Data Transfer
· For PAM4 mode:
— FHT supports only 56.1, 58, and 116 Gbps per lane with a maximum of 4 lanes.
— FGT supports up to 58 Gbps per lane with a maximum of 12 lanes.
Refer to Table 18 on page 42 for more details on the supported transceiver
data rates for PAM4 mode.
· For NRZ mode:
— FHT supports only 28.05 and 58 Gbps per lane with a maximum of 4 lanes.
— FGT is supporting up to 28.05 Gbps per lane with a maximum of 16 lanes.
Refer to Table 18 on page 42 for more details on the supported transceiver
data rates for NRZ mode.
· Supports continuous streaming (Basic) or packet (Full) modes.
· Supports low overhead frame packets.
· Supports byte granularity transfer for every burst size.
· Supports user-initiated or automatic lane alignment.
· Supports programmable alignment period.
PCS
· Uses hard IP logic that interfaces with Intel Agilex F-tile transceivers for
soft logic resource reduction.
· Supports PAM4 modulation mode for 100GBASE-KP4 specification. RS-FEC is
always enabled in this modulation mode.
· Supports NRZ with optional RS-FEC modulation mode.
· Supports 64b/66b encoding decoding.
Error Detection and Handling
· Supports CRC error checking on TX and RX data paths. · Supports RX link error checking. · Supports RX PCS error detection.
Interfaces
· Supports only full duplex packet transfer with independent links.
· Uses point-to-point interconnect to multiple FPGA devices with low transfer
latency.
· Supports user-defined commands.
2.3. IP Version Support Level
The Intel Quartus Prime software and Intel FPGA device support for the F-Tile Serial Lite IV Intel FPGA IP is as follows:
Table 5.
IP Version and Support Level
Intel Quartus Prime 22.1
Device Intel Agilex F-tile transceivers
IP Version Simulation Compilation Hardware Design
5.0.0
2.4. Device Speed Grade Support
The F-Tile Serial Lite IV Intel FPGA IP supports the following speed grades
for Intel Agilex F-tile devices: · Transceiver speed grade: -1, -2, and -3 ·
Core speed grade: -1, -2, and -3
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Related Information
Intel Agilex Device Data Sheet More information about the supported data rate
in Intel Agilex F-tile transceivers.
2.5. Resource Utilization and Latency
The resources and latency for the F-Tile Serial Lite IV Intel FPGA IP were obtained from the Intel Quartus Prime Pro Edition software version 22.1.
Table 6.
Intel Agilex F-Tile Serial Lite IV Intel FPGA IP Resource Utilization
The latency measurement is based on the round trip latency from the TX core
input to the RX core output.
Transceiver Type
Variant
Number of Data Lanes Mode RS-FEC ALM
Latency (TX core clock cycle)
FGT
28.05 Gbps NRZ 16
Basic Disabled 21,691 65
16
Full Disabled 22,135 65
16
Basic Enabled 21,915 189
16
Full Enabled 22,452 189
58 Gbps PAM4 12
Basic Enabled 28,206 146
12
Full Enabled 30,360 146
FHT
58 Gbps NRZ
4
Basic Enabled 15,793 146
4
Full Enabled 16,624 146
58 Gbps PAM4 4
Basic Enabled 15,771 154
4
Full Enabled 16,611 154
116 Gbps PAM4 4
Basic Enabled 21,605 128
4
Full Enabled 23,148 128
2.6. Bandwidth Efficiency
Table 7.
Bandwidth Efficiency
Variables Transceiver mode
PAM4
Streaming mode RS-FEC
Full Enabled
Basic Enabled
Serial interface bit rate in Gbps (RAW_RATE)
Burst size of a transfer in number of word (BURST_SIZE) (1)
Alignment period in clock cycle (SRL4_ALIGN_PERIOD)
56.0 2,048 4,096
56.0 4,194,304 4,096
Settings
NRZ
Full
Disabled
Enabled
28.0
28.0
2,048
2,048
4,096
4,096
Basic Disabled 28.0
Enabled 28.0
4,194,304
4,194,304
4,096
4,096 continued…
(1) The BURST_SIZE for Basic mode approaches infinity, hence a large number is used.
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Variables
Settings
64/66b encode
0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697
Overhead of a burst size in number of word (BURST_SIZE_OVHD)
2 (2)
0 (3)
2 (2)
2 (2)
0 (3)
0 (3)
Alignment marker period 81,915 in clock cycle (ALIGN_MARKER_PERIOD)
81,915
81,916
81,916
81,916
81,916
Alignment marker width in 5
5
0
4
0
4
clock cycle
(ALIGN_MARKER_WIDTH)
Bandwidth efficiency (4)
0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616
Effective rate (Gbps) (5)
54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248
Maximum user clock frequency (MHz) (6)
423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457
Related Information Link Rate and Bandwidth Efficiency Calculation on page 40
(2) In Full mode, the BURST_SIZE_OVHD size is inclusive of the START/END
paired Control Words in a data stream.
(3) For Basic mode, BURST_SIZE_OVHD is 0 because there is no START/END during
streaming.
(4) Refer to Link Rate and Bandwidth Efficiency Calculation for bandwidth
efficiency calculation.
(5) Refer to Link Rate and Bandwidth Efficiency Calculation for effective rate
calculation.
(6) Refer to Link Rate and Bandwidth Efficiency Calculation for maximum user
clock frequency calculation.
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3. Getting Started
3.1. Installing and Licensing Intel FPGA IP Cores
The Intel Quartus Prime software installation includes the Intel FPGA IP library. This library provides many useful IP cores for your production use without the need for an additional license. Some Intel FPGA IP cores require purchase of a separate license for production use. The Intel FPGA IP Evaluation Mode allows you to evaluate these licensed Intel FPGA IP cores in simulation and hardware, before deciding to purchase a full production IP core license. You only need to purchase a full production license for licensed Intel IP cores after you complete hardware testing and are ready to use the IP in production.
The Intel Quartus Prime software installs IP cores in the following locations by default:
Figure 2.
IP Core Installation Path
intelFPGA(_pro) quartus – Contains the Intel Quartus Prime software ip –
Contains the Intel FPGA IP library and third-party IP cores altera – Contains
the Intel FPGA IP library source code
Table 8.
IP Core Installation Locations
Location
Software
Intel Quartus Prime Pro Edition
Platform Windows Linux
Note:
The Intel Quartus Prime software does not support spaces in the installation path.
3.1.1. Intel FPGA IP Evaluation Mode
The free Intel FPGA IP Evaluation Mode allows you to evaluate licensed Intel
FPGA IP cores in simulation and hardware before purchase. Intel FPGA IP
Evaluation Mode supports the following evaluations without additional license:
· Simulate the behavior of a licensed Intel FPGA IP core in your system. ·
Verify the functionality, size, and speed of the IP core quickly and easily. ·
Generate time-limited device programming files for designs that include IP
cores. · Program a device with your IP core and verify your design in
hardware.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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Intel FPGA IP Evaluation Mode supports the following operation modes:
· Tethered–Allows running the design containing the licensed Intel FPGA IP
indefinitely with a connection between your board and the host computer.
Tethered mode requires a serial joint test action group (JTAG) cable connected
between the JTAG port on your board and the host computer, which is running
the Intel Quartus Prime Programmer for the duration of the hardware evaluation
period. The Programmer only requires a minimum installation of the Intel
Quartus Prime software, and requires no Intel Quartus Prime license. The host
computer controls the evaluation time by sending a periodic signal to the
device via the JTAG port. If all licensed IP cores in the design support
tethered mode, the evaluation time runs until any IP core evaluation expires.
If all of the IP cores support unlimited evaluation time, the device does not
time-out.
· Untethered–Allows running the design containing the licensed IP for a
limited time. The IP core reverts to untethered mode if the device disconnects
from the host computer running the Intel Quartus Prime software. The IP core
also reverts to untethered mode if any other licensed IP core in the design
does not support tethered mode.
When the evaluation time expires for any licensed Intel FPGA IP in the design,
the design stops functioning. All IP cores that use the Intel FPGA IP
Evaluation Mode time out simultaneously when any IP core in the design times
out. When the evaluation time expires, you must reprogram the FPGA device
before continuing hardware verification. To extend use of the IP core for
production, purchase a full production license for the IP core.
You must purchase the license and generate a full production license key
before you can generate an unrestricted device programming file. During Intel
FPGA IP Evaluation Mode, the Compiler only generates a time-limited device
programming file (
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Figure 3.
Intel FPGA IP Evaluation Mode Flow
Install the Intel Quartus Prime Software with Intel FPGA IP Library
Parameterize and Instantiate a Licensed Intel FPGA IP Core
Verify the IP in a Supported Simulator
Compile the Design in the Intel Quartus Prime Software
Generate a Time-Limited Device Programming File
Program the Intel FPGA Device and Verify Operation on the Board
No IP Ready for Production Use?
Yes Purchase a Full Production
IP License
Note:
Include Licensed IP in Commercial Products
Refer to each IP core’s user guide for parameterization steps and
implementation details.
Intel licenses IP cores on a per-seat, perpetual basis. The license fee
includes firstyear maintenance and support. You must renew the maintenance
contract to receive updates, bug fixes, and technical support beyond the first
year. You must purchase a full production license for Intel FPGA IP cores that
require a production license, before generating programming files that you may
use for an unlimited time. During Intel FPGA IP Evaluation Mode, the Compiler
only generates a time-limited device programming file (<project
name>_time_limited.sof) that expires at the time limit. To obtain your
production license keys, visit the Intel FPGA Self-Service Licensing Center.
The Intel FPGA Software License Agreements govern the installation and use of
licensed IP cores, the Intel Quartus Prime design software, and all unlicensed
IP cores.
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Related Information · Intel FPGA Licensing Support Center · Introduction to
Intel FPGA Software Installation and Licensing
3.2. Specifying the IP Parameters and Options
The IP parameter editor allows you to quickly configure your custom IP
variation. Use the following steps to specify IP options and parameters in the
Intel Quartus Prime Pro Edition software.
1. If you do not already have an Intel Quartus Prime Pro Edition project in
which to integrate your F-Tile Serial Lite IV Intel FPGA IP, you must create
one. a. In the Intel Quartus Prime Pro Edition, click File New Project Wizard
to create a new Quartus Prime project, or File Open Project to open an
existing Quartus Prime project. The wizard prompts you to specify a device. b.
Specify the device family Intel Agilex and select a production F-tile device
that meets the speed grade requirements for the IP. c. Click Finish.
2. In the IP Catalog, locate and select F-Tile Serial Lite IV Intel FPGA IP.
The New IP Variation window appears.
3. Specify a top-level name for your new custom IP variation. The parameter
editor saves the IP variation settings in a file named
4. Click OK. The parameter editor appears. 5. Specify the parameters for your
IP variation. Refer to the Parameter section for
information about F-Tile Serial Lite IV Intel FPGA IP parameters. 6.
Optionally, to generate a simulation testbench or compilation and hardware
design
example, follow the instructions in the Design Example User Guide. 7. Click
Generate HDL. The Generation dialog box appears. 8. Specify output file
generation options, and then click Generate. The IP variation
files generate according to your specifications. 9. Click Finish. The
parameter editor adds the top-level .ip file to the current
project automatically. If you are prompted to manually add the .ip file to the
project, click Project Add/Remove Files in Project to add the file. 10. After
generating and instantiating your IP variation, make appropriate pin
assignments to connect ports and set any appropriate per-instance RTL
parameters.
Related Information Parameters on page 42
3.3. Generated File Structure
The Intel Quartus Prime Pro Edition software generates the following IP output
file structure.
For information about the file structure of the design example, refer to the
F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide.
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Figure 4. F-Tile Serial Lite IV Intel FPGA IP Generated Files
example_design
Example location for your IP core design example files. The default location is example_design, but you are prompted to specify a different path.
sim Simulation files
synth IP synthesis files
synth
Subcore synthesis files
sim
Subcore Simulation files
Table 9.
F-Tile Serial Lite IV Intel FPGA IP Generated Files
File Name
Description
The Platform Designer system or top-level IP variation file.
The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.
IP or Platform Designer generation log file. A summary of the messages during IP generation.
Lists simulation parameters to support incremental regeneration.
Lists synthesis parameters to support incremental regeneration.
Contains all the required information about the IP component to integrate and
compile the IP component in the Intel Quartus Prime software.
continued…
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File Name
Description
Describes the connections and IP component parameterizations in your Platform
Designer system. You can parse its contents to get requirements when you
develop software drivers for IP components. Downstream tools such as the Nios®
II tool chain use this file. The .sopcinfo file and the system.h file
generated for the Nios II tool chain include address map information for each
slave relative to each master that accesses the slave. Different masters may
have a different address map to access a particular slave component.
Contains information about the upgrade status of the IP component.
Required input file for ip-make-simscript to generate simulation scripts for
supported simulators. The .spd file contains a list of files generated for
simulation, along with information about memories that you can initialize.
You can use the Verilog black-box (_bb.v) file as an empty module declaration
for use as a black box.
HDL example instantiation template. You can copy and paste the contents of
this file into your HDL file to instantiate the IP variation.
If IP contains register information, .regmap file generates. The .regmap file
describes the register map information of master and slave interfaces. This
file complements the .sopcinfo file by providing more detailed register
information about the system. This enables register display views and user
customizable statistics in the System Console.
Allows hard processor system (HPS) System Debug tools to view the register
maps of peripherals connected to HPS in a Platform Designer system. During
synthesis, the .svd files for slave interfaces visible to System Console
masters are stored in the .sof file in the debug section. System Console reads
this section, which Platform Designer can query for register map information.
For system slaves, Platform Designer can access the registers by name.
HDL files that instantiate each submodule or child IP for synthesis or
simulation.
Contains a ModelSim/QuestaSim script msim_setup.tcl to set up and run a
simulation.
Contains a shell script vcs_setup.sh to set up and run a VCS simulation.
Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up
and run a VCS MX simulation.
Contains a shell script xcelium_setup.sh and other setup files to set up and
run Xcelium simulation.
Contains HDL files for the IP submodules.
For each generated child IP directory, Platform Designer generates synth/ and
sim/ sub-directories.
3.4. Simulating Intel FPGA IP Cores
The Intel Quartus Prime software supports IP core RTL simulation in specific
EDA simulators. IP generation optionally creates simulation files, including
the functional simulation model, any testbench (or example design), and
vendor-specific simulator setup scripts for each IP core. You can use the
functional simulation model and any testbench or example design for
simulation. IP generation output may also include scripts to compile and run
any testbench. The scripts list all models or libraries you require to
simulate your IP core.
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The Intel Quartus Prime software provides integration with many simulators and
supports multiple simulation flows, including your own scripted and custom
simulation flows. Whichever flow you choose, IP core simulation involves the
following steps:
1. Generate IP HDL, testbench (or example design), and simulator setup script
files.
2. Set up your simulator environment and any simulation scripts.
3. Compile simulation model libraries.
4. Run your simulator.
3.4.1. Simulating and Verifying the Design
By default, the parameter editor generates simulator-specific scripts containing commands to compile, elaborate, and simulate Intel FPGA IP models and simulation model library files. You can copy the commands into your simulation testbench script, or edit these files to add commands for compiling, elaborating, and simulating your design and testbench.
Table 10. Intel FPGA IP Core Simulation Scripts
Simulator
File Directory
ModelSim
QuestaSim
VCS
VCS MX
Xcelium
Script msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh
3.5. Synthesizing IP Cores in Other EDA Tools
Optionally, use another supported EDA tool to synthesize a design that
includes Intel FPGA IP cores. When you generate the IP core synthesis files
for use with third-party EDA synthesis tools, you can create an area and
timing estimation netlist. To enable generation, turn on Create timing and
resource estimates for third-party EDA synthesis tools when customizing your
IP variation.
The area and timing estimation netlist describes the IP core connectivity and
architecture, but does not include details about the true functionality. This
information enables certain third-party synthesis tools to better report area
and timing estimates. In addition, synthesis tools can use the timing
information to achieve timing-driven optimizations and improve the quality of
results.
The Intel Quartus Prime software generates the
(7) If you did not set up the EDA tool option– which enables you to start third-party EDA simulators from the Intel Quartus Prime software–run this script in the ModelSim or QuestaSim simulator Tcl console (not in the Intel Quartus Prime software Tcl console) to avoid any errors.
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 17
3. Getting Started 683074 | 2022.04.28
3.6. Compiling the Full Design
You can use the Start Compilation command on the Processing menu in the Intel
Quartus Prime Pro Edition software to compile your design.
F-Tile Serial Lite IV Intel® FPGA IP User Guide 18
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4. Functional Description
Figure 5.
F-Tile Serial Lite IV Intel FPGA IP consists of MAC and Ethernet PCS. The MAC communicates with the custom PCS through MII interfaces.
The IP supports two modulation modes:
· PAM4–Provides 1 to 12 number of lanes for selection. The IP always
instantiates two PCS channels for each lane in PAM4 modulation mode.
· NRZ–Provides 1 to 16 number of lanes for selection.
Each modulation mode supports two data modes:
· Basic mode–This is a pure streaming mode where data is sent without the
startof-packet, empty cycle, and end-of-packet to increase bandwidth. The IP
takes the first valid data as the start of a burst.
Basic Mode Data Transfer tx_core_clkout tx_avs_ready
tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
rx_avs_valid rx_avs_data
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
ISO 9001:2015 Registered
4. Functional Description 683074 | 2022.04.28
Figure 6.
· Full mode–This is the packet mode data transfer. In this mode, the IP sends a burst and a sync cycle at the start and the end of a packet as delimiters.
Full Mode Data Transfer tx_core_clkout
tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket
rx_avs_endofpacket
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
rx_avs_data
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Related Information · F-Tile Serial Lite IV Intel FPGA IP Overview on page 6 · F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide
4.1. TX Datapath
The TX datapath consists of the following components: · MAC adapter · Control
word insertion block · CRC · MII encoder · PCS block · PMA block
F-Tile Serial Lite IV Intel® FPGA IP User Guide 20
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4. Functional Description 683074 | 2022.04.28
Figure 7. TX Datapath
From user logic
TX MAC
Avalon Streaming Interface
MAC Adapter
Control Word Insertion
CRC
MII Encoder
MII Interface Custom PCS
PCS and PMA
TX Serial Interface To Other FPGA Device
4.1.1. TX MAC Adapter
The TX MAC adapter controls the data transmission to the user logic using the
Avalon® streaming interface. This block supports user-defined information
transmission and flow control.
Transferring User-defined Information
In Full mode, the IP provides the tx_is_usr_cmd signal that you can use to initiate user-defined information cycle such as XOFF/XON transmission to the user logic. You can initiate the user-defined information transmission cycle by asserting this signal and transfer the information using tx_avs_data along with the assertion of tx_avs_startofpacket and tx_avs_valid signals. The block then deasserts the tx_avs_ready for two cycles.
Note:
The user-defined information feature is available only in Full mode.
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 21
4. Functional Description 683074 | 2022.04.28
Figure 8.
Flow Control
There are conditions where the TX MAC is not ready to receive data from the
user logic such as during link re-alignment process or when there is no data
available for transmission from the user logic. To avoid data loss due to
these conditions, the IP uses the tx_avs_ready signal to control the data flow
from the user logic. The IP deasserts the signal when the following conditions
occur:
· When tx_avs_startofpacket is asserted, tx_avs_ready is deasserted for one
clock cycle.
· When tx_avs_endofpacket is asserted, tx_avs_ready is deasserted for one
clock cycle.
· When any paired CWs is asserted tx_avs_ready is deasserted for two clock
cycles.
· When RS-FEC alignment marker insertion occurs at the custom PCS interface,
tx_avs_ready is deasserted for four clock cycles.
· Every 17 Ethernet core clock cycles in PAM4 modulation mode and every 33
Ethernet core clock cycles in NRZ modulation mode. The tx_avs_ready is
deasserted for one clock cycle.
· When user logic deasserts tx_avs_valid during no data transmission.
The following timing diagrams are examples of TX MAC adapter using tx_avs_ready for data flow control.
Flow Control with tx_avs_valid Deassertion and START/END Paired CWs
tx_core_clkout
tx_avs_valid tx_avs_data
DN
D0
D1 D2 D3
Valid signal deasserts
D4
D5 D6
tx_avs_ready tx_avs_startofpacket
Ready signal deasserts for two cycles to insert END-STRT CW
tx_avs_endofpacket
usrif_data
DN
D0
D1 D2 D3
D4
D5
CW_data
DN END STRT D0 D1 D2 D3 EMPTY D4
F-Tile Serial Lite IV Intel® FPGA IP User Guide 22
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4. Functional Description 683074 | 2022.04.28
Figure 9.
Flow Control with Alignment Marker Insertion
tx_core_clkout tx_avs_valid
tx_avs_data tx_avs_ready
DN-5 DN-4 DN-3 DN-2 DN-1
D0
DN+1
01234
tx_avs_startofpacket tx_avs_endofpacket
usrif_data CW_data CRC_data MII_data
DN-1 DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN DN+1
i_sl_tx_mii_valid
i_sl_tx_mii_d[63:0]
DN-1
DN
DN+1
i_sl_tx_mii_c[7:0]
0x0
i_sl_tx_mii_am
01234
i_sl_tx_mii_am_pre3
01234
Figure 10.
Flow Control with START/END Paired CWs Coincide with Alignment Marker Insertion
tx_core_clkout tx_avs_valid
tx_avs_data
DN-5 DN-4 DN-3 DN-2 DN-1
D0
tx_avs_ready
012 345 6
tx_avs_startofpacket
tx_avs_endofpacket
usrif_data
DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0
CW_data
DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0
CRC_data
DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0
MII_data
DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0
i_sl_tx_mii_valid
i_sl_tx_mii_d[63:0]
DN-1
END STRT D0
i_sl_tx_mii_c[7:0]
0x0
i_sl_tx_mii_am i_sl_tx_mii_am_pre3
01234
01234
4.1.2. Control Word (CW) Insertion
The F-Tile Serial Lite IV Intel FPGA IP constructs CWs based on the input
signals from the user logic. The CWs indicate packet delimiters, transmission
status information or user data to the PCS block and they are derived from
XGMII control codes.
The following table shows the description of the supported CWs:
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 23
4. Functional Description 683074 | 2022.04.28
Table 11.
START END ALIGN
Description of Supported CWs
CW
Number of Words (1 word
= 64 bits)
1
Yes
1
Yes
2
Yes
EMPTY_CYC
2
Yes
IDLE
1
No
DATA
1
Yes
In-band
Description
Start of data delimiter. End of data delimiter. Control word (CW) for RX
alignment. Empty cycle in a data transfer. IDLE (out of band). Payload.
Table 12. CW Field Description
Field RSVD num_valid_bytes_eob
EMPTY eop sop seop align CRC32 usr
Description
Reserved field. May be used for future extension. Tied to 0.
Number of valid bytes in the last word (64-bit). This is a 3bit value. ·
3’b000: 8 bytes · 3’b001: 1 byte · 3’b010: 2 bytes · 3’b011: 3 bytes · 3’b100:
4 bytes · 3’b101: 5 bytes · 3’b110: 6 bytes · 3’b111: 7 bytes
Number of non-valid words at the end of a burst.
Indicates the RX Avalon streaming interface to assert an end-of-packet signal.
Indicates the RX Avalon streaming interface to assert a start-of-packet
signal.
Indicates the RX Avalon streaming interface to assert a start-of-packet and an
end-of-packet in the same cycle.
Check RX alignment.
The values of computed CRC.
Indicates that the control word (CW) contains user-defined information.
F-Tile Serial Lite IV Intel® FPGA IP User Guide 24
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4. Functional Description 683074 | 2022.04.28
4.1.2.1. Start-of-burst CW
Figure 11. Start-of-burst CW Format
START
63:56
RSVD
55:48
RSVD
47:40
RSVD
data
39:32 31:24
RSVD RSVD
23:16
sop usr align=0 seop
15:8
channel
7:0
‘hFB(START)
control 7:0
0
0
0
0
0
0
0
1
Table 13.
In Full mode, you can insert the START CW by asserting the tx_avs_startofpacket signal. When you assert only the tx_avs_startofpacket signal, the sop bit is set. When you assert both the tx_avs_startofpacket and tx_avs_endofpacket signals, the seop bit is set.
START CW Field Values
Field sop/seop
usr (8)
align
Value
1
Depending on the tx_is_usr_cmd signal:
·
1: When tx_is_usr_cmd = 1
·
0: When tx_is_usr_cmd = 0
0
In Basic mode, the MAC sends a START CW after the reset is deasserted. If no data is available, the MAC continuously sends EMPTY_CYC paired with END and START CWs until you start sending data.
4.1.2.2. End-of-burst CW
Figure 12. End-of-burst CW Format
END
63:56
‘hFD
55:48
CRC32[31:24]
47:40
CRC32[23:16]
data 39:32 31:24
CRC32[15:8] CRC32[7:0]
23:16 eop=1 RSVD RSVD RSVD
RSVD
15:8
RSVD
EMPTY
7:0
RSVD
num_valid_bytes_eob
control
7:0
1
0
0
0
0
0
0
0
(8) This is supported only in Full mode.
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 25
4. Functional Description 683074 | 2022.04.28
Table 14.
The MAC inserts the END CW when the tx_avs_endofpacket is asserted. The END CW contains the number of valid bytes at the last data word and the CRC information.
The CRC value is a 32-bit CRC result for the data between the START CW and the data word before the END CW.
The following table shows the values of the fields in END CW.
END CW Field Values
Field eop CRC32 num_valid_bytes_eob
Value 1
CRC32 computed value. Number of valid bytes at the last data word.
4.1.2.3. Alignment Paired CW
Figure 13. Alignment Paired CW Format
ALIGN CW Pair with START/END
64+8bits XGMII Interface
START
63:56
RSVD
55:48
RSVD
47:40
RSVD
data
39:32 31:24
RSVD RSVD
23:16 eop=0 sop=0 usr=0 align=1 seop=0
15:8
RSVD
7:0
‘hFB
control 7:0
0
0
0
0
0
0
0
1
64+8bits XGMII Interface
END
63:56
‘hFD
55:48
RSVD
47:40
RSVD
data
39:32 31:24
RSVD RSVD
23:16 eop=0 RSVD RSVD RSVD
RSVD
15:8
RSVD
7:0
RSVD
control 7:0
1
0
0
0
0
0
0
0
The ALIGN CW is a paired CW with START/END or END/START CWs. You can insert the ALIGN paired CW by either asserting the tx_link_reinit signal, set the Alignment Period counter, or initiating a reset. When the ALIGN paired CW is inserted, the align field is set to 1 to initiate the receiver alignment block to check data alignment across all lanes.
F-Tile Serial Lite IV Intel® FPGA IP User Guide 26
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4. Functional Description 683074 | 2022.04.28
Table 15.
ALIGN CW Field Values
Field align
eop sop usr seop
Value 1 0 0 0 0
4.1.2.4. Empty-cycle CW
Figure 14. Empty-cycle CW Format
EMPTY_CYC Pair with END/START
64+8bits XGMII Interface
END
63:56
‘hFD
55:48
RSVD
47:40
RSVD
data
39:32 31:24
RSVD RSVD
23:16 eop=0 RSVD RSVD RSVD
RSVD
15:8
RSVD
RSVD
7:0
RSVD
RSVD
control 7:0
1
0
0
0
0
0
0
0
64+8bits XGMII Interface
START
63:56
RSVD
55:48
RSVD
47:40
RSVD
data
39:32 31:24
RSVD RSVD
23:16
sop=0 usr=0 align=0 seop=0
15:8
RSVD
7:0
‘hFB
control 7:0
0
0
0
0
0
0
0
1
Table 16.
When you deassert tx_avs_valid for two clock cycles during a burst, the MAC inserts an EMPTY_CYC CW paired with END/START CWs. You can use this CW when there is no data available for transmission momentarily.
When you deassert tx_avs_valid for one cycle, the IP deasserts tx_avs_valid for twice the period of tx_avs_valid deassertion to generate a pair of END/START CWs.
EMPTY_CYC CW Field Values
Field align
eop
Value 0 0
continued…
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 27
4. Functional Description 683074 | 2022.04.28
Field sop usr seop
Value 0 0 0
4.1.2.5. Idle CW
Figure 15. Idle CW Format
IDLE CW
63:56
‘h07
55:48
‘h07
47:40
‘h07
data
39:32 31:24
‘h07 ‘h07
23:16
‘h07
15:8
‘h07
7:0
‘h07
control 7:0
1
1
1
1
1
1
1
1
The MAC insert the IDLE CW when there is no transmission. During this period,
the tx_avs_valid signal is low.
You can use the IDLE CW when a burst transfer has completed or the
transmission is in an idle state.
4.1.2.6. Data Word
The data word is the payload of a packet. The XGMII control bits are all set to 0 in data word format.
Figure 16. Data Word Format
64+8 bits XGMII Interface
DATA WORD
63:56
user data 7
55:48
user data 6
47:40
user data 5
data
39:32 31:24
user data 4 user data 3
23:16
user data 2
15:8
user data 1
7:0
user data 0
control 7:0
0
0
0
0
0
0
0
0
4.1.3. TX CRC
You can enable the TX CRC block using the Enable CRC parameter in the IP
Parameter Editor. This feature is supported in both Basic and Full modes.
F-Tile Serial Lite IV Intel® FPGA IP User Guide 28
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4. Functional Description 683074 | 2022.04.28
The MAC adds the CRC value to the END CW by asserting the tx_avs_endofpacket
signal. In the BASIC mode, only the ALIGN CW paired with END CW contains a
valid CRC field.
The TX CRC block interfaces with the TX Control Word Insertion and TX MII
Encode block. The TX CRC block computes the CRC value for 64-bit value per-
cycle data starting from the START CW up to the END CW.
You can assert the crc_error_inject signal to intentionally corrupt data in a
specific lane to create CRC errors.
4.1.4. TX MII Encoder
The TX MII encoder handles the packet transmission from the MAC to the TX PCS.
The following figure shows the data pattern on the 8-bit MII bus in PAM4 modulation mode. The START and END CW appear once in every two MII lanes.
Figure 17. PAM4 Modulation Mode MII Data Pattern
CYCLE 1
CYCLE 2
CYCLE 3
CYCLE 4
CYCLE 5
SOP_CW
DATA_1
DATA_9 DATA_17
IDLE
DATA_DUMMY SOP_CW
DATA_DUMMY
DATA_2 DATA_3 DATA_4
DATA_10 DATA_11 DATA_12
DATA_18 DATA_19 DATA_20
EOP_CW IDLE
EOP_CW
SOP_CW
DATA_5 DATA_13 DATA_21
IDLE
DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW
SOP_CW DATA_DUMMY
DATA_7 DATA_8
DATA_15 DATA_16
DATA_23 DATA_24
IDLE EOP_CW
The following figure shows the data pattern on the 8-bit MII bus in NRZ modulation mode. The START and END CW appear in every MII lanes.
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 29
4. Functional Description 683074 | 2022.04.28
Figure 18. NRZ Modulation Mode MII Data Pattern
CYCLE 1
CYCLE 2
CYCLE 3
SOP_CW
DATA_1
DATA_9
SOP_CW
DATA_2 DATA_10
SOP_CW SOP_CW
DATA_3 DATA_4
DATA_11 DATA_12
SOP_CW
DATA_5 DATA_13
SOP_CW
DATA_6 DATA_14
SOP_CW
DATA_7 DATA_15
SOP_CW
DATA_8 DATA_16
CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24
CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW
4.1.5. TX PCS and PMA
The F-Tile Serial Lite IV Intel FPGA IP configures the F-tile transceiver to
Ethernet PCS mode.
4.2. RX Datapath
The RX datapath consists of the following components: · PMA block · PCS block
· MII decoder · CRC · Deskew block · Control Word removal block
F-Tile Serial Lite IV Intel® FPGA IP User Guide 30
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4. Functional Description 683074 | 2022.04.28
Figure 19. RX Datapath
To user logic Avalon Streaming Interface
RX MAC
Control Word Removal
Deskew
CRC
MII Decoder
MII Interface Custom PCS
PCS and PMA
RX Serial Interface From Other FPGA Device
4.2.1. RX PCS and PMA
The F-Tile Serial Lite IV Intel FPGA IP configures F-tile transceiver to
Ethernet PCS mode.
4.2.2. RX MII Decoder
This block identifies if incoming data contains control word and alignment
markers. The RX MII decoder outputs data in the form of 1-bit valid, 1-bit
marker indicator, 1bit control indicator, and 64-bit data per lane.
4.2.3. RX CRC
You can enable the TX CRC block using the Enable CRC parameter in the IP
Parameter Editor. This feature is supported in both Basic and Full modes. The
RX CRC block interfaces with the RX Control Word Removal and RX MII Decoder
blocks. The IP asserts rx_crc_error signal when a CRC error occurs.
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 31
4. Functional Description 683074 | 2022.04.28
The IP deasserts the rx_crc_error at every new burst. It is an output to the
user logic for user logic error handling.
4.2.4. RX Deskew
The RX deskew block detects the alignment markers for each lane and re-aligns
the data before sending it to the RX CW removal block.
You can choose to let the IP core to align the data for each lane
automatically when an alignment error occurs by setting the Enable Auto
Alignment parameter in the IP parameter Editor. If you disable the automatic
alignment feature, the IP core asserts the rx_error signal to indicate
alignment error. You must assert the rx_link_reinit to initiate the lane
alignment process when a lane alignment error occurs.
The RX deskew detects the alignment markers based on a state machine. The
following diagram shows the states in the RX deskew block.
F-Tile Serial Lite IV Intel® FPGA IP User Guide 32
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4. Functional Description 683074 | 2022.04.28
Figure 20.
RX Deskew Lane Alignment State Machine with Auto Alignment Enabled Flow Chart
Start
IDLE
Reset = 1 yes no
All PCS
no
lanes ready?
yes
WAIT
All sync markers no
detected?
yes
ALIGN
no
yes Timeout?
yes
Lost of alignment?
no End
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 33
4. Functional Description 683074 | 2022.04.28
Figure 21.
RX Deskew Lane Alignment State Machine with Auto Alignment Disabled Flow Chart
Start
IDLE
Reset = 1 yes no
All PCS
no
lanes ready?
yes
yes
rx_link_reinit =1
no ERROR
no yes Timeout?
WAIT
no All sync markers
detected?
yes ALIGN
yes
Lost of alignment?
no
End
1. The alignment process starts with the IDLE state. The block moves to WAIT
state when all PCS lanes are ready and rx_link_reinit is deasserted.
2. In WAIT state, the block checks all detected markers are asserted within
the same cycle. If this condition is true, the block moves to the ALIGNED
state.
3. When the block is in the ALIGNED state, it indicates the lanes are
aligned. In this state, the block continues to monitor lane alignment and
check if all markers are present within the same cycle. If at least one marker
is not present in the same cycle and the Enable Auto Alignment parameter is
set, the block goes to the
F-Tile Serial Lite IV Intel® FPGA IP User Guide 34
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4. Functional Description 683074 | 2022.04.28
IDLE state to re-initialize the alignment process. If Enable Auto Alignment is not set and at least one marker is not present in the same cycle, the block goes to ERROR state and waits for the user logic to assert rx_link_reinit signal to initiate lane alignment process.
Figure 22. Lane Realignment with Enable Auto Alignment Enabled rx_core_clk
rx_link_up
rx_link_reinit
and_all_markers
Deskew State
ALGNED
IDLE
WAIT
ALGNED
AUTO_ALIGN = 1
Figure 23. Lane Realignment with Enable Auto Alignment Disabled rx_core_clk
rx_link_up
rx_link_reinit
and_all_markers
Deskew State
ALGNED
ERROR
IDLE
WAIT
ALGNED
AUTO_ALIGN = 0
4.2.5. RX CW Removal
This block decodes the CWs and sends data to the user logic using the Avalon
streaming interface after the removal of the CWs.
When there is no valid data available, the RX CW removal block deasserts the
rx_avs_valid signal.
In FULL mode, if the user bit is set, this block asserts the rx_is_usr_cmd
signal and the data in the first clock cycle is used as user-defined
information or command.
When rx_avs_ready deasserts and rx_avs_valid asserts, the RX CW removal block
generates an error condition to the user logic.
The Avalon streaming signals related to this block are as follow: ·
rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty ·
rx_avs_data
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F-Tile Serial Lite IV Intel® FPGA IP User Guide 35
4. Functional Description 683074 | 2022.04.28
· rx_avs_valid
· rx_num_valid_bytes_eob
· rx_is_usr_cmd (only available in Full mode)
4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture
The F-Tile Serial Lite IV Intel FPGA IP has four clock inputs which generate
clocks to different blocks: · Transceiver reference clock (xcvr_ref_clk)–Input
clock from external clock
chips or oscillators which generates clocks for TX MAC, RX MAC, and TX and RX
custom PCS blocks. Refer to Parameters for supported frequency range. · TX
core clock (tx_core_clk)–This clock is derived from transceiver PLL is used
for TX MAC. This clock is also an output clock from the F-tile transceiver to
connect to the TX user logic. · RX core clock (rx_core_clk)–This clock is
derived from the transceiver PLL is used for RX deskew FIFO and RX MAC. This
clock is also an output clock from the F-tile transceiver to connect to the RX
user logic. · Clock for transceiver reconfiguration interface
(reconfig_clk)–input clock from external clock circuits or oscillators which
generates clocks for F-tile transceiver reconfiguration interface in both TX
and RX datapaths. The clock frequency is 100 to 162 MHz.
The following block diagram shows F-Tile Serial Lite IV Intel FPGA IP clock
domains and the connections within the IP.
F-Tile Serial Lite IV Intel® FPGA IP User Guide 36
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4. Functional Description 683074 | 2022.04.28
Figure 24.
F-Tile Serial Lite IV Intel FPGA IP Clock Architecture
Oscillator
FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface
Clock
(reconfig_clk)
tx_core_clkout (connect to user logic)
tx_core_clk= clk_pll_div64[mid_ch]
FPGA2
F-Tile Serial Lite IV Intel FPGA IP
Transceiver Reconfiguration Interface Clock
(reconfig_clk)
Oscillator
rx_core_clk= clk_pll_div64[mid_ch]
rx_core_clkout (connect to user logic)
clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]
Avalon Streaming Interface TX Data
TX MAC
serial_link[n-1:0]
Deskew
TX
RX
FIFO
Avalon Streaming Interface RX Data RX MAC
Avalon Streaming Interface RX Data
RX MAC
Deskew FIFO
rx_core_clkout (connect to user logic)
rx_core_clk= clk_pll_div64[mid_ch]
Custom PCS
Custom PCS
serial_link[n-1:0]
RX
TX
TX MAC
Avalon Streaming Interface TX Data
tx_core_clk= clk_pll_div64[mid_ch]
tx_core_clkout (connect to user logic)
Transceiver Ref Clock (xcvr_ref_clk)
Transceiver Ref Clock (xcvr_ref_clk)
Oscillator*
Oscillator*
Legend
FPGA device
TX core clock domain
RX core clock domain
Transceiver reference clock domain External device Data signals
4.4. Reset and Link Initialization
The MAC, F-tile Hard IP, and reconfiguration blocks have different reset
signals: · TX and RX MAC blocks use tx_core_rst_n and rx_core_rst_n reset
signals. · tx_pcs_fec_phy_reset_n and rx_pcs_fec_phy_reset_n reset signals
drive
the soft reset controller to reset the F-tile Hard IP. · Reconfiguration block
uses the reconfig_reset reset signal.
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4. Functional Description 683074 | 2022.04.28
Figure 25. Reset Architecture
Avalon Streaming Interface TX Data
MAC
Avalon Streaming SYNC Interface RX Data
FPGA F-tile Serial Lite IV Intel FPGA IP
tx_mii rx_mii
phy_ehip_ready phy_rx_pcs_ready
F-tile Hard IP
TX Serial Data RX Serial Data
tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset
Reset Logic
Related Information · Reset Guidelines on page 51 · F-Tile Serial Lite IV
Intel FPGA IP Design Example User Guide
4.4.1. TX Reset and Initialization Sequence
The TX reset sequence for F-Tile Serial Lite IV Intel FPGA IP is as follows:
- Assert tx_pcs_fec_phy_reset_n, tx_core_rst_n, and reconfig_reset
simultaneously to reset the F-tile hard IP, MAC, and reconfiguration blocks. Release tx_pcs_fec_phy_reset_n and reconfiguration reset after waiting for tx_reset_ack to ensure the blocks are properly reset. 2. The IP then asserts the phy_tx_lanes_stable, tx_pll_locked, and phy_ehip_ready signals after tx_pcs_fec_phy_reset_n reset is released, to indicate the TX PHY is ready for transmission. 3. The tx_core_rst_n signal deasserts after phy_ehip_ready signal goes high. 4. The IP starts transmitting IDLE characters on the MII interface once the MAC is out of reset. There is no requirement for TX lane alignment and skewing because all lanes use the same clock. 5. While transmitting IDLE characters, the MAC asserts the tx_link_up signal. 6. The MAC then starts transmitting ALIGN paired with START/END or END/START CW at a fixed interval to initiate the lane alignment process of the connected receiver.
F-Tile Serial Lite IV Intel® FPGA IP User Guide 38
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Figure 26.
TX Reset and Initialization Timing Diagram
reconfig_sl_clk
reconfig_clk
tx_core_rst_n
1
tx_pcs_fec_phy_reset_n 1
3
reconfig_reset
1
3
reconfig_sl_reset
1
3
tx_reset_ack
2
tx_pll _locked
4
phy_tx_lanes_stable
phy_ehip_ready
tx_li nk_up
7
5 6 8
4.4.2. RX Reset and Initialization Sequence
The RX reset sequence for F-Tile Serial Lite IV Intel FPGA IP is as follows:
1. Assert rx_pcs_fec_phy_reset_n, rx_core_rst_n, and reconfig_reset
simultaneously to reset the F-tile hard IP, MAC, and reconfiguration blocks.
Release rx_pcs_fec_phy_reset_n and reconfiguration reset after waiting for
rx_reset_ack to ensure the blocks are properly reset.
2. The IP then asserts the phy_rx_pcs_ready signal after the custom PCS reset
is released, to indicate RX PHY is ready for transmission.
3. The rx_core_rst_n signal deasserts after phy_rx_pcs_ready signal goes
high.
4. The IP starts the lane alignment process after the RX MAC reset is
released and upon receiving ALIGN paired with START/END or END/START CW.
5. The RX deskew block asserts the rx_link_up signal once alignment for all
lanes has complete.
6. The IP then asserts the rx_link_up signal to the user logic to indicate
that the RX link is ready to start data reception.
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4. Functional Description 683074 | 2022.04.28
Figure 27. RX Reset and Initialization Timing Diagram
reconfig_sl_clk
reconfig_clk
rx_core_rst_n
1
rx_pcs_fec_phy_reset_n 1
reconfig_reset
1
reconfig_sl_reset
1
rx_reset_ack
rx_cdr_lock
rx_block_lock
rx_pcs_ready
rx_link_up
3 3 3 2
4 5 5
6 7
4.5. Link Rate and Bandwidth Efficiency Calculation
The F-Tile Serial Lite IV Intel FPGA IP bandwidth efficiency calculation is as below:
Bandwidth efficiency = raw_rate 64/66 (burst_size – burst_size_ovhd)/burst_size [align_marker_period / (align_marker_period + align_marker_width)] [(srl4_align_period – 2) / srl4_align_period]
Table 17. Bandwidth Efficiency Variables Description
Variable
Description
raw_rate burst_size
This is the bit rate achieved by the serial interface. raw_rate = SERDES width
- transceiver clock frequency Example: raw_rate = 64 * 402.812500 Gbps = 25.78
Gbps
Value of burst size. To calculate average bandwidth efficiency, use common burst size value. For maximum rate, use maximum burst size value.
burst_size_ovhd
The burst size overhead value.
In Full mode, the burst_size_ovhd value is referring to the START and END
paired CWs.
In Basic mode, there is no burst_size_ovhd because there is no START and END
paired CWs.
align_marker_period
The value of the period where an alignment marker is inserted. The value is 81920 clock cycle for compilation and 1280 for fast simulation. This value is obtained from the PCS hard logic.
align_marker_width srl4_align_period
The number of clock cycles where a valid alignment marker signal is held high.
The number of clock cycles between two alignment markers. You can set this
value using the Alignment Period parameter in the IP Parameter Editor.
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The link rate calculations are as below: Effective rate = bandwidth efficiency
- raw_rate You can get the maximum user clock frequency with the following equation. The maximum user clock frequency calculation assumes continuous data streaming and no IDLE cycle occurs at the user logic. This rate is important when designing the user logic FIFO to avoid FIFO overflow. Maximum user clock frequency = effective rate / 64
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5. Parameters
Table 18. F-Tile Serial Lite IV Intel FPGA IP Parameter Description
Parameter
Value
Default
Description
General Design Options
PMA modulation type
· PAM4 · NRZ
PAM4
Select the PCS modulation mode.
PMA Type
· FHT · FGT
FGT
Selects the transceiver type.
PMA data rate
· For PAM4 mode:
— FGT transceiver type: 20 Gbps 58 Gbps
— FHT transceiver type: 56.1 Gbps, 58 Gbps, 116 Gbps
· For NRZ mode:
— FGT transceiver type: 10 Gbps 28.05 Gbps
— FHT transceiver type: 28.05 Gbps, 58 Gbps
56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)
Specifies the effective data rate at the output of the transceiver incorporating transmission and other overheads. The value is calculated by the IP by rounding up to 1 decimal place in Gbps unit.
PMA mode
· Duplex · Tx · Rx
Duplex
For FHT transceiver type, the supported direction is duplex only. For FGT transceiver type, the supported direction is Duplex, Tx, and Rx.
Number of PMA
· For PAM4 mode:
2
lanes
— 1 to 12
· For NRZ mode:
— 1 to 16
Select the number of lanes. For simplex design, the supported number of lanes is 1.
PLL reference clock frequency
· For FHT transceiver type: 156.25 MHz
· For FGT transceiver type: 27.5 MHz 379.84375 MHz, depending on the
selected transceiver data rate.
· For FHT transceiver type: 156.25 MHz
· For FGT transceiver type: 165 MHz
Specifies the reference clock frequency of the transceiver.
System PLL
—
reference clock
frequency
170 MHz
Only available for FHT transceiver type. Specifies the System PLL reference clock and will be used as input of F-Tile Reference and System PLL Clocks Intel FPGA IP to generate the System PLL clock.
System PLL frequency
Alignment Period
— 128 65536
Enable RS-FEC
Enable
876.5625 MHz 128 Enable
Specifies the System PLL clock frequency.
Specifies the alignment marker period. The value must be x2. Turn on to enable
the RS-FEC feature.
continued…
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
ISO 9001:2015 Registered
5. Parameters 683074 | 2022.04.28
Parameter
Value
Default
Description
Disable
For PAM4 PCS modulation mode, RS-FEC is always enabled.
User Interface
Streaming mode
· FULL · BASIC
Full
Select the data streaming for the IP.
Full: This mode sends a start-of-packet and end-of-packet cycle within a frame.
Basic: This is a pure streaming mode where data is sent without a start-of- packet, empty, and end-of-packet to increase bandwidth.
Enable CRC
Enable Disable
Disable
Turn on to enable CRC error detection and correction.
Enable auto alignment
Enable Disable
Disable
Turn on to enable automatic lane alignment feature.
Enable debug endpoint
Enable Disable
Disable
When ON, the F-Tile Serial Lite IV Intel FPGA IP includes an embedded Debug Endpoint that internally connects to the Avalon memory-mapped interface. The IP can perform certain tests and debug functions through JTAG using the System Console. Default value is Off.
Simplex Merging (This parameter setting is only available when you select FGT dual simplex design.)
RSFEC enabled on the other Serial Lite IV Simplex IP placed at the same FGT channel(s)
Enable Disable
Disable
Turn on this option if you require a mixture of configuration with RS-FEC enabled and disabled for the F-Tile Serial Lite IV Intel FPGA IP in a dual simplex design for NRZ transceiver mode, where both TX and RX are placed on the same FGT channel(s).
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6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals
6.1. Clock Signals
Table 19. Clock Signals
Name
Width Direction
Description
tx_core_clkout
1
Output TX core clock for the TX custom PCS interface, TX MAC and user logics in
the TX datapath.
This clock is generated from the custom PCS block.
rx_core_clkout
1
Output RX core clock for the RX custom PCS interface, RX deskew FIFO, RX MAC
and user logics in the RX datapath.
This clock is generated from the custom PCS block.
xcvr_ref_clk
reconfig_clk reconfig_sl_clk
1
Input Transceiver reference clock.
When the transceiver type is set to FGT, connect this clock to the output signal (out_refclk_fgt_0) of the F-Tile Reference and System PLL Clocks Intel FPGA IP. When the transceiver type is set to FHT, connect
this clock to the output signal (out_fht_cmmpll_clk_0) of the F-Tile Reference and System PLL Clocks Intel FPGA IP.
Refer to Parameters for supported frequency range.
1
Input Input clock for transceiver reconfiguration interface.
The clock frequency is 100 to 162 MHz.
Connect this input clock signal to external clock circuits or oscillators.
1
Input Input clock for transceiver reconfiguration interface.
The clock frequency is 100 to 162 MHz.
Connect this input clock signal to external clock circuits or oscillators.
out_systempllclk
Input
System PLL clock.
Connect this clock to the output signal (out_systempll_clk_0) of the F-Tile
Reference and System PLL Clocks Intel FPGA IP.
Related Information Parameters on page 42
6.2. Reset Signals
Table 20. Reset Signals
Name
Width Direction
tx_core_rst_n
1
Input
Clock Domain Asynchronous
rx_core_rst_n
1
Input
Asynchronous
tx_pcs_fec_phy_reset_n 1
Input
Asynchronous
Description
Active-low reset signal. Resets the F-Tile Serial Lite IV TX MAC.
Active-low reset signal. Resets the F-Tile Serial Lite IV RX MAC.
Active-low reset signal.
continued…
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals 683074 | 2022.04.28
Name
Width Direction Clock Domain
Description
Resets the F-Tile Serial Lite IV TX custom PCS.
rx_pcs_fec_phy_reset_n 1
Input
Asynchronous
Active-low reset signal. Resets the F-Tile Serial Lite IV RX custom PCS.
reconfig_reset
1
Input
reconfig_clk Active-high reset signal.
Resets the Avalon memory-mapped interface reconfiguration block.
reconfig_sl_reset
1
Input reconfig_sl_clk Active-high reset signal.
Resets the Avalon memory-mapped interface reconfiguration block.
6.3. MAC Signals
Table 21.
TX MAC Signals
In this table, N represents the number of lanes set in the IP parameter
editor.
Name
Width
Direction Clock Domain
Description
tx_avs_ready
1
Output tx_core_clkout Avalon streaming signal.
When asserted, indicates that the TX MAC is ready to accept data.
tx_avs_data
· (64N)2 (PAM4 mode)
· 64*N (NRZ mode)
Input
tx_core_clkout Avalon streaming signal. TX data.
tx_avs_channel
8
Input tx_core_clkout Avalon streaming signal.
The channel number for data being transferred on the current cycle.
This signal is not available in Basic mode.
tx_avs_valid
1
Input tx_core_clkout Avalon streaming signal.
When asserted, indicates the TX data signal is valid.
tx_avs_startofpacket
1
Input tx_core_clkout Avalon streaming signal.
When asserted, indicates the start of a TX data packet.
Assert for only a single clock cycle for each packet.
This signal is not available in Basic mode.
tx_avs_endofpacket
1
Input tx_core_clkout Avalon streaming signal.
When asserted, indicates the end of a TX data packet.
Assert for only a single clock cycle for each packet.
This signal is not available in Basic mode.
tx_avs_empty
5
Input tx_core_clkout Avalon streaming signal.
Indicates the number of non-valid words in the final burst of the TX data.
This signal is not available in Basic mode.
tx_num_valid_bytes_eob
4
Input
tx_core_clkout
Indicates the number of valid bytes in the last word of the final burst. This
signal is not available in Basic mode.
continued…
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Name tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error
Width 1
1 1
N 5
Direction Clock Domain
Description
Input
tx_core_clkout
When asserted, this signal initiate a userdefined information cycle.
Assert this signal at the same clock cycle as tx_startofpacket assertion.
This signal is not available in Basic mode.
Output tx_core_clkout When asserted, indicates the TX data link is ready for data transmission.
Output
tx_core_clkout
When asserted, this signal initiates lanes re-alignment.
Assert this signal for one clock cycle to trigger the MAC to send ALIGN CW.
Input
tx_core_clkout When asserted, the MAC injects a CRC32 error to selected lanes.
Output tx_core_clkout Not used.
The following timing diagram shows an example of TX data transmissions of 10 words from user logic across 10 TX serial lanes.
Figure 28.
TX Data Transmission Timing Diagram
tx_core_clkout
tx_avs_valid
tx_avs_ready
tx_avs_startofpackets
tx_avs_endofpackets
tx_avs_data
0,1..,19 10,11…19 …… N-10..
0,1,2,…,9
… N-10..
Lane 0
…………
STRT 0 10
N-10 END STRT 0
Lane 1
…………
STRT 1 11
N-9 END STRT 1
N-10 END IDLE IDLE N-9 END IDLE IDLE
Lane 9
…………
STRT 9 19
N-1 END STRT 9
N-1 END IDLE IDLE
Table 22.
RX MAC Signals
In this table, N represents the number of lanes set in the IP parameter
editor.
Name
Width
Direction Clock Domain
Description
rx_avs_ready
1
Input rx_core_clkout Avalon streaming signal.
When asserted, indicates that the user logic is ready to accept data.
rx_avs_data
(64N)2 (PAM4 mode)
64*N (NRZ mode)
Output
rx_core_clkout Avalon streaming signal. RX data.
rx_avs_channel
8
Output rx_core_clkout Avalon streaming signal.
The channel number for data being
received on the current cycle.
This signal is not available in Basic mode.
rx_avs_valid
1
Output rx_core_clkout Avalon streaming signal.
continued…
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Name
Width
Direction Clock Domain
Description
When asserted, indicates the RX data signal is valid.
rx_avs_startofpacket
1
Output rx_core_clkout Avalon streaming signal.
When asserted, indicates the start of an RX data packet.
Assert for only a single clock cycle for each packet.
This signal is not available in Basic mode.
rx_avs_endofpacket
1
Output rx_core_clkout Avalon streaming signal.
When asserted, indicates the end of an RX data packet.
Assert for only a single clock cycle for each packet.
This signal is not available in Basic mode.
rx_avs_empty
5
Output rx_core_clkout Avalon streaming signal.
Indicates the number of non-valid words in the final burst of the RX data.
This signal is not available in Basic mode.
rx_num_valid_bytes_eob
4
Output
rx_core_clkout Indicates the number of valid bytes in the last word of the
final burst.
This signal is not available in Basic mode.
rx_is_usr_cmd
1
Output rx_core_clkout When asserted, this signal initiate a user-
defined information cycle.
Assert this signal at the same clock cycle as tx_startofpacket assertion.
This signal is not available in Basic mode.
rx_link_up
1
Output rx_core_clkout When asserted, indicates the RX data link
is ready for data reception.
rx_link_reinit
1
Input rx_core_clkout When asserted, this signal initiates lanes
re-alignment.
If you disable Enable Auto Alignment, assert this signal for one clock cycle to trigger the MAC to re-align the lanes. If the Enable Auto Alignment is set, the MAC re-align the lanes automatically.
Do not assert this signal when Enable Auto Alignment is set.
rx_error
(N22)+3 (PAM4 mode)
(N2)3 (NRZ mode)
Output
rx_core_clkout
When asserted, indicates error conditions occur in the RX datapath.
· [(N*2+2):N+3] = Indicates PCS error for specific lane.
· [N+2] = Indicates alignment error. Reinitialize lane alignment if this bit
is asserted.
· [N+1]= Indicates data is forwarded to the user logic when user logic is not
ready.
· [N] = Indicates loss of alignment.
· [(N-1):0] = Indicates the data contains CRC error.
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6.4. Transceiver Reconfiguration Signals
Table 23.
PCS Reconfiguration Signals
In this table, N represents the number of lanes set in the IP parameter
editor.
Name
Width
Direction Clock Domain
Description
reconfig_sl_read
1
Input reconfigsl PCS reconfiguration read command
clk
signals.
reconfig_sl_write
1
Input reconfigsl PCS reconfiguration write
clk
command signals.
reconfig_sl_address
14 bits + clogb2N
Input
reconfigsl clk
Specifies PCS reconfiguration Avalon memory-mapped interface address in a
selected lane.
Each lane has 14 bits and the upper bits refers to the lane offset.
Example, for a 4-lane NRZ/PAM4 design, with reconfig_sl_address[13:0]
referring to the address value:
· reconfig_sl_address[15:1 4] set to 00 = address for lane 0.
· reconfig_sl_address[15:1 4] set to 01 = address for lane 1.
· reconfig_sl_address[15:1 4] set to 10 = address for lane 2.
· reconfig_sl_address[15:1 4] set to 11 = address for lane 3.
reconfig_sl_readdata
32
Output reconfigsl Specifies PCS reconfiguration data
clk
to be read by a ready cycle in a
selected lane.
reconfig_sl_waitrequest
1
Output reconfigsl Represents PCS reconfiguration
clk
Avalon memory-mapped interface
stalling signal in a selected lane.
reconfig_sl_writedata
32
Input reconfigsl Specifies PCS reconfiguration data
clk
to be written on a write cycle in a
selected lane.
reconfig_sl_readdata_vali
1
d
Output
reconfigsl Specifies PCS reconfiguration
clk
received data is valid in a selected
lane.
Table 24.
F-Tile Hard IP Reconfiguration Signals
In this table, N represents the number of lanes set in the IP parameter
editor.
Name
Width
Direction Clock Domain
Description
reconfig_read
1
Input reconfig_clk PMA reconfiguration read
command signals.
reconfig_write
1
Input reconfig_clk PMA reconfiguration write
command signals.
reconfig_address
18 bits + clog2bN
Input
reconfig_clk
Specifies PMA Avalon memorymapped interface address in a selected lane.
continued…
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Name
reconfig_readdata reconfig_waitrequest reconfig_writedata
reconfig_readdatavalid
Width
32 1 32 1
Direction Clock Domain
Description
In both PAM4 ad NRZ modes, each lane has 18 bits and the remaining upper bits
refers to the lane offset.
Example, for a 4-lane design:
· reconfig_address[19:18] set to 00 = address for lane 0.
· reconfig_address[19:18] set to 01 = address for lane 1.
· reconfig_address[19:18] set to 10 = address for lane 2.
· reconfig_address[19:18] set to 11 = address for lane 3.
Output
reconfig_clk Specifies PMA data to be read by a ready cycle in a selected lane.
Output
reconfig_clk Represents PMA Avalon memorymapped interface stalling signal in a selected lane.
Input
reconfig_clk Specifies PMA data to be written on a write cycle in a selected lane.
Output
reconfig_clk Specifies PMA reconfiguration received data is valid in a selected lane.
6.5. PMA Signals
Table 25.
PMA Signals
In this table, N represents the number of lanes set in the IP parameter
editor.
Name
Width
Direction Clock Domain
Description
phy_tx_lanes_stable
N*2 (PAM4 mode)
N (NRZ mode)
Output
Asynchronous When asserted, indicates TX datapath is ready to send data.
tx_pll_locked
N*2 (PAM4 mode)
N (NRZ mode)
Output
Asynchronous When asserted, indicates the TX PLL has achieved lock status.
phy_ehip_ready
N*2 (PAM4 mode)
N (NRZ mode)
Output
Asynchronous
When asserted, indicates that the custom PCS has completed internal
initialization and ready for transmission.
This signal asserts after tx_pcs_fec_phy_reset_n and tx_pcs_fec_phy_reset_nare
deasserted.
tx_serial_data
N
Output TX serial clock TX serial pins.
rx_serial_data
N
Input RX serial clock RX serial pins.
phy_rx_block_lock
N*2 (PAM4 mode)
N (NRZ mode)
Output
Asynchronous When asserted, indicates that the 66b block alignment has completed for the lanes.
rx_cdr_lock
N*2 (PAM4 mode)
Output
Asynchronous
When asserted, indicates that the recovered clocks are locked to data.
continued…
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Name phy_rx_pcs_ready phy_rx_hi_ber
Width
Direction Clock Domain
Description
N (NRZ mode)
N*2 (PAM4 mode)
N (NRZ mode)
Output
Asynchronous
When asserted, indicates that the RX lanes of the corresponding Ethernet channel are fully aligned and ready to receive data.
N*2 (PAM4 mode)
N (NRZ mode)
Output
Asynchronous
When asserted, indicates that the RX PCS of the corresponding Ethernet channel is in a HI BER state.
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7. Designing with F-Tile Serial Lite IV Intel FPGA IP
7.1. Reset Guidelines
Follow these reset guidelines to implement your system-level reset.
· Tie tx_pcs_fec_phy_reset_n and rx_pcs_fec_phy_reset_n signals together on
the system level in order to reset the TX and RX PCS simultaneously.
· Assert tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n,
rx_core_rst_n, and reconfig_reset signals at the same time. Refer to Reset and
Link Initialization for more information about the IP reset and initialization
sequences.
· Hold tx_pcs_fec_phy_reset_n, and rx_pcs_fec_phy_reset_n signals low, and
reconfig_reset signal high and wait for tx_reset_ack and rx_reset_ack to
properly reset the F-tile hard IP and the reconfiguration blocks.
· To achieve fast link-up between FPGA devices, reset the connected F-Tile
Serial Lite IV Intel FPGA IPs at the same time. Refer to F-Tile Serial Lite IV
Intel FPGA IP Design Example User Guide for information about monitoring the
IP TX and RX link using the toolkit.
Related Information
· Reset and Link Initialization on page 37
· F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide
7.2. Error Handling Guidelines
The following table lists the error handling guidelines for error conditions which may occur with the F-Tile Serial Lite IV Intel FPGA IP design.
Table 26. Error Condition and Handling Guidelines
Error Condition
One or more lanes cannot establish communication after a given time frame.
Guidelines
Implement a time-out system to reset the link at the application level.
A lane loses communication after communication is established.
A lane loses communication during the deskew process.
This may happen after or during the data transfer phases. Implement a link
loss detection at the application level and reset the link.
Implement link reinitialization process for the erroneous lane. You must
ensure that the board routing does not exceed 320 UI.
Loss lane alignment after all lanes have been aligned.
This may happen after or during data transfer phases. Implement a lane alignment loss detection at the application level to restart the lane alignment process.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives
IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
If an IP core version is not listed, the user guide for the previous IP core version applies.
Intel Quartus Prime Version
21.3
IP Core Version 3.0.0
User Guide F-Tile Serial Lite IV Intel® FPGA IP User Guide
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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9. Document Revision History for the F-Tile Serial Lite IV Intel FPGA IP User Guide
Document Version 2022.04.28
2021.11.16 2021.10.22 2021.08.18
Intel Quartus Prime Version
22.1
21.3 21.3 21.2
IP Version 5.0.0
3.0.0 3.0.0 2.0.0
Changes
· Updated Table: F-Tile Serial Lite IV Intel FPGA IP Features — Updated Data
Transfer description with additional FHT transceiver rate support: 58G NRZ,
58G PAM4, and 116G PAM4
· Updated Table: F-Tile Serial Lite IV Intel FPGA IP Parameter Description —
Added new parameter · System PLL reference clock frequency · Enable debug
endpoint — Updated the Values for PMA data rate — Updated parameter naming to
match GUI
· Updated the description for data transfer in Table: F-Tile Serial Lite IV
Intel FPGA IP Features.
· Renamed table name IP to F-Tile Serial Lite IV Intel FPGA IP Parameter
Description in the Parameters section for clarity.
· Updated Table: IP parameters: — Added a new parameter–RSFEC enabled on the
other Serial Lite IV Simplex IP placed at the same FGT channel(s). — Updated
the default values for Transceiver reference clock frequency.
Initial release.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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References
- 1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
- 1. Introduction to Intel® FPGA IP Cores
- 1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User...
- 1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release...
- 1. F-Tile Serial Lite IV Intel® FPGA IP Release Notes