ON Semiconductor AGB1N0CS-GEVK Demo 3 Evaluation Board User Manual

: June 16, 2024
: ON Semiconductor

Table of Contents

ON Semiconductor AGB1N0CS-GEVK Demo 3 Evaluation Board User Manual
Demo 3 Evaluation Board User’s Manual
EVAL BOARD USER’S MANUAL
AGB1N0CS−GEV
FPGA Frame Buffer
Receivers and Data Rates
HiSPi Receiver:
CCP Receiver:
Parallel Receiver:
HDMI Transmitter
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ON Semiconductor AGB1N0CS-GEVK Demo 3 Evaluation Board User Manual

Demo 3 Evaluation Board User’s Manual

Demo 3 Evaluation Board Overview
The Demo 3 Baseboard is used to connect to headboards and www.onsemi.com
interface with a host PC in order to demonstrate the features of ON Semiconductor’s image sensor products.

Features

High-Bandwidth USB 0 Interface
Altera Arria II GX FPGA
HDMIÒTransmitter
1 Gb Memory Buffer
Up to 4-Lane MIPI and HiSPi Interfaces
CCP and Parallel Interfaces
I2C Control Unit

Block Diagram

EVAL BOARD USER’S MANUAL

Figure 1. AGB1N0CS Evaluation Board

AGB1N0CS−GEV

Demo 3 Baseboard Function Overview

The Demo 3’s FPGA, Altera’s EP2AGX45DF25C4N, provides an interface between ON Semiconductor imaging sensors and the Cypress FX3 USB 3.0 controller. An
external SPI EPROM contains the programming file for the FPGA. The EPROM is configurable using the FX3 SPI master interface. The FPGA has a memory controller block that controls data from the on-board DDR3 SDRAM.

FPGA Frame Buffer

The 1Gb frame buffer using a 64Mbx16 matches data rates between the sensor and FX3 interfaces. It is sized to buffer 3 frames of a 20-Megapixel sensor. There is a triple-buffer to help minimize frame loss. The frame buffer has two principal operating modes that support either self-timed operation or direct interface to the FX3 at HDMI video output of 720p 60 or 1080p 60 frame rates. The frame buffer controller runs at 150 MHz FPGA core clock with peak available bandwidth at 750-Megapixels/second, peak input bandwidth of 400-Megapixels/second, and peak output bandwidth of 200-Megapixels/second. The frame buffer can be configured to operate as a frame capture device, with the entire buffer filled prior to sending data to the FX3 interface.

Receivers and Data Rates

The FPGA receives data through MIPI, HiSPi, CCP, and parallel interfaces. Each of these receiver blocks has an output FIFO that moves data from the receiver clock to the 150 MHz FPGA core clock.

MIPI Receiver:

The MIPI receiver handles 4 lanes of data at a maximum data rate of 768 Mbps/lane. The signal pairs use both single-ended and differential signaling with accordance to the MIPI Alliance Specification for D−PHY v.1.00.00.

HiSPi Receiver:

The HiSPi receiver supports high-speed transmission of image sensor data, operating at 1 Gbps per data lane. It is a unidirectional differential serial interface with four data lanes and one DDR clock lane. It supports Streaming−S, Streaming−SP, and Packetized SP protocols that conform to the HiSPi protocol specification v.1.50.00.

CCP Receiver:

The CCP receiver is a single-lane data interface that supports 8-, 10-, or 12-bit raw data. It operates with a maximum serial data rate of at least 640 Mbps. The receiver conforms to the SMIA CCP2 1.0 specification.

Parallel Receiver:

The parallel receiver allows asynchronous switching between driven and high-Z under pin or register control. The receiver supports 10 or 12 bits of data, running at a pixel rate of at least 125 MHz.

HDMI Transmitter

The HDMI transmitter utilizes the ADV7526 chip by Analog Devices to transmit HDMI 34-bit data to the output port. The HDMI interface supports the HDMI 1.4 standard with 12-bit deep color. It supports RGB and YCbCr digital video input. The I2C device address is 0x72 and accesses registers inside the HDMI transmitter block.