ALINX AXKU042 KINTEX UltraScale FPGA Development Board User Manual

ALINX AXKU042 KINTEX UltraScale FPGA Development Board

Version Record
Alinx Electronic Technology (Shanghai) Co., Ltd, based on the KINTEX UltraSacale series development platform for the architecture (model: AXKU042) has been officially released. In order to let you quickly understand this development platform, we have compiled this user manual.

AXKU042 adopts a core board and expansion board model, which facilitates users’ secondary development and utilization of the core board. The core board is equipped with four 1GB high-speed DDR4 SDRAM chips and two 128Mb QSPI FLASH chips. In terms of expansion board design, we have extended a variety of interfaces for users: two 10G SFP+fiber optic interfaces, 3 FMC expansion interfaces (1 HPC, 2 LPC), 1-gigabit network port, 1 UART serial port, 1 SD card interface, LED buttons, and so on. The following figure is a schematic diagram of the entire development system structure:

Through this diagram, you can see the interfaces and functions that the AXKU042 Development Board contains:

FPGA Core Board

1. FPGA chip：Xilinx KINTEX UltraSacale chip XCKU040.

2. DDR4：With four large-capacity 1GB (4 GB total) high-speed DDR4 SDRAM, can be used as data storage for FPGA, image analysis cache, and data processing;

3. QSPI FLASH two 128Mbit QSPI NOR FLASH memory chips can be used as a storage for configuration files and user data;

4. One differential crystal vibration of 200 Mhz;

5. Two diode LEDs, 1 power indicator, 1 DONE configuration indicator.
   Development Board

6. Two SFP and optical fiber communication interfaces， each fiber optical data communication receives and transmits at speeds of up to 16.3 Gb/s.

7. One PCIE3.0 X8 interface， endpoint mode， is used to communicate data between PC and PCIE.

8. USB Uart interface， used for communication with the computer for user debugging. The serial port chip adopts the USB-UAR chip of Silicon Labs CP2102GM, and the USB interface adopts the MINI USB interface.

9. 1 channel 10/100M/1000MEthernet RJ45 interface for Ethernet data exchange with computers or other network devices. The network interface chip uses Micrel’s KSZ9031 industrial-grade GPHY chip.

10. 3 standard FMC expansion port, including 2 LPC FMC expansion ports and 1 HPC FMC expansion port, which can be connected to various FMC modules of Xilinx or Alinx(HDMI input and output modules, binocular camera modules, high-speed AD modules, etc. )

11. 1Micro SD card holder, used to store operating system image and file system.

12. 2 SMA external interfaces, the pins are connected to the transceiver for external high-speed input and output signals.

13. Onboard a temperature and humidity sensor chip LM75 for detecting the temperature and humidity of the environment around the board.

14. One EEPROM is used for IIC bus communication and storage of some customer-defined information.

15. A 10-pin 2.54mm spacing standard JTAG port for FPGA program download and debugging. Users can debug and download FPGAs through the XILINX downloader.

16. Two 156.25Mhz differential crystal onboard provides a reference clock for the transceiver.

17. LEDs,1 power indicator, 4 user indicators,1 pair of panel indicator.

Part 1 AXKU042 Development Board

Part 1.1: FPGA Development Board Introduction

AXKU042(core board model, the same below) FPGA core board, FPGA chip is based on XCKU040-2FFVA1156I of XILINX company XC7K325 series.This core board uses four Micron’s MT40A512M16LY-062EIT, each of which has a capacity of 1GB, the total capacity is 4 GB. In addition, the FPGA chip configuration uses two128MBit QSPI FLASH, used as FPGA data storage and system files. The six board-to-board connectors of the core board AXKU042 expand 359 IOs, Of which 104 IO levels of BANK64 and BANK65 is 3.3V, while other IOs levels of bank is 1.8V; In addition,the core board also extended 20 pairs of high-speed Transceiver GTH interfaces. For users who need a lot of IO, this core board will be a good choice. And IO connection part, the line between the chip and the interface have been done the equal length and differential processing, and the core board size is only 80 * 60 (mm), very suitable for secondary development.

Part 1.2: FPGA Chip
The FPGA development board uses Xilinx’s KINTEX UltraScale chip, model number XCKU040-2FFVA1156I. The speed class is 2 and the temperature class is industrial. This model is a FFVA1156 package with 1156 pins and a 1.0mm pitch. The chip naming rules for Xilinx KINTEX UltraScale FPGA are shown in Figure 1-2-1 below:

Figure 1-2-1 The Chip Model Definition of KINTEX UltraScale Series The main parameters of AXKU042 are as follows：

Part 1.3: DDR4 DRAM
The AXKU042 FPGA development board is equipped with four Micron 1GB DDR4 chips, model MT40A512M16LY-062EIT. Four DDR4 SDRAMs form a 64-bit bus width. Because four DDR4 chips are connected to the FPGA, the DDR4 SDRAM can run at speeds up to 1200MHz, and four DDR4 memory systems are directly connected to the BANK44, BANK45, and BANK46 interfaces of the FPGA. The specific configuration of DDR4 SDRAM is shown in Table 3-1.

Figure 3-1 DDR4 SDRAM Configuration

The hardware design of DDR4 requires strict consideration of signal integrity. We have fully considered the matching resistor/terminal resistance, trace impedance control, and trace length control in circuit design and PCB design to ensure
the high-speed and stable operation of DDR3. The hardware connection mode of FPGA and DDR4 DRAM is shown in Figure 1-3-1:

Figure1-3-1 DDR4 DRAM schematic diagram 4 pieces DDR4 DRAM pin assignments

Part 1.4: QSPI Flash

The AXKU042 FPGA development board is equipped with two 128MBit Quad-SPI FLASH, and the model is N25Q128A, which uses the 3.3V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, it can store FPGA configuration Bin files and other user data files in use. The specific models and related parameters of QSPI FLASH are shown in Figure 4-1.

Figure 4-1 QSPI Flash Specification

QSPI FLASH is connected to the dedicated pins of BANK0 of the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data signals are connected to D00~D03 and FCS pins. Figure 4-2 shows the hardware connection of QSPI Flash and FPGA Chip.

QSPI Flash pin assignments

Part 1.5: Clock configuration

200Mhz differential clock source A differential 200MHz clock source is provided on the FPGA development board to provide the system clock to the FPGA. The crystal differential output is connected to the FPGA BANK45, which can be used to drive the DDR controller operating clock and other user logic in the FPGA. The schematic diagram of the clock source is shown in Figure 1-5-1.

System Clock pin assignments

There are two red LEDs on the AXKU042 FPGA development board, one of which is the power indicator (PWR), and one is a DONE indicator. When the AXKU042 FPGA board is powered on, the power indicator and DONE indicator will light up; when the AXKU042 FPGA is configured, the DONE LED will light up; The LEDs hardware connection is shown in Figure 1-6-1.

Part 1.7: Power Supply
The power input voltage of the AXKU042 FPGA development board is DC12V, and the power supply is provided by the carrier board. The power supply design diagram on the board is shown in Figure 1-7-1 below:

Figure 1-7-1 Power Supply schematic diagram
+12V generates+0.95V FPGA core power through the DCDC power chipcMYMGK1R820ERSR. The output current of the MYMGK1R820FRSR is as high as 20A, which far meets the core voltage current demand. Then + 12V power supply through the DCDC chip ETA1471 is generated four power supplies:+1.2V,+1.8V+3.3V, and MGTAVTT. The MGTAVCC used in the GTX transceiver is generated by the DCDC chip ETA8156, and an LDO chip SPX3819-1-8 is used to generate the auxiliary power supply of the GTX+1.8V. The VTT and VREF voltages of DDR4 are generated by TPS51200.

Part 1.8: Size Dimension

Part 1.9: Board to Board Connectors pin assignment The core board expands a total of six high-speed expansion connectors, and uses four 120-pin inter- board connectors (J1,J3, J4,J5) and the two 80-pin inter-board connectors (J2,J6) to connect to the carrier board. The connector uses Panasonic’s AXK5A2137YG and AXK580137YG. The connectors of the corresponding carrier plates are AXK6A2337YG and AXK680337YG. J1 is connected to the IO of BANK66 and BANK68, and the power is 1.8V.

Pin assignment of J1 connector
J2 connector 80 Pin, connect the high-speed differential signal of transceiver BANK226~228.

J1 Pin| Signal Name| FPGA Pin| J1 Pin| Signal Name| FPGA Pin
---|---|---|---|---|---
1| B66_L3_N| C8| 2| B66_L1_N| E8
3| B66_L3_P| D8| 4| B66_L1_P| F8
5| B66_L7_N| K8| 6| B66_L2_N| A9
7| B66_L7_P| L8| 8| B66_L2_P| B9
J1 Pin| Signal Name| FPGA Pin| J1 Pin| Signal Name| FPGA Pin
---|---|---|---|---|---
1| B66_L3_N| C8| 2| B66_L1_N| E8
3| B66_L3_P| D8| 4| B66_L1_P| F8
5| B66_L7_N| K8| 6| B66_L2_N| A9
7| B66_L7_P| L8| 8| B66_L2_P| B9
79| GND| –| 80| GND| –
---|---|---|---|---|---
81| B68_L16_N| F19| 82| B68_L10_N| D18
83| B68_L16_P| G19| 84| B68_L10_P| D19
85| B68_L18_N| H18| 86| B68_L1_N| A14
87| B68_L18_P| H19| 88| B68_L1_P| B14
89| GND| –| 90| GND| –
91| B68_L22_N| J18| 92| B68_L3_N| A15
93| B68_L22_P| J19| 94| B68_L3_P| B15
95| B68_L24_N| L18| 96| B68_L5_N| B16
97| B68_L24_P| L19| 98| B68_L5_P| B17
99| GND| –| 100| GND| –
101| B68_L13_N| G16| 102| B68_L7_N| C14
103| B68_L13_P| G17| 104| B68_L7_P| D14
105| B68_L14_N| F17| 106| B68_L6_N| C17
107| B68_L14_P| F18| 108| B68_L6_P| C18
109| GND| –| 110| GND| –
111| B68_L12_N| E17| 112| B68_L2_N| A18
113| B68_L12_P| E18| 114| B68_L2_P| A19
115| B68_L17_N| H16| 116| B68_L4_N| B19
117| B68_L17_P| H17| 118| B68_L4_P| C19
119| GND| –| 120| GND| –

Pin assignment of J2 connector
J3 is the high-speed difference signal of the transceiver BANK224~226 and the partial signal of BANK64, BANK65

J2 Pin| Signal Name| FPGA Pin| J2 Pin| Signal Name| FPGA Pin
---|---|---|---|---|---
1| GND| –| 2| GND| –
3| 226_TX2_N| U3| 4| 226_RX2_N| T1
5| 226_TX2_P| U4| 6| 226_RX2_P| T2
7| GND| –| 8| GND| –
9| 226_TX3_N| R3| 10| 226_RX3_N| P1
11| 226_TX3_P| R4| 12| 226_RX3_P| P2
13| GND| –| 14| GND| –
15| 226_CLK1_N| T5| 16| 226_CLK0_N| V5
17| 226_CLK1_P| T6| 18| 226_CLK0_P| V6
19| GND| –| 20| GND| –
21| 227_TX0_P| N4| 22| 227_RX0_P| M2
---|---|---|---|---|---
23| 227_TX0_N| N3| 24| 227_RX0_N| M1
25| GND| –| 26| GND| –
27| 227_TX1_P| L4| 28| 227_RX1_P| K2
29| 227_TX1_N| L3| 30| 227_RX1_N| K1
31| GND| –| 32| GND| –
33| 227_TX2_P| J4| 34| 227_RX2_P| H2
35| 227_TX2_N| J3| 36| 227_RX2_N| H1
37| GND| –| 38| GND| –
39| 227_TX3_P| G4| 40| 227_RX3_P| F2
41| 227_TX3_N| G3| 42| 227_RX3_N| F1
43| GND| –| 44| GND| –
45| 227_CLK1_P| M6| 46| 227_CLK0_P| P6
47| 227_CLK1_N| M5| 48| 227_CLK0_N| P5
49| GND| –| 50| GND| –
51| 228_TX0_P| F6| 52| 228_RX0_P| E4
53| 228_TX0_N| F5| 54| 228_RX0_N| E3
55| GND| –| 56| GND| –
57| 228_TX1_P| D6| 58| 228_RX1_P| D2
59| 228_TX1_N| D5| 60| 228_RX1_N| D1
61| GND| –| 62| GND| –
63| 228_TX2_P| C4| 64| 228_RX2_P| B2
65| 228_TX2_N| C3| 66| 228_RX2_N| B1
67| GND| –| 68| GND| –
69| 228_TX3_P| B6| 70| 228_RX3_P| A4
71| 228_TX3_N| B5| 72| 228_RX3_N| A3
73| GND| –| 74| GND| –
75| 228_CLK1_P| H6| 76| 228_CLK0_P| K6
77| 228_CLK1_N| H5| 78| 228_CLK0_N| K5
79| GND| –| 80| GND| –

Pin assignment of J3 connector

J3 Pin| Signal Name| FPGA Pin| J3 Pin| Signal Name| FPGA Pin
---|---|---|---|---|---
1| B64_L7_N| AF13| 2| B64_L21_N| AL9
3| B64_L7_P| AE13| 4| B64_L21_P| AK10
---|---|---|---|---|---
5| B64_L11_N| AH12| 6| B64_L24_N| AL8
7| B64_L11_P| AG12| 8| B64_L24_P| AK8
9| GND| L7| 10| GND| –
11| B64_L9_N| AF12| 12| B64_L12_N| AH11
13| B64_L9_P| AE12| 14| B64_L12_P| AG11
15| B64_L13_N| AG10| 16| B64_L14_N| AG9
17| B64_L13_P| AF10| 18| B64_L14_P| AF9
19| GND| L7| 20| GND| –
21| B64_L10_N| AE11| 22| B64_L15_N| AF8
23| B64_L10_P| AD11| 24| B64_L15_P| AE8
25| B64_L18_N| AH8| 26| B64_L16_N| AE10
27| B64_L18_P| AH9| 28| B64_L16_P| AD10
29| GND| L7| 30| GND| –
31| B64_L17_N| AD8| 32| FPGA_TCK| AC9
33| B64_L17_P| AD9| 34| FPGA_TDO| U9
35| B64_L23_N| AJ8| 36| FPGA_TMS| W9
37| B64_L23_P| AJ9| 38| FPGA_TDI| V9
39| GND| L7| 40| GND| –
41| B65_T0U| H23| 42| B66_T3U| E12
43| B65_T3U| K22| 44| B66_T2U| F12
45| B65_T1U| N23| 46| B66_T1U| L9
47| B65_T2U| N27| 48| NC| –
49| GND| L7| 50| GND| –
51| 224_TX0_N| AN3| 52| 224_RX0_N| AP1
53| 224_TX0_P| AN4| 54| 224_RX0_P| AP2
55| GND| L7| 56| GND| –
57| 224_TX1_N| AM5| 58| 224_RX1_N| AM1
59| 224_TX1_P| AM6| 60| 224_RX1_P| AM2
61| GND| L7| 62| GND| –
63| 224_TX2_N| AL3| 64| 224_RX2_N| AK1
65| 224_TX2_P| AL4| 66| 224_RX2_P| AK2
67| GND| L7| 68| GND| –
69| 224_TX3_N| AK5| 70| 224_RX3_N| AJ3
71| 224_TX3_P| AK6| 72| 224_RX3_P| AJ4
73| GND| L7| 74| GND| –
---|---|---|---|---|---
75| 224_CLK1_N| AD5| 76| 224_CLK0_N| AF5
77| 224_CLK1_P| AD6| 78| 224_CLK0_P| AF6
79| GND| L7| 80| GND| –
81| 225_TX0_N| AH5| 82| 225_RX0_N| AH1
83| 225_TX0_P| AH6| 84| 225_RX0_P| AH2
85| GND| L7| 86| GND| –
87| 225_TX1_N| AG3| 88| 225_RX1_N| AF1
89| 225_TX1_P| AG4| 90| 225_RX1_P| AF2
91| GND| L7| 92| GND| –
93| 225_TX2_N| AE3| 94| 225_RX2_N| AD1
95| 225_TX2_P| AE4| 96| 225_RX2_P| AD2
97| GND| L7| 98| GND| –
99| 225_TX3_N| AC3| 100| 225_RX3_N| AB1
101| 225_TX3_P| AC4| 102| 225_RX3_P| AB2
103| GND| L7| 104| GND| –
105| 225_CLK1_N| Y5| 106| 225_CLK0_N| AB5
107| 225_CLK1_P| Y6| 108| 225_CLK0_P| AB6
109| GND| L7| 110| GND| –
111| 226_TX0_N| AA3| 112| 226_RX0_N| Y1
113| 226_TX0_P| AA4| 114| 226_RX0_P| Y2
115| GND| L7| 116| GND| –
117| 226_TX1_N| W3| 118| 226_RX1_N| V1
119| 226_TX1_P| W4| 120| 226_RX1_P| V2

J4 connects the signal of BANK48 and the partial signal of BANK64. Pin assignment of J4 connector

J4 Pin| Signal Name| FPGA Pin| J4 Pin| Signal Name| FPGA Pin
---|---|---|---|---|---
1| B48_L8_N| AG34| 2| B48_T2U| AA33
3| B48_L8_P| AF33| 4| B48_T1U| AE31
5| B48_L7_N| AG32| 6| B48_T3U| V32
7| B48_L7_P| AG31| 8| B47_T3U| U29
9| GND| –| 10| GND| –
11| B48_L10_N| AF34| 12| B48_L18_N| AD33
13| B48_L10_P| AE33| 14| B48_L18_P| AC33
J4 Pin| Signal Name| FPGA Pin| J4 Pin| Signal Name| FPGA Pin
---|---|---|---|---|---
1| B48_L8_N| AG34| 2| B48_T2U| AA33
3| B48_L8_P| AF33| 4| B48_T1U| AE31
5| B48_L7_N| AG32| 6| B48_T3U| V32
7| B48_L7_P| AG31| 8| B47_T3U| U29
9| GND| –| 10| GND| –
11| B48_L10_N| AF34| 12| B48_L18_N| AD33
13| B48_L10_P| AE33| 14| B48_L18_P| AC33
85| NC| –| 86| NC| –
---|---|---|---|---|---
87| NC| –| 88| POWER_PG| –
89| GND| –| 90| GND| –
91| B64_L8_N| AJ13| 92| B64_T1U| AJ11
93| B64_L8_P| AH13| 94| B64_T3U| AM9
95| B64_L6_N| AL13| 96| B64_T0U| AK11
97| B64_L6_P| AK13| 98| B64_T2U| AJ10
99| GND| –| 100| GND| –
101| B64_L1_N| AP10| 102| B64_L2_N| AP13
103| B64_L1_P| AP11| 104| B64_L2_P| AN13
105| B64_L4_N| AN12| 106| B64_L22_N| AP8
107| B64_L4_P| AM12| 108| B64_L22_P| AN8
109| GND| –| 110| GND| –
111| B64_L20_N| AP9| 112| B64_L19_N| AM10
113| B64_L20_P| AN9| 114| B64_L19_P| AL10
115| B64_L3_N| AN11| 116| B64_L5_N| AL12
117| B64_L3_P| AM11| 118| B64_L5_P| AK12
119| GND| –| 120| GND| –

J5 connects the signal of BANK47 and the partial signal of BANK65. Pin assignment of J5 connector

J5 Pin| Signal Name| FPGA Pin| J5 Pin| Signal Name| FPGA Pin
---|---|---|---|---|---
1| B65_L10_N| K23| 2| NC| –
3| B65_L10_P| L22| 4| NC| –
5| B65_L6_N| H24| 6| B65_L23_N| M21
7| B65_L6_P| J23| 8| B65_L23_P| N21
9| GND| L7| 10| GND| –
11| B65_L19_N| M22| 12| NC| –
13| B65_L19_P| N22| 14| B65_L2_P| G25
15| B65_L9_N| K25| 16| B65_L1_N| G27
17| B65_L9_P| L25| 18| B65_L1_P| H27
19| GND| L7| 20| GND| –
21| B65_L24_N| K21| 22| B65_L5_N| H26
23| B65_L24_P| K20| 24| B65_L5_P| J26
25| B65_L12_N| M24| 26| B65_L4_N| J25
27| B65_L12_P| N24| 28| B65_L4_P| J24
---|---|---|---|---|---
29| GND| L7| 30| GND| –
31| B65_L20_N| P21| 32| B65_L3_N| K27
33| B65_L20_P| P20| 34| B65_L3_P| K26
35| B65_L7_N| L27| 36| B65_L11_N| M26
37| B65_L7_P| M27| 38| B65_L11_P| M25
39| GND| L7| 40| GND| –
41| B65_L13_N| N26| 42| B65_L18_N| P23
43| B65_L13_P| P26| 44| B65_L18_P| R23
45| B65_L14_N| P25| 46| B65_L15_N| R27
47| B65_L14_P| P24| 48| B65_L15_P| T27
49| GND| –| 50| GND| –
51| B65_L8_N| L24| 52| B65_L17_N| R26
53| B65_L8_P| L23| 54| B65_L17_P| R25
55| NC| –| 56| B65_L16_N| T25
57| NC| –| 58| B65_L16_P| T24
59| GND| L7| 60| GND| –
61| B47_L11_N| AA23| 62| B47_L19_N| V28
63| B47_L11_P| Y23| 64| B47_L19_P| V27
65| B47_L14_N| Y25| 66| B47_L22_N| U27
67| B47_L14_P| W25| 68| B47_L22_P| U26
69| GND| –| 70| GND| –
71| B47_L7_N| AB22| 72| B47_L20_N| U25
73| B47_L7_P| AA22| 74| B47_L20_P| U24
75| B47_L21_N| Y28| 76| B47_L17_N| T23
77| B47_L21_P| W28| 78| B47_L17_P| T22
79| GND| –| 80| GND| –
81| B47_L3_N| AC24| 82| B47_L15_N| U22
83| B47_L3_P| AB24| 84| B47_L15_P| U21
85| B47_L23_N| W29| 86| B47_L24_N| W26
87| B47_L23_P| V29| 88| B47_L24_P| V26
89| GND| –| 90| GND| –
91| B47_L10_N| AC21| 92| B47_L13_N| W24
93| B47_L10_P| AB21| 94| B47_L13_P| W23
95| B47_L5_N| AB27| 96| B47_L1_N| Y27
97| B47_L5_P| AA27| 98| B47_L1_P| Y26
---|---|---|---|---|---
99| GND| –| 100| GND| –
101| B47_L9_N| AB20| 102| B47_L12_N| AA25
103| B47_L9_P| AA20| 104| B47_L12_P| AA24
105| B47_L4_N| AC27| 106| B47_L6_N| AB26
107| B47_L4_P| AC26| 108| B47_L6_P| AB25
109| GND| –| 110| GND| –
111| B47_L8_N| AC23| 112| B47_L16_N| V23
113| B47_L8_P| AC22| 114| B47_L16_P| V22
115| B47_L2_N| AD26| 116| B47_L18_N| W21
117| B47_L2_P| AD25| 118| B47_L18_P| V21
119| GND| –| 120| GND| –

J6 connects 12V power, the signal of BANK66, and the partial signal of BANK68. Pin assignment of J6 connector

J6 Pin| Signal Name| FPGA Pin| J6 Pin| Signal Name| FPGA Pin
---|---|---|---|---|---
1| +12V| –| 2| +12V| –
3| +12V| –| 4| +12V| –
5| +12V| –| 6| +12V| –
7| +12V| –| 8| +12V| –
9| +12V| –| 10| +12V| –
11| GND| –| 12| GND| –
13| B67_L17_N| A20| 14| B67_L8_N| A25
15| B67_L17_P| B20| 16| B67_L8_P| B25
17| B67_L16_N| C22| 18| B67_L6_N| A28
19| B67_L16_P| C21| 20| B67_L6_P| A27
21| GND| –| 22| GND| –
23| B67_L15_N| B22| 24| B67_L13_N| C23
25| B67_L15_P| B21| 26| B67_L13_P| D23
27| B67_L11_N| D25| 28| B67_L12_N| C24
29| B67_L11_P| E25| 30| B67_L12_P| D24
31| GND| –| 32| GND| –
33| B67_L18_N| D21| 34| B67_L4_N| A29
35| B67_L18_P| D20| 36| B67_L4_P| B29
37| B67_L20_N| E21| 38| B67_L2_N| B27
39| B67_L20_P| E20| 40| B67_L2_P| C27
---|---|---|---|---|---
41| GND| –| 42| GND| –
43| B67_L14_N| E23| 44| B67_L1_N| E27
45| B67_L14_P| E22| 46| B67_L1_P| F27
47| B67_L22_N| F20| 48| B67_L10_N| A24
49| B67_L22_P| G20| 50| B67_L10_P| B24
51| GND| –| 52| GND| –
53| B67_L19_N| F25| 54| B67_L9_N| B26
55| B67_L19_P| G24| 56| B67_L9_P| C26
57| B67_L24_N| G21| 58| B67_L5_N| C28
59| B67_L24_P| H21| 60| B67_L5_P| D28
61| GND| –| 62| GND| –
63| B67_L21_N| F24| 64| B67_L3_N| D29
65| B67_L21_P| F23| 66| B67_L3_P| E28
67| B67_L23_N| F22| 68| B67_L7_N| D26
69| B67_L23_P| G22| 70| B67_L7_P| E26
71| GND| –| 72| GND| –
73| B68_T1U| C16| 74| B67_T1U| A23
75| B68_T2U| H14| 76| B67_T2U| A22
77| B68_T3U| L17| 78| B67_T3U| H22
79| NC| –| 80| NC| –

Part 2: Carrier Board

Part 2.1: Introduction

Through the previous function introduction, you can understand the function of the carrier board part.

• 2-channel fiber interface
• 1-channel PCIEx8 interface
• 1-channel USB UART interface
• 1-channel Ethernet RJ45 interface
• 3-Channel FMC interface
• 1-channel Micro SD card slot
• 2-channel SMA interface
• EEPROM, temperature and humidity sensor
• JTAG debugging interface
• 7 LED lights
• 2 Keys

Part 2.2: PCIE X8 interface
AXKU042 development board is equipped with a PCIe3.0 x 8 interface for connecting 8 pairs of transceivers to the PCIEx8 gold finger, it can realize the data communication of PCIEex8, PCIEex4, PCIex2, and PCIex1. The transmit and receive signals of the PCIe interface are directly connected to the GTP transceiver of the FPGA. The eight channels of TX and RX signals are connected to the FPGA in differential signals, and the single-channel communication rate can be up to 8Gbps bandwidth. The design diagram of the PCIe interface of the AXKU042 FPGA development board is shown in Figure 2-2-1, where the TX transmit signal and the reference clock CLK signal are connected in AC coupled mode.

PCIe x8 Interface Pin Assignment

Signal Name| FPGA Pin Name| Pin

Number

| Description
---|---|---|---
PCIE_RX0_N| MGTHRXN3_225| AB1| PCIE channel 0 Data Transmit Negative
PCIE_RX0_P| MGTHRXP3_225| AB2| PCIE channel 0 Data Transmit Positive
PCIE_RX1_N| MGTHRXN2_225| AD1| PCIE channel 1 Data Transmit Negative
PCIE_RX1_P| MGTHRXP2_225| AD2| PCIE channel 1 Data Transmit Positive
PCIE_RX2_N| MGTHRXN1_225| AF1| PCIE channel 2 Data Transmit Negative
PCIE_RX2_P| MGTHRXP1_225| AF2| PCIE channel 2 Data Transmit Positive
PCIE_RX3_N| MGTHRXN0_225| AH1| PCIE channel 3 Data Transmit Negative
PCIE_RX3_P| MGTHRXP0_225| AH2| PCIE channel 3 Data Transmit Positive
PCIE_RX4_N| MGTHRXN3_224| AJ3| PCIE channel 4 Data Transmit Negative
PCIE_RX4_P| MGTHRXP3_224| AJ4| PCIE channel 4 Data Transmit Positive
PCIE_RX5_N| MGTHRXN2_224| AK1| PCIE channel 5 Data Transmit Negative
PCIE_RX5_P| MGTHRXP2_224| AK2| PCIE channel 5 Data Transmit Positive
PCIE_RX6_N| MGTHRXN1_224| AM1| PCIE channel 6 Data Transmit Negative
PCIE_RX6_P| MGTHRXP1_224| AM2| PCIE channel 6 Data Transmit Positive
PCIE_RX7_N| MGTHRXN0_224| AP1| PCIE channel 7 Data Transmit Negative
PCIE_RX7_P| MGTHRXP0_224| AP2| PCIE channel 7 Data Transmit Positive
PCIE_TX0_N| MGTHTXN3_225| AC3| PCIE channel 0 Data Transmit Negative
PCIE_TX0_P| MGTHTXP3_225| AC4| PCIE channel 0 Data Transmit Positive
PCIE_TX1_N| MGTHTXN2_225| AE3| PCIE channel 1 Data Transmit Negative
PCIE_TX1_P| MGTHTXP2_225| AE4| PCIE channel 1 Data Transmit Positive
PCIE_TX2_N| MGTHTXN1_225| AG3| PCIE channel 2 Data Transmit Negative
PCIE_TX2_P| MGTHTXP1_225| AG4| PCIE channel 2 Data Transmit Positive
PCIE_TX3_N| MGTHTXN0_225| AH5| PCIE channel 3 Data Transmit Negative
PCIE_TX3_P| MGTHTXP0_225| AH6| PCIE channel 3 Data Transmit Positive
PCIE_TX4_N| MGTHTXN3_224| AK5| PCIE channel 4 Data Transmit Negative
PCIE_TX4_P| MGTHTXP3_224| AK6| PCIE channel 4 Data Transmit Positive
PCIE_TX5_N| MGTHTXN2_224| AL3| PCIE channel 5 Data Transmit Negative
PCIE_TX5_P| MGTHTXP2_224| AL4| PCIE channel 5 Data Transmit Positive
PCIE_TX6_N| MGTHTXN1_224| AM5| PCIE channel 6 Data Transmit Negative
PCIE_TX6_P| MGTHTXP1_224| AM6| PCIE channel 6 Data Transmit Positive
PCIE_TX7_N| MGTHTXN0_224| AN3| PCIE channel 7 Data Transmit Negative
PCIE_TX7_P| MGTHTXP0_224| AN4| PCIE channel 7 Data Transmit Positive
PCIE_CLK_N| MGTREFCLK0N_225| AB5| PCIE channel Reference Clock Negative
PCIE_CLK_P| MGTREFCLK0P_225| AB6| PCIE channel Reference Clock Positive
PCIE_PERST| IO_T3U_N12_PERSTN0_65| K22| PCIE card Reset Signal

Part 2.3: SFP+ Optical fiber interface

AXKU042 FPGA development board has a two SFP interface. The Users can buy SFP optical modules (1.25G, 2.5G, 10G optical modules on the market) and insert them into these 2 optical fiber interfaces for optical fiber data communication. The 2 optical fiber interfaces are respectively connected with 2 RX/TX of FPGA BANK226 GTH transceiver. Both the TX signal and the RX signal are connected to the FPGA and the optical module through a DC blocking capacitor in a differential signal mode, and the data rate of each TX transmission and RX reception is as high as 16.3Gb/s. The reference clock of the GXH transceiver of BANK226 is provided by a differential crystal oscillator 156.25M.

The design diagram of FPGA and SFP fiber is shown in Figure 2-3-1 below

Figure 2-3-1 SFP Fiber schematic diagram
The 1st fiber interface FPGA pin assignment is as follows:

received

The 2nd fiber interface FPGA pin assignment is as follows

received

Part 2.4: Gigabit Ethernet Interface There is 1 Gigabit Ethernet port on the AXKU042 FPGA Development board. The GPHY chip uses Micrel’s KSZ9031RNX Ethernet PHY chip to provide users with network communication services. The KSZ9031RNX chip supports 10/100/1000 Mbps network transmission rate and communicates with the MAC layer of the system through the RGMII interface. KSZ9031RNX supports MDI/MDX adaptation, various speed adaptations, Master/Slave adaptation, and supports MDIO bus for PHY register management. When the KSZ9031RNX is powered on, it will detect the level status of some specific IOs to determine its own operating mode. Table 3-5-1 describes the default settings after the GPHY chip is powered on.

configuration

| 10/100/1000 adaptive, compatible

with full-duplex, half-duplex

When the network is connected to Gigabit Ethernet, the data transmission of FPGA chip and PHY chip KSZ9031RNX is communicated through the RGMII bus, the transmission clock is 125Mhz, and the data is sampled on the rising edge and falling samples of the clock. When the network is connected to 100M Ethernet, the data transmission of the FPGA chip and PHY chip KSZ9031RNX is communicated through the RMII bus, and the transmission clock is 25Mhz. Data is sampled on the rising edge and falling samples of the clock. Ethernet PHY chip connection diagram as shown in Figure 2-4-1:

Figure 2-4-1 schematic diagram
The Gigabit Ethernet interface pin assignments are as follows:

Part 2.5: USB to Serial Port
The AXKU042 FPGA development board is equipped with a UART to USB interface for serial communication and debugging of the development board. The conversion chip uses the USB-UAR chip of Silicon Labs CP2102GM. The CP2102 serial chip and the FPGA are connected by a level-shifting chip to adapt to different FPGA BANK voltages. The USB interface uses the MINI USB interface, which can be connected to the USB port of the upper PC for serial data communication on the FPGA development board with a USB cable. The schematic diagram of the USB Uart circuit design is shown below in Table 6-1:

Figure 2-5-1 USB to serial port schematic diagram USB to serial port pin assignment

Signal Name| FPGA Pin Name| Pin

Number

| Description
---|---|---|---
UART_RXD| B64_T1U| AJ11| Uart Data Input
UART_TXD| B64_T3U| AM9| Uart Data Output

Part 2.6: FMC Expansion Port
The AXKU042 FPGA development board comes with two standard FMC LPC expansion ports and one standard FMC HPC expansion port that can be connected to various FMC modules of XILINX or ALINX (HDMI input and output modules, binocular camera modules, high-speed AD modules, etc.). The LPC FMC1 expansion port has 36 pairs of differential signals, which are respectively connected to the IO of BANK47 and BANK48 of the FPGA chip. The IO level of BANK47 and BANK48 is 1.8V and cannot be modified.

The 1-pair speed GTH transceiver signal is connected to BNAK226. The LPC FMC2 expansion port has 36 pairs of differential signals, which are respectively connected to the IO of the BANK64 and BANK65 of the FPGA chip. The level standard is determined by the voltage VADJ of the BANK, and the default is 3.3V. The FMC HPC expansion port contains 58 pairs of differential IO signals, which are respectively connected to FPGA chips BANK66, BANK67, and BANK68, and the voltage standard is 1.8V. 8 high-speed GTH transceiver signals are connected to the IO of the FPGA chip BANK227 and BANK228. The schematic diagrams of FPGA and FMC LPC connectors are shown in Figures 2-6-1, 2-6-2, and 2-6-3：

Figure 2-6-3 HPC FMC3 schematic diagram
The 1st FMC LPC Connectors Pin Assignment

The 2nd FMC LPC connector pin assignment is as follows

The 3rd FMC LPC connector pin assignment is as follows

Part 2.7: SD Card Slot
The AXKU042 FPGA development board includes a Micro SD card interface to provide users with access to SD card memory for storing pictures, music or other user data files. The signal is linked to the IO signal of the BANK64 of FPGA, and the schematic of the FPGA and SD card connector is shown in Figure 2-7-1

Figure 2-7-1 SD Card Slot schematic diagram SD Card Slot pin assignment

Part 2.8: SMA Interface The AXKU042 FPGA development board is designed with 2 SMA interfaces, and the differential signal is connected to the BANK66 ordinary clock IO port, providing customers with an external clock interface or according to the ordinary IO port, the interface level is 1.8V. The schematic diagram of the FPGA and SMA interface connection is shown in Figure 2-8-1.

SMA Interface pin assignment

Part 2.9: Temperature Sensor and EEPROM

A high-precision, low-power, digital temperature sensor chip is mounted on the AXKU042 FPGA development board, and the model is LM75A of ON Semiconductor. The temperature accuracy of the LM75A chip is 0.5 degrees. The sensor and FPGA are directly connected to the I2C digital interface. The FPGA reads the temperature near the current FPGA development board through the I2C interface.The model of the EEPROM is 24LC04, and the capacity is: 4Kbit, which is connected to the PS terminal through the I2C bus.

Figure 2-9-1 below shows the design of the LM75 sensor and EEPROM chip

Figure 2-9-1 I2C Connection schematic diagram I2C Sensor Pin Assignment

Part 2.10: LED Light There are Seven red LEDs on the AXKU042 FPGA carrier board, one of which is the power indicator (PWR), four are control indicators, two are panel indicators. When the AXKU042 FPGA board is powered on, the power indicator will light up, 4 user LEDs and two-panel indicators are connected to the IO of the FPGA BANK65 and BANK66, the user can control the lighting and extinction through the program. When the IO voltage connected to the user LED is configured low level, the user LED lights up. When the connected IO voltage is configured as high level, the user LED will be extinguished.

The LED hardware connection is shown in Figure 2-10-1

Figure 2-10-2 panel indicator LED

Pin assignment of user LED lights

Part 2.11: Keys

The AXKU062 FPGA development board contains two user Keys and 1 reset key. One user key are connected to the IO of FPGA BANK65. The user key is active at a low level to realize some functions of the board for customers; The reset key is used for system reset. The circuit of the user key part is shown in Figure 2-11-1:

Keys Pin Assignment

Part 2.12: JTAG Interface

The JTAG interface is reserved on the AXKU042 development board for downloading FPGA programs or firmware programs to FLASH. In order to not damage the FPGA chip by plugging and unplugging under power, we added a protection diode to the JTAG signal to ensure that the signal voltage is within the range accepted by the FPGA and avoid damage to the FPGA chip. JTAG schematic diagram is shown in Figure 2-12-1:

Part 2.13: Power Supply

The power input voltage of the AXKU042 development board is DC12V, with an external+12V power supply or power supplied to the board through PCIE. When using an external power supply, please use the power supply provided by the development board, and do not use other specifications of the power supply to avoid damaging the development board. The schematic diagram of the power supply design on the board is shown in Figure 2-13-1

Part 2.14: Fan

Because FPGA generates a lot of heat when it works normally, we add a heat sink and fan to the chip on the board to prevent the chip from overheating. The control of the fan is controlled by the FPGA chip. The control pin is connected to the IO of the BANK48. If the IO level output is high, the MOSFET is turned on and the fan is working. If the IO level output is low, the fan stops. The fan design on the board is shown in Figure 2-14-1.

Fan Pin Assignment

Part 2.15:Size Dimension

http://www.alinx.com

References

• ALINX 芯驿电子科技（上海）有限公司

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