infineon CYT2B6 TRAVEO T2G 32 Bit Automotive MCU User Guide
- June 12, 2024
- infineon
Table of Contents
- infineon CYT2B6 TRAVEO T2G 32 Bit Automotive MCU
- Product Information: CYT2B6 TRAVEOTM T2G 32-bit Automotive MCU
- Product Usage Instructions
- General description
- 16 TCPWM0 Group #0, Counter #17 TCPWM0 Group #0, Counter #18 TCPWM0 Group #0,
- 24 TCPWM0 Group #0, Counter #25 TCPWM0 Group #0, Counter #26 TCPWM0 Group #0,
- 39 TCPWM0 Group #0, Counter #40 TCPWM0 Group #0, Counter #41 TCPWM0 Group #0,
- 48 TCPWM0 Group #0, Counter #49 TCPWM0 Group #0, Counter #50 TCPWM0 Group #0,
- References
- Read User Manual Online (PDF format)
- Download This Manual (PDF format)
infineon CYT2B6 TRAVEO T2G 32 Bit Automotive MCU
Product Information: CYT2B6 TRAVEOTM T2G 32-bit Automotive MCU
The CYT2B6 TRAVEOTM T2G 32-bit Automotive MCU is a microcontroller unit designed specifically for automotive applications. It offers a range of features and capabilities to support various automotive systems.
Features:
- CPU Core: The MCU is equipped with a 32-bit CPU core.
- Functional Safety: It meets ASIL-B requirements for functional safety.
- Operating Voltage: The MCU can operate within a voltage range of 2.7 V to 5.5 V.
- Core Voltage: The core voltage can be set between 1.05 V to 1.15 V.
- Operating Frequency: The MCU supports various operating frequencies for the MPU and PPU.
- Memory: It has a code-flash memory of 576 KB and a work-flash memory of 64 KB. Additionally, it features SRAM and ROM memories.
- Communication Interfaces: The MCU supports multiple communication interfaces including CAN, UART, I2C, SPI, and LIN.
- Timers: It has RTC and TCPWM timers for precise timing control.
- Analog: The MCU features SAR ADCs with multiple channels for analog input.
- Security: It offers flash security with program/work read protection and supports eSHE for enhanced secure hardware extension.
- DMA Controller: The MCU has multiple DMA channels for efficient data transfer.
- Oscillators: It includes an internal main oscillator and a low-speed oscillator for clock generation.
- Watchdog Timer: The MCU supports a watchdog timer for system monitoring.
- GPIO: It provides a number of GPIO pins for general-purpose input/output.
- Low-Voltage Detect: The MCU has low-voltage detection capabilities.
- Maximum Ambient Temperature: The MCU can operate within a specified maximum ambient temperature.
- Debug Interface: It supports SWD/JTAG debug interface for debugging and programming.
- Debug Trace: The MCU offers debug trace functionality for advanced debugging.
Product Usage Instructions
- Power Supply: Connect the MCU to a power source within the operating voltage range of 2.7 V to 5.5 V. Ensure the core voltage is set correctly between 1.05 V to 1.15 V.
- Clock Configuration: Set the desired operating frequency using the internal main oscillator or the low-speed oscillator. The PLL and FLL can be used to achieve the desired frequency.
- Memory Usage: Utilize the code-flash memory of 576 KB and work-flash memory of 64 KB for program storage. Allocate SRAM and ROM as required for data storage.
- Communication Interfaces: Connect external devices to the appropriate communication interfaces such as CAN, UART, I2C, SPI, or LIN. Configure the interfaces according to the desired communication protocol.
- Timer Configuration: Set up RTC and TCPWM timers for precise timing control in your application.
- Analog Input: Utilize the SAR ADCs with multiple channels to capture analog data. Configure the ADC channels and sampling parameters accordingly.
- Security Configuration: Enable flash security features for program/work read protection if required. Configure eSHE using third-party firmware if necessary.
- DMA Configuration: Use the DMA controller to efficiently transfer data between different peripherals and memory locations. Configure the DMA channels as needed.
- GPIO Usage: Connect external devices or utilize the GPIO pins for general-purpose input/output. Configure the GPIO pins according to your application requirements.
- Debugging and Programming: Use the SWD/JTAG debug interface for debugging and programming the MCU. Take advantage of the debug trace functionality for advanced debugging.
Please refer to the product datasheet available at www.infineon.com for more detailed information and specifications.
CYT2B6
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
General description
CYT2B6 is a family of TRAVEOTM T2G microcontrollers targeted at automotive systems such as body control units. CYT2B6 has an Arm® Cortex®-M4 CPU for primary processing and an Arm® Cortex®-M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data rate (CAN FD), and Local Interconnect Network (LIN). TRAVEOTM T2G devices are manufactured on an advanced 40-nm process. CYT2B6 incorporates a low-power flash memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure computing platform.
Features
· Dual CPU subsystem – 80-MHz (max) 32-bit Arm® Cortex®-M4F CPU with · Single-
cycle multiply · Single-precision floating point unit (FPU) · Memory
protection unit (MPU) – 80-MHz (max) 32-bit Arm® Cortex®-M0+ CPU with ·
Single-cycle multiply · Memory protection unit – Inter-processor communication
in hardware – Three DMA controllers · Peripheral DMA controller #0 (P-DMA0)
with 54 channels · Peripheral DMA controller #1 (P-DMA1) with 26 channels ·
Memory DMA controller #0 (M-DMA0) with 2 channels
· Integrated memories – 576 KB of code-flash with an additional 64 KB of work-
flash · Read-While-Write (RWW) allows updating the code-flash/work-flash while
executing from it · Single- and dual-bank modes (specifically for Firmware
update Over The Air [FOTA]) · Flash programming through SWD/JTAG interface –
64 KB of SRAM with selectable retention granularity
· Crypto engine[1] – Supports enhanced Secure Hardware Extension (eSHE) and
Hardware Security Module (HSM) – Secure boot and authentication · Using
digital signature verification · Using fast secure boot – AES: 128-bit blocks,
128-/192-/256-bit keys – 3DES[2]: 64-bit blocks, 64-bit key – Vector unit[2]
supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and
Elliptic Curve (ECC) – SHA-1/2/3[2]: SHA-512, SHA-256, SHA-160 with variable
length input data – CRC[2]: supports CCITT CRC16 and IEEE-802.3 CRC32 – True
random number generator (TRNG) and pseudo random number generator (PRNG) –
Galois/Counter Mode (GCM)
Notes 1. The Crypto engine features are available on select MPNs. 2. This feature is not available in “eSHE only” parts; for more information, refer to Ordering information.
Datasheet www.infineon.com
Please read the Important Notice and Warnings at the end of this document page 1
002-25756 Rev. *C 2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Features
· Functional safety for ASIL-B – Memory protection unit (MPU) – Shared memory
protection unit (SMPU) – Peripheral protection unit (PPU) – Watchdog timer
(WDT) – Multi-counter watchdog timer (MCWDT) – Low-voltage detector (LVD) –
Brown-out detector (BOD) – Overvoltage detection (OVD) – Clock supervisor
(CSV) – Hardware error correction (SECDED ECC) on all safety-critical memories
(SRAM, flash)
· Low-power 2.7-V to 5.5-V operation – Low-power Active, Sleep, Low-power
Sleep, DeepSleep, and Hibernate modes for fine-grained power management –
Configurable options for robust BOD · Two threshold levels (2.7 V and 3.0 V)
for BOD on VDDD and VDDA · One threshold level (1.1 V) for BOD on VCCD
· Wakeup support – A GPIO pin to wakeup from Hibernate mode – Up to 78 GPIO
pins to wakeup from Sleep modes – Event Generator, SCB, Watchdog Timer, RTC
alarms to wake from DeepSleep modes
· Clock sources – Internal main oscillator (IMO) – Internal low-speed
oscillator (ILO) – External crystal oscillator (ECO) – Watch crystal
oscillator (WCO) – Phase-locked loop (PLL) – Frequency-locked loop (FLL)
· Communication interfaces – Up to four CAN FD channels · Increased data rate
(up to 8 Mbps) compared to classic CAN, limited by physical layer topology and
transceivers · Compliant to ISO 11898-1:2015 · Supports all the requirements
of Bosch CAN FD Specification V1.0 for non-ISO CAN FD · ISO 16845:2015
certificate available – Up to six runtime-reconfigurable SCB (serial
communication block) channels, each configurable as I2C, SPI, or UART – Up to
five independent LIN channels · LIN protocol compliant with ISO 17987
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Features
· Timers – Up to 50 16-bit and two 32-bit timer/counter pulse-width modulator
(TCPWM) blocks · Up to four 16-bit counters for motor control · Up to 46
16-bit counters and two 32-bit counters for regular operations · Supports
timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with
dead time (PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
– Up to 11 Event Generation (EVTGEN) timers supporting cyclic wakeup from
DeepSleep · Events trigger a specific device operation (such as execution of
an interrupt handler, a SAR ADC conversion, and so on)
· Real time clock (RTC) – Year/Month/Date, Day-of-week, Hour:Minute:Second
fields – 12- and 24-hour formats – Automatic leap-year correction
· I/O – Up to 78 programmable I/Os – Two I/O types · GPIO Standard (GPIO_STD)
· GPIO Enhanced (GPIO_ENH)
· Regulators – Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input
supply – Two types of regulators · DeepSleep · Core internal
· Programmable analog – Three SAR A/D converters with up to 35 external
channels (32 I/Os + 3 I/Os for motor control) · ADC0 supports 11 logical
channels, with 11 + 1 physical connections · ADC1 supports 13 logical
channels, with 13 + 1 physical connections · ADC2 supports 8 logical channels,
with 8 + 1 physical connections · Any external channel can be connected to any
logical channel in the respective SAR – Each ADC supports 12-bit resolution
and sampling rates of up to 1 Msps – Each ADC also supports up to six internal
analog inputs like · Bandgap reference to establish absolute voltage levels ·
Calibrated diode for junction temperature calculations · Two AMUXBUS inputs
and two direct connections to monitor supply levels – Each ADC supports
addressing of external multiplexers – Each ADC has a sequencer supporting
autonomous scanning of configured channels – Synchronized sampling of all ADCs
for motor-sense applications
· Smart I/O – Up to three Smart I/O blocks, which can perform Boolean
operations on signals going to and from I/Os – Up to 16 I/Os (GPIO_STD)
supported
· Debug interface – JTAG controller and interface compliant to
IEEE-1149.1-2001 – Arm® SWD (serial wire debug) port – Supports Arm® Embedded
Trace Macrocell (ETM) Trace · Data trace using SWD · Instruction and data
trace using JTAG
Datasheet
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Features
· Compatible with industry-standard tools – GHS/MULTI or IAR EWARM for code
development and debugging
· Packages – 64-LQFP, 10 × 10 × 1.7 mm (max), 0.5-mm lead pitch – 80-LQFP, 12
× 12 × 1.7 mm (max), 0.5-mm lead pitch – 100-LQFP, 14 × 14 × 1.7 mm (max),
0.5-mm lead pitch
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Features list
1
Features list
Table 1-1 CYT2B6 feature list for all packages
Features
64-LQFP
Packages 80-LQFP
100-LQFP
CPU
Core
32-bit Arm® Cortex®-M4F CPU and 32-bit Arm® Cortex®-M0+ CPU
Functional safety
ASIL-B
Operating voltage
2.7 V to 5.5 V
Core voltage
1.05 V to 1.15 V
Operating frequency
Arm® Cortex®-M4 80 MHz (max) and Arm® Cortex®-M0+ 80 MHz (max), related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on)
MPU, PPU
Supported
FPU
Single precision (32-bit)
DSP-MUL/DIV/MAC
Supported by Arm® Cortex®-M4F CPU
Memory
Code-flash
576 KB (448 KB + 128 KB)
Work-flash
64 KB (48 KB + 16 KB)
SRAM (configurable for retention)
64 KB
ROM
32 KB
Communication interfaces
CAN 0 (CAN FD: Up to 8 Mbps)
2 ch
CAN 1 (CAN FD: Up to 8 Mbps)
1 ch
2 ch
CAN RAM
24 KB per instance (2 ch), 48 KB in total
Serial communication block (SCB/UART)
6 ch
Serial communication block (SCB/I2C)
5 ch
6 ch
Serial communication block (SCB/SPI)
3 ch
6 ch
LIN0
5 ch
Timers
RTC
1 ch
TCPWM (16-bit) (Motor Control)
4 ch
TCPWM (16-bit)
46 ch
TCPWM (32-bit)
2 ch
External interrupts
49
63
78
Analog
3 Units (SAR0/11, SAR1/13, SAR2/8 logical channels)
12-bit, 1 Msps SAR ADC
22 external channels 28 external channels 32 external channels
(SAR0 8 ch, SAR1 7 ch,
(SAR0 10 ch,
(SAR0 11 ch, SAR1 13 ch,
SAR2 7 ch)
SAR1 10 ch, SAR2 8 ch)
SAR2 8 ch)
18 ch (6 per ADC) Internal sampling
Motor control input
3 ch (synchronous sampling of one channel on each of the 3 ADCs)
Security
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Features list
Table 1-1
CYT2B6 feature list for all packages (continued)
Features
64-LQFP
Packages 80-LQFP
100-LQFP
Flash security (program/work read protection)
Supported
Flash chip erase enable eSHE
Configurable By separate firmware[3]
System
DMA controller
P-DMA0 with 54 channels (16 general purpose), P-DMA1 with 26 channels (8 general purpose), and M-DMA0 with 2 channels
Internal main oscillator
8 MHz
Internal low-speed oscillator
32.768 kHz (nominal)
PLL
Input frequency: 3.988 to 33.34 MHz, PLL output frequency: up to 80 MHz
FLL
Input frequency: 0.25 to 80 MHz, FLL output frequency: up to 80 MHz
Watchdog timer and multi-counter watchdog timer
Supported
Clock supervisor
Supported
Cyclic wakeup from DeepSleep
Supported
GPIO_STD
45
59
74
GPIO_ENH
4
Smart I/O (Blocks)
3 blocks, 9 I/Os
3 blocks, 14 I/Os
3 blocks, 16 I/Os
Low-voltage detect
Two, 26 selectable levels
Maximum ambient temperature
105 °C for S-grade and 125 °C for E-grade
Debug interface
SWD/JTAG
Debug trace
Arm® Cortex® -M4 ETB size of 8 KB, Arm® Cortex®-M0+ MTB size of 4 KB
Note 3. Enhanced Secure Hardware Extension (eSHE) is enabled by third-party firmware.
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Features list
1.1
Communication peripheral instance list
The following table lists the instances supported under each package for communication peripherals, based on the minimum pins needed for the functionality.
Table 1-2 Peripheral instance list
Module
64-LQFP
80-LQFP
100-LQFP
Minimum pin functions
CAN0
0/1
0/1
0/1
TX, RX
CAN1
0
0/1
0/1
TX, RX
LIN0
0/1/2/3/4
0/1/2/3/4
0/1/2/3/4
TX, RX
SCB/UART 0/1/3/4/5/7
0/1/3/4/5/7
0/1/3/4/5/7
TX, RX
SCB/I2C
0/3/4/5/7
0/1/3/4/5/7
0/1/3/4/5/7
SCL, SDA
SCB/SPI
0/3/4
0/1/3/4/5/7
0/1/3/4/5/7
MISO, MOSI, SCK, SELECT0
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Blocks and functionality
2
Blocks and functionality
Block diagram
CYT2B6
MXS40-HT ASIL-B
System Resources
Power Sleep Control POR BOD OVD LVD
REF
PWRSYS-HT
LDO
Clock
Clock Control
2xILO WDT
IMO ECO
FLL
CSV
1xPLL
Reset Reset Control
XRES
Test
TestMode Entry Digital DFT Analog DFT
WCO RTC
Power Modes Active/Sleep LowePowerActive/Sleep DeepSleep
Hibernate
IOSS GPIO
SWJ/ETM/ITM/CTI
Arm® Cortex®-M4
80 MHz
FPU, NVIC, MPU
PCLK
Prog. Analog
SAR ADC (12-bit)
x3
SARMUX 32 ch
I/O Subsystem
eCT Flash 576 KB Code Flash +
64 KB Work Flash
8 KB $
8 KB $
Flash Controller
CPU Subsystem
SRAM0
64 KB
SRAM Controller
M-DMA0
2 Channel
P-DMA1
26 Channel
P-DMA0
54 Channel
CRYPTO
AES, SHA, CRC, TRNG, RSA, ECC
Initiator/MMIO
SWJ/MTB/CTI
Arm® Cortex®-M0+
80 MHz
MUL, NVIC, MPU
ROM
32 KB
ROM Controller
System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)
Peripheral Interconnect (MMIO, PPU)
eFuse
1024 bit
EVTGEN Event Generator
Up to 4x CANFD
CAN-FD Interface
Up to 5x SCB
I2C, SPI, UART
1x SCB
I2C, SPI, UART
Up to 5x LIN
LIN/UART
52x TCPWM
TIMER,CTR,QD, PWM
High Speed I/O Matrix, Smart I/O, Boundary Scan 3x Smart I/O
Up to 74x GPIO_STD, 4x GPIO_ENH
The Block diagram shows the CYT2B6 architecture, giving a simplified view of
the interconnection between subsystems and blocks. CYT2B6 has four major
subsystems: CPU, system resources, peripherals, and I/O[4, 5]. The color-
coding shows the lowest power mode where the particular block is still
functional.
CYT2B6 provides extensive support for programming, testing, debugging, and
tracing of both hardware and firmware.
Debug-on-chip functionality enables in-system debugging using the production
device. It does not require special interfaces, debugging pods, simulators, or
emulators.
The JTAG interface is fully compatible with industry-standard third-party
probes such as I-jet, J-Link, and GHS.
The debug circuits are enabled by default.
CYT2B6 provides a high level of security with robust flash protection and the
ability to disable features such as debug.
Additionally, each device interface can be permanently disabled for
applications concerned with phishing attacks from a maliciously reprogrammed
device or attempts to defeat security by starting and interrupting flash
programming sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled.
Notes 4. GPIO_STD supporting 2.7 V to 5.5 V VDDIO range. 5. GPIO_ENH supporting 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages.
Datasheet
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Based on Arm® Cortex®-M4 dual
Functional description
3
Functional description
3.1
CPU subsystem
3.1.1
CPU
The CYT2B6 CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU and a 32-bit Arm® Cortex®-M4F CPU with MPU, and single-precision FPU. This subsystem also includes P-/M-DMA controllers, a cryptographic accelerator, 576 KB of code-flash, 64 KB of work-flash, 64 KB of SRAM, and 32 KB of ROM.
The Cortex®-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash, SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by an inter-processor communication (IPC) mechanism using hardware semaphores.
3.1.2
DMA controllers
CYT2B6 has three DMA controllers: P-DMA0 with 16 general-purpose and 38 dedicated channels, P-DMA1 with 8 general-purpose and 18 dedicated channels, and M-DMA0 with two channels. P-DMA is used for peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels. General-purpose channels have a rich interconnect matrix including P-DMA cross triggering, which enables demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel) to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each channel. They support independent accesses to peripherals using the AHB multi- layer bus.
3.1.3
Flash
CYT2B6 has 576 KB (448 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size) of code-flash with an additional work-flash of up to 64 KB (48 KB with 2-KB sector size, and 16 KB with 128-B sectors size). Work-flash is optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW) operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support dual-bank operation for over-the-air (OTA) programming.
3.1.4
SRAM
CYT2B6 has 64 KB of SRAM. The SRAM0 controller provides DeepSleep retention in 32-KB increments.
3.1.5
ROM
CYT2B6 has 32-KB ROM that contains boot and configuration routines. This ROM enables secure boot and authentication of user flash to guarantee a secure system.
3.1.6
Cryptography accelerator for security
The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy check, pseudo random number generation, true random number generation, galois/counter mode, and a vector unit to support asymmetric key cryptography such as RSA and ECC.
Depending on the part number, this block is either completely or partially available or not available at all. See Ordering information for more details.
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Functional description
3.2
System resources
3.2.1
Power system
The power system ensures that the supply voltage levels meet the requirements of each power mode, and provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip reset during the initial power ramp.
Three BOD circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on VDDD and VCCD are initially enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be enabled by the user. For the external supplies VDDD and VDDA, BOD circuits are software configurable with two settings; a 2.7-V minimum voltage that is robust for all internal signaling and a 3.0-V minimum voltage, which is also robust for all I/O specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not a robust detector.
Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage. Two voltage-detection circuits are provided to monitor the external supply voltage (VDDD) for falling and rising levels, each configurable for one of the 26 selectable levels.
All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic. The BOD and OVD circuits on VDDA can be configured to generate either a reset or a fault.
3.2.2
Regulators
CYT2B6 contains two regulators that provide power to the low-voltage core transistors: DeepSleep and core internal. These regulators accept a 2.75.5-V VDDD supply and provide a low-noise 1.1-V supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and firmware when switching between power modes. The core internal and core external regulators operate in active mode, and provide power to the CPU subsystem and associated peripherals.
3.2.2.1 DeepSleep
The DeepSleep regulator is used to maintain power to a small number of blocks
when in DeepSleep mode. These blocks include the ILO and WDT timers, BOD
detector, SCB0, SRAM memories, Smart I/O, and other configuration memories.
The DeepSleep regulator is enabled when in DeepSleep mode, and the core
internal regulator is disabled. It is disabled when XRES_L is asserted (LOW)
and when the core internal regulator is disabled.
3.2.2.2 Core internal
The core internal regulator supports load currents up to 150 mA, and is
operational during device start-up (boot process) and in Active/Sleep modes.
3.2.3
Clock system
The CYT2B6 clock system provides clocks to all subsystems that require them, and glitch-free switching between different clock sources. In addition, the clock system ensures that no metastable conditions occur.
The clock system for CYT2B6 consists of the 8-MHz IMO, two ILOs, three watchdog timers, a PLL, an FLL, five clock supervisors (CSV), a 3.988- to 33.34 MHz ECO, and a 32.768-kHz WCO.
The clock system supports two main clock domains: CLK_HF and CLK_LF.
· CLK_HFx are the Active mode clocks. Each can use any of the high-frequency clock sources including IMO, EXT_CLK, ECO, FLL, or PLL
· CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO
Datasheet
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Functional description
Table 3-1 Name
CLK_HF0 CLK_HF1
CLK_HF Destinations Description
CPUSS clocks, PERI, and AHB infrastructure Event Generator, also available in
HSIOM as an output
3.2.3.1 IMO clock source
The IMO is the frequency reference in CYT2B6 when no external reference is
available or enabled. The IMO operates at a frequency of around 8 MHz.
3.2.3.2 ILO clock source
An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks
for a watchdog timer when in DeepSleep mode. There are two ILOs to ensure
clock supervisor (CSV) capability in DeepSleep mode. ILO-driven counters can
be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also
used for clock supervision.
3.2.3.3 PLL and FLL
A PLL or FLL may be used to generate high-speed clocks from the IMO, the ECO,
or EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of
35 µs) in exchange for a small amount (±2%) of frequency error[6].
3.2.3.4 Clock supervisor (CSV)
Each CSV allows one clock (reference) to supervise the behavior of another
clock (monitored). Each CSV has counters for both the monitored and reference
clocks. Parameters for each counter determine the frequency of the reference
clock as well as the upper and lower frequency limits of the monitored clock.
If the frequency range comparator detects a stopped clock or a clock outside
the specified frequency range, an abnormal state is signaled and either a
reset or an interrupt is generated.
3.2.3.5 EXT_CLK
One of the two GPIO_STD I/Os can be used to provide an external clock input of
up to 80 MHz. This clock can be used as the source clock for either the PLL or
FLL, or can be used directly by the CLK_HF domain.
3.2.3.6 ECO
The ECO provides high-frequency clocking using an external crystal connected
to the ECO_IN and ECO_OUT pins. It supports fundamental mode (non-overtone)
quartz crystals, in the range of 3.988 to 33.34 MHz. When used in conjunction
with the PLL, it generates CPU and peripheral clocks up to device’s maximum
frequency. ECO accuracy depends on the selected crystal. If the ECO is
disabled, the associated pins can be used for any of the available I/O
functions.
3.2.3.7 WCO
The WCO is a low-power, watch-crystal oscillator intended for real-time-clock
applications. It requires an external 32.768-kHz crystal connected to the
WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock reference
for CLK_LF, which is the clock source for the MCWDT and RTC.
Note
6. Operation of reference-timed peripherals (like a UART) with an FLL-based
reference is not recommended due the allowed frequency error.
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.2.4
Reset
CYT2B6 can be reset from a variety of sources, including software. Reset events are asynchronous and guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT, software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES_L pin is available for external reset.
3.2.5
Watchdog timers
CYT2B6 has one watchdog timer (WDT) and two multi-counter watchdog timers (MCWDT).
The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause register.
An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.
3.2.6
Power modes
CYT2B6 has the following power modes:
· Active all peripherals are available
· Low-Power Active (LPACTIVE) Low-power profile of Active mode where all peripherals and the CPUs are available, but with limited capability
· Sleep all peripherals except the CPUs are available
· Low-Power Sleep (LPSLEEP) Low-power profile of Sleep mode where all peripherals except the CPUs are available, but with limited capability
· DeepSleep only peripherals which work with CLK_LF are available
· Hibernate the device and I/O states are frozen, and the device resets on wakeup
3.3
Peripherals
3.3.1
Peripheral clock dividers
Integer and fractional clock dividers are provided for peripheral and timing purposes.
Table 3-2 Clock dividers
Divider div_8 div_16 div_24_5
Count 32 16 8
Description Integer divider, 8 bits Integer divider, 16 bits Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)
3.3.2
Peripheral protection unit
The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU, P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.3.3
12-bit SAR ADC
CYT2B6 contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to
26.67 MHz and provide a 12-bit result in 26 clock cycles.
The references for all three SAR ADCs come from a dedicated pair of inputs:
VREFH and VREFL[7].
CYT2B6 devices support up to 53 logical ADC channels, and external inputs from up to 35 I/Os. Each ADC also supports six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC and package type) are listed in Table 1-1.
Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates subsequent conversions for repetitive or group conversions without CPU intervention.
Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32 GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports synchronous sampling of one motor-sense channel on each of the three ADCs.
CYT2B6 has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be sampled by one ADC at a time. Software post processing is required to convert the temperature sensor reading into kelvin or Celsius values.
To accommodate signals with varying source impedances and frequencies, it is possible to have different sample times programmed for each channel. Each ADC also supports range comparison, which allows fast detection of out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate the measurement for out-of-range values.
The ADCs are not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input reference voltage VREFH range is 2.7 V to VDDA and VREFL is VSSA.
3.3.4
Timer/counter/PWM (TCPWM) block
The TCPWM block consists of 16-bit (50 channels) and 32-bit (two channels) counters with a user-programmable period. Four of the 16-bit counters include extra features to support motor control operations. Each TCPWM counter contains a capture register to record the count at the time of an event, a period register (used to either stop or auto-reload the counter when its count is equal to the period register), and compare registers to generate signals that are used as PWM duty-cycle outputs.
Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature, PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.
In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead times for PWM output signals.
The TCPWM block also provides true and complement outputs, with programmable offset between them, to allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time for software intervention).
Note 7. VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting
the measurements. VREF_L, when properly connected, reduces
or removes the impact of IR drops in the VSSIO and VSSA paths from
measurements.
Datasheet
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2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.3.5
Serial communication blocks (SCB)
CYT2B6 contains up to six serial communication blocks, each configurable to support I2C, UART, or SPI.
3.3.5.1 I2C interface
An SCB can be configured to implement a full I2C master (capable of multi-
master arbitration) or slave interface. Each SCB configured for I2C can
operate at speeds of up to 1 Mbps (Fast-mode Plus[8]) and has flexible
buffering options to reduce the interrupt overhead and latency of the CPU. In
addition, each SCB supports FIFO buffering for receive and transmit data,
which, by increasing the time for the CPU to read the data, reduces the need
for clock stretching. The I2C interface is compatible with Standard, Fast-
mode, and Fast-mode Plus devices as specified in the NXP I2C-bus specification
and user manual (UM10204). The I2C-bus I/O is implemented with GPIO in open-
drain modes[9, 10].
3.3.5.2 UART interface
When configured as a UART, each SCB provides a full-featured UART with maximum
signaling rate determined by the configured peripheral-clock frequency and
over-sampling rate. It supports infrared interface (IrDA) and SmartCard (ISO
7816) protocols, which are minor variants of the UART protocol. It also
supports the 9-bit multiprocessor mode that allows the addressing of
peripherals connected over common Rx and Tx lines. Common UART functions such
as parity, number of stop bits, break detect, and frame error are supported.
FIFO buffering of transmit and receive data allows greater CPU service
latencies to be tolerated.
The LIN protocol is supported by the UART. LIN is based on a single-master
multi-slave topology. There is one master node and multiple slave nodes on the
LIN bus. The SCB UART supports only LIN slave functionality. Compared to the
dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of
software interaction and increased CPU load.
3.3.5.3 SPI interface
The SPI configuration supports full Motorola SPI, TI Synchronous Serial
Protocol (SSP, essentially adds a start pulse that is used to synchronize SPI-
based Codecs), and National Microwire (a half-duplex form of SPI). The SPI
interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz
SPI Clock. SCB also supports EZSPI[11] mode.
SCB0 supports the following additional features:
· Operable as a slave in DeepSleep mode · I2C slave EZ (EZI2C[12]) mode with
up to 256-B data buffer for multi-byte communication without CPU
intervention · I2C slave externally-clocked operations
· Command/response mode with a 512-B data buffer for multi-byte communication
without CPU intervention
Notes 8. I/Os drive level does not support the full bus capacitance in Fast-
mode Plus speeds. 9. This is not 100% compliant with the I2C-bus
specification; I/Os are not over-voltage tolerant, do not support the 20-mA
sink require-
ment of Fast-mode Plus, and violate the leakage specification when no power is
applied. 10.Only Port 0 with the slew rate control enabled meets the minimum
fall time requirement. 11.The Easy SPI (EZSPI) protocol is based on the
Motorola SPI operating in any mode (0, 1, 2, or 3). It allows communication
between
master and slave reduces the need for CPU intervention. 12.The Easy I2C
(EZI2C) protocol is a unique communication scheme built on top of the I2C
protocol by Infineon. It uses a meta protocol
around the standard I2C protocol to communicate to an I2C slave using indexed
memory transfers. This reduces the need for CPU intervention.
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.3.6
CAN FD
CYT2B6 supports two CAN FD controller blocks, each supporting up to two CAN FD channels. All CAN FD controllers are compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in hardware.
All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx handler manages message acceptance filtering, transfer of received messages from the CAN core to a message RAM, and provides receive- message status. The Tx handler is responsible for the transfer of transmit messages from the message RAM, to the CAN core, and provides transmit-message status.
3.3.7
Local interconnect network (LIN)
CYT2B6 contains up to five LIN channels. Each channel supports transmission/reception of data following the LIN protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a 3-pin interface (including an enable function) and supports master and slave functionality. Each channel also supports classic and enhanced checksum, along with break detection during message reception and wake-up signaling. Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.
3.3.8
One-time-programmable (OTP) eFuse
CYT2B6 contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing, programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available for user purposes.
3.3.9
Event generator
The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing overall power consumption and processing overhead.
3.3.10 Trigger multiplexer
CYT2B6 supports connecting various peripherals using trigger signals. Triggers
are used to inform a peripheral of the occurrence of an event or change of
state. These triggers are used to affect or initiate some action in other
peripherals. The trigger multiplexer is used to route triggers from a source
peripheral to a destination. Triggers provide active logic functionality and
are typically supported in Active mode.
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.4
I/Os
CYT2B6 has up to 78 programmable I/Os.
The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on, and reset, the I/Os are forced to the High-Z state. During the Hibernate mode, the I/Os are frozen.
Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service routine (ISR) associated with it.
I/O port power source mapping is listed in Table 3-3. The associated supply determines the VOH, VOL, VIH, and VIL levels when configured for CMOS and Automotive thresholds.
Table 3-3 I/O port power source
Supply VDDD VDDIO_1 VDDIO_2
Ports
P0, P2, P3, P5, P17, P18, P19, P21, P22, P23 P6, P7, P8[13] P11, P12, P13, P14
Note 13.The I/Os in VDDIO_1 domain are referred to the VDDD domain in 64-LQFP package.
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Functional description
3.4.1
Port nomenclature
Px.y describes a particular bit “y” available within an I/O port “x.” For example, P4.2 reads “port 4, bit 2”.
Each I/O implements the following:
· Programmable drive mode – High impedance – Resistive pull-up – Resistive pull-down – Open drain with strong pull-down – Open drain with strong pull-up – Strong pull-up or pull-down – Weak pull-up or pull-down
CYT2B6 has two types of programmable I/Os: GPIO standard and GPIO Enhanced.
3.4.2
GPIO Standard (GPIO_STD)
Supports standard automotive signaling across the 2.7-V to 5.5-V VDDIO range. GPIO Standard I/Os have multiple configurable drive levels, drive modes, and selectable input levels.
3.4.3
GPIO Enhanced (GPIO_ENH)
Supports extended functionality automotive signaling across at lower voltages (full I2C timing support, slew-rate control).
the
2.7-V
to
5.5-V
VDDIO
range
with
higher
currents
Both GPIO_STD and GPIO_ENH implement the following:
· Configurable input threshold (CMOS, TTL, or Automotive)
· Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
· Analog input mode (input and output buffers disabled)
3.4.4
Smart I/O
Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals coming into the chip. CYT2B6 has three Smart I/O blocks. Operation can be synchronous or asynchronous and the blocks operate in all device power modes except for the Hibernate mode.
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
CYT2B6 address map
4
CYT2B6 address map
The CYT2B6 microcontroller supports the memory spaces shown in Figure 4-1.
· 576 KB (448 KB + 128 KB) of code-flash, used in the single- or dual-bank
mode based on the associated bit in the flash control register – Single-bank
mode – 576 KB – Dual-bank mode – 288 KB per bank
· 64 KB (48 KB + 16 KB) of work-flash, used in the single- or dual-bank mode
based on the associated bit in the flash control register – Single-bank mode –
64 KB – Dual-bank mode – 32 KB per bank
· 64 KB of SRAM (First 2 KB is reserved for internal usage)
· 32 KB of secure ROM
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
CYT2B6 address map
0xFFFF FFFF
ARM System Space
CPU & Debug Registers
0xE000 0000 0x43FF FFFF
Reserved
0x4000 0000
0x1780 7FFF 0x1780 0000 0x1700 7FFF 0x1700 0000
0x1400 FFFF
0x1400 C000 0x1400 BFFF
0x1400 0000
0x1008 FFFF 0x1007 0000 0x1006 FFFF
Reserved
Reserved
Reserved 16 KB
(128 B Small Sectors) 48 KB
(2 KB Large Sectors) Reserved 128 KB
(8 KB Small Sectors)
448 KB (32 KB Large Sectors)
Peripheral Interconnect or Memory map
Mainly used for on-chip peripherals e.g., AHB or APB Peripherals
Alternate Flash Supervisory Region
Flash Supervisory Region
Used to store manufacture specific data like flash protection settings, trim settings, device addresses, serial numbers, calibration data, etc.
Work flash
Work flash used for long term data retention
Code flash
Mainly used for user program code
0x1000 0000 0x0800 FFFF
0x0800 0800 0x0800 0000 0x0000 7FFF 0x0000 0000
Reserved
62 KB
2 KB
Reserved 32 KB
SRAM0 ROM
Figure 4-1 CYT2B6 address map[14, 15]
General purpose RAM, mainly used for data
Secured Boot ROM to set user specified protection levels, trim and
configuration data, code authentication, jump to user mode etc.
Notes 14.The size representation is not up to scale. 15.First 2 KB of SRAM is
reserved, not available for users. User must keep the power of first 32KB
block of SRAM0 in enabled or retained
in all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Flash base address map
5
Flash base address map
Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions along with their respective base addresses.
Table 5-1 Code-flash Address Mapping in Single Bank Mode
Code-flash Size (KB)
Large Sectors (LS)
Small Sectors (SS)
Large Sector Base Address
Small Sector Base Address
576
32 KB × 14
8 KB × 16
0x1000 0000
0x1007 0000
Table 5-2 Work-flash Address Mapping in Single Bank Mode
Work-flash Size (KB)
Large Sectors Small Sectors Large Sector Base Address Small Sector Base Address
64
2 KB × 24
128 B × 128
0x1400 0000
0x1400 C000
Table 5-3 Code-flash Address Mapping in Dual Bank Mode (Mapping A)
Code-flash First Size (KB) Half LS
First Half SS
Second Half LS
Second Half SS
First Half First Half LS Base SS Base Address Address
576 32 KB × 7 8 KB × 8 32 KB × 7 8 KB × 8 0x1000 0x1003
0000
8000
Second Half
LS Base Address
0x1200 0000
Second Half SS
Base Address
0x1203 8000
Table 5-4 Code-flash Address Mapping in Dual Bank Mode (Mapping B)
Code-flash First Size (KB) Half LS
First Half SS
Second Half LS
Second Half SS
First Half First Half LS Base SS Base Address Address
576
32 KB × 7 8 KB × 8 32 KB × 7 8 KB × 8 0x1200 0x1203
0000
8000
Second Half
LS Base Address
0x1000 0000
Second Half SS
Base Address
0x1003 8000
Table 5-5 Work-flash Address Mapping in Dual Bank Mode (Mapping A)
Work-flash First Size (KB) Half LS
First Half SS
Second Half LS
Second Half SS
First Half First Half LS Base SS Base Address Address
64
2 KB × 12 128 B × 64 2 KB × 12 128 B × 64 0x1400 0x1400
0000
6000
Second Half
LS Base Address
0x1500 0000
Second Half SS
Base Address
0x1500 6000
Table 5-6 Work-flash Address Mapping in Dual Bank Mode (Mapping B)
Work-flash First Size (KB) Half LS
First Half SS
Second Half LS
Second Half SS
First Half First Half LS Base SS Base Address Address
64
2 KB × 12 128 B × 64 2 KB × 12 128 B × 64 0x1500 0x1500
0000
6000
Second Half
LS Base Address
0x1400 0000
Second Half SS
Base Address
0x1400 6000
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Peripheral I/O map
6
Peripheral I/O map
Table 6-1 CYT2B6 peripheral I/O map
Section
Description
Base Address Instances Instance Size Group Slave
Peripheral interconnect
0x4000 0000
Peripheral group (0, 1, 2, 3, 5, 6, 9) PERI
Peripheral trigger group
0x4000 4000
7
0x4000 8000
11
0x20 0x400
0
0
Peripheral 1:1 trigger group
0x4000 C000
11
0x400
Peripheral interconnect, master interface 0x4001 0000
PERI_MS PERI Programmable PPU
0x4001 0000 6[16]
0x40
0
1
PERI Fixed PPU
0x4001 0800 458
0x40
Crypto Cryptography component
0x4010 0000
1
0
CPUSS CPU subsystem (CPUSS)
0x4020 0000
2
0
FAULT
Fault structure subsystem Fault structures
0x4021 0000
0x4021 0000
4
0x100
2
1
Inter process communication
0x4022 0000
IPC
IPC structures
0x4022 0000
8
0x20
2
2
IPC interrupt structures
0x4022 1000
8
0x20
Protection
0x4023 0000
PROT
Shared memory protection unit structures
0x4023 2000
16
0x40
2
3
Memory protection unit structures
0x4023 4000
16
0x400
FLASHC Flash controller
0x4024 0000
2
4
System Resources Subsystem Core Registers
0x4026 0000
Clock Supervision High Frequency
0x4026 1400
3
0x10
Clock Supervision Reference Frequency 0x4026 1710
1
SRSS
Clock Supervision Low Frequency
0x4026 1720
1
2
5
Clock Supervision Internal Low Frequency 0x4026 1730
1
Multi Counter WDT
0x4026 8000
2
0x100
Free Running WDT
0x4026 C000
1
SRSS Backup Domain/RTC BACKUP
Backup Register
0x4027 0000
0x4027 1000
4
2
6
0x04
P-DMA
P-DMA0 Controller P-DMA0 channel structures P-DMA1 Controller P-DMA1 channel structures
0x4028 0000
0x4028 8000
54
0x4029 0000
0x4029 8000
26
2
7
0x40
2
8
0x40
M-DMA0 Controller M-DMA
M-DMA0 channels
0x402A 0000
0x402A 1000
2
0x100
2
9
eFUSE eFUSE Customer Data (192 bits)
0x402C 0868
6
0x04
2 10
HSIOM High-Speed I/O Matrix (HSIOM)
0x4030 0000
17
0x10
3
0
Note 16.These six Programmable PPUs are configured by the Boot ROM and are
available for the user based on the access rights. Refer to the
device specific TRM to know more about the configuration of these programmable
PPUs.
Datasheet
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Based on Arm® Cortex®-M4 dual
Peripheral I/O map
Table 6-1
CYT2B6 peripheral I/O map (continued)
Section
Description
Base Address Instances Instance Size Group Slave
GPIO
GPIO port control/configuration
0x4031 0000
17
0x80
3
1
Programmable I/O configuration SMARTIO
SMARTIO port configuration
0x4032 0000
0x4032 0C00
3
0x100
3
2
Timer/Counter/PWM 0 (TCPWM0)
0x4038 0000
TCPWM0 Group #0 (16-bit)
0x4038 0000
46
TCPWM
TCPWM0 Group #1 (16-bit, Motor control) 0x4038 8000
4
0x80
3
3
0x80
TCPWM0 Group #2 (32-bit)
0x4039 0000
2
0x80
Event generator 0 (EVTGEN0)
0x403F 0000
EVTGEN
Event generator 0 comparator structures 0x403F 0800
11
3
4
0x20
Local Interconnect Network 0 (LIN0)
0x4050 0000
LIN
LIN0 Channels
0x4050 8000
5
0x100
5
0
CAN0 controller Message RAM CAN0 TTCANFD CAN1 controller Message RAM CAN1
0x4052 0000
2
0x4053 0000
0x4054 0000
2
0x4055 0000
0x200 0x5FFF 0x200 0x5FFF
5
1
5
2
SCB
Serial Communications Block (SPI/UART/I2C)
0x4060 0000
6
0x10000
0-7
6 [NA 2, 6]
Programmable Analog Subsystem (PASS0)
0x4090 0000
SAR0 channel controller
0x4090 0000
PASS0 SAR
SAR1 channel controller SAR2 channel controller
0x4090 1000 0x4090 2000
9
0
SAR0 channel structures
0x4090 0800
11
0x40
SAR1 channel structures
0x4090 1800
13
0x40
SAR2 channel structures
0x4090 2800
8
0x40
Datasheet
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Based on Arm® Cortex®-M4 dual
CYT2B6 clock diagram
7
CYT2B6 clock diagram
IMO
EXT_CLK
ECO
ECO Prescaler
WCO
LS
MUX
MU X
MUX FLL
MU X
MUX PLL
MU X
MUX
MU X
MUX
LS
MUX
LS
CLK_REF_HF
CLK_ PATH0
CLK_ PATH1
CLK_ PATH2
CLK_ PATH3
CLK_LF
CLK_ILO0 MUX
CLK_BAK
ILO0
LS
CLK_ILO0 CLK_REF_HF
CSV
MUX
Predivider (1/2/4/8)
MUX
Predivider (1/2/4/8)
MUX
Predivider (1/2/4/8)
CSV
CSV
CSV CLK_HF2
CLK_HF0
CLK_HF1
CSV CLK_ILO0
CSV CLK_LF
Divider (1-256)
CLK_PERI
Divider (1-256)
CLK_FAST
Divider (1-256)
CLK_SLOW
Divider (1-256)
CLK_GR3
Divider (1-256)
CLK_GR5
Divider (1-256)
Divider (1-256)
CLK_GR6 CLK_GR9
Peripheral Clock Dividers
PCLK_SMARTIOx_CLOCK PCLK_TCPWM_CLOCKSx
PCLK_CANFDx_CLOCK_CAN PCLK_LIN_CLOCK_CH_ENx
PCLK_SCBx_CLOCK PCLK_PASS_CLOCK_SARx PCLK_CPUSS_CLOCK_TRACE_IN
ILO1
LS
WDT RTC MCWDT
LEGEND 1: Active Domain DeepSleep Domain Hibernate Domain
LEGEND 2: Relationship of Monitored Clock and Reference Clock
Monitored Clock
Reference Clock
CSV
Event Generator
ROM/SRAM/FLASH
CM4 CPUSS Fast Infrastructure
CM0+ CPUSS Slow Infrastructure P-DMA / M-DMA
CRYPTO PERI SRSS
EFUSE
IOSS TCPWM CAN FD
LIN
SCB[*] SCB[0] SAR ADC CPUSS(Trace Clock)
Serial interface clock
Figure 7-1 CYT2B6 clock diagram
Datasheet
25
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
CYT2B6 CPU start-up sequence
8
CYT2B6 CPU start-up sequence
The start-up sequence is described in the following steps:
1. System Reset (@0x0000 0000)
2. CM0+ executes ROM boot (@0x0000 0004) i. Applies trims ii. Applies Debug
Access port (DAP) access restrictions and system protection from eFuse and
supervisory flash iii.Authenticates flash boot (only in SECURE life-cycle
stage) and transfers control to it
3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000) i. Debug
pins are configured as per the SWD/JTAG spec[17] ii. Sets CM0+ vector offset
register (CM0_VTOR part of the Arm® system space) to the beginning of flash
(@0x1000 0000) iii.CM0+ branches to its Reset handler
4. CM0+ starts execution i. Moves CM0+ vector table to SRAM (updates CM0+
vector table base) ii. Sets CM4_VECTOR_TABLE_BASE (@0x0000 0200) to the
location of CM4 vector table mentioned in flash (specified in CM4 linker
definition file) iii.Releases CM4 from reset iv.Continues execution of CM0+
user application
5. CM4 executes directly from either code-flash or SRAM i. CM4 branches to
its Reset handler ii. Continues execution of CM4 user application
Note 17.Port configuration of SWD/JTAG pins will be changed from the default
GPIO mode to support debugging after the boot process, refer
to Table 11-1 for pin assignments.
Datasheet
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002-25756 Rev. *C
2022-10-07
50 VDDIO_2 49 P12.4 48 P12.3 47 P12.2 46 P12.1 45 P12.0 44 VREFH 43 VDDA 42 VSSA 41 VREFL 40 P11.2 39 P11.1 38 P11.0 37 P8.2 36 P8.1 35 P8.0 34 P7.5 33 P7.4 32 P7.3 31 P7.2 30 P7.1 29 P7.0 28 VCCD 27 VSSD 26 VSSD
VSSD 76 P19.0 77 P19.1 78 P19.2 79 P19.3 80 P21.0 81 P21.1 82 P21.2 83 P21.3 84 XRES_L 85 VDDD 86 VSSD 87 VSSD 88 VCCD 89 P21.5 90 P22.0 91 P22.1 92 P22.2 93 P22.3 94 P23.3 95 P23.4 96 P23.5 97 P23.6 98 P23.7 99 VDDD 100
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
9
Pin assignment
VSSD 1 P0.0 2 P0.1 3 P0.2 4 P0.3 5 P2.0 6 P2.1 7 P2.2 8 P2.3 9 P3.0 10 P3.1 11
VDDD 12 VSSD 13
P5.0 14 P5.1 15 P5.2 16 P5.3 17 P6.0 18 P6.1 19 P6.2 20 P6.3 21 P6.4 22 P6.5
23 VDDD 24 VDDIO_1 25
100-LQFP
Figure 9-1 100-LQFP pin assignment
75 VDDD 74 P18.7 73 P18.6 72 P18.5 71 P18.4 70 P18.3 69 P18.2 68 P18.1 67 P18.0 66 P17.2 65 P17.1 64 P17.0 63 P14.3 62 P14.2 61 P14.1 60 P14.0 59 P13.7 58 P13.6 57 P13.5 56 P13.4 55 P13.3 54 P13.2 53 P13.1 52 P13.0 51 VSSD
Datasheet
27
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
VSSD 76 PWM_50_N/TC_50_TR1/TC_H_0_TR0/FAULT_OUT_2 P19.0 77
PWM_26/TC_26_TR0/TC_H_0_TR1/FAULT_OUT_3 P19.1 78
PWM_26_N/TC_26_TR1/TRIG_IN[28] P19.2 79 TRIG_IN[29] P19.3 80
PWM_42/TC_42_TR0/WCO_IN P21.0 81
PWM_41/PWM_42_N/TC_41_TR0/TC_42_TR1/WCO_OUT P21.1 82
PWM_40/PWM_41_N/TC_40_TR0/TC_41_TR1/TRIG_DBG[1]/EXT_CLK/ECO_IN P21.2 83
PWM_39/PWM_40_N/TC_39_TR0/TC_40_TR1/ECO_OUT P21.3 84 XRES_L 85 VDDD 86 VSSD 87
VSSD 88 VCCD 89
PWM_37/TC_37_TR0 P21.5 90 PWM_34/TC_34_TR0/CAN1_1_TX P22.0 91
PWM_33/PWM_34_N/TC_33_TR0/TC_34_TR1/CAN1_1_RX P22.1 92
PWM_33_N/TC_33_TR1 P22.2 93 P22.3 94
FAULT_OUT_3/TRIG_IN[30] P23.3 95
PWM_25/TC_25_TR0/TRIG_DBG[0]/SWJ_SWO_TDO/TRIG_IN[31] P23.4 96
PWM_24/PWM_25_N/TC_24_TR0/TC_25_TR1/SWJ_SWCLK_TCLK P23.5 97
PWM_23/PWM_24_N/TC_23_TR0/TC_24_TR1/SWJ_SWDIO_TMS P23.6 98
PWM_22/PWM_23_N/TC_22_TR0/TC_23_TR1/CAL_SUP_NZ/SWJ_SWDOE_TDI/EXT_CLK/HIBERNATE_WAKEUP[1]
P23.7 99
VDDD 100
VSSD 1 PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA
(1)/SCB0_MISO/LIN1_RX P0.0 2
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL (1)/SCB0_MOSI/LIN1_TX
P0.1 3
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/LIN1_EN/CAN0_1_TX
P0.2 4
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX P0.3
5
PWM_7/TC_7_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2]
P2.0 6 PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA
(0)/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1 7
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/SCB7_RTS/SCB7_SCL
(0)/SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4] P2.2 8
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3 9
PWM_1/TC_1_TR0/TRIG_DBG[0] P3.0 10
PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/TRIG_DBG[1] P3.1 11 VDDD 12 VSSD 13
PWM_9/TC_9_TR0 P5.0 14 PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1 P5.1 15
PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1 P5.2 16
PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1 P5.3 17
PWM_M_0/TC_M_0_TR0/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0 P6.0 18
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1
P6.1 19
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/ADC[0]_2
P6.2 20
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAL_SUP_NZ/ADC[0]_3
P6.3 21 PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4 P6.4 22
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5 P6.5 23
VDDD 24 VDDIO_1 25
100-LQFP
75 VDDD 74 P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/TRACE_DATA_3/ADC[2]_7 73 P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/SCB1_SEL3/TRACE_DATA_2/ADC[2]_6 72 P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5 71 P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4 70 P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3 69 P18.2 PWM_55/TC_55_TR0/SCB1_RTS/SCB1_SCL/SCB1_CLK/ADC[2]_2 68 P18.1 PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/ADC[2]_1 67 P18.0 PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0 66 P17.2 PWM_H_2_N 65 P17.1 PWM_H_2/CAN1_1_RX 64 P17.0 CAN1_1_TX 63 P14.3 PWM_51/PWM_50_N/TC_51_TR0/TC_50_TR1/ADC[1]_23 62 P14.2 PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/ADC[1]_22 61 P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/CAN1_0_RX 60 P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/CAN1_0_TX 59 P13.7 PWM_47/TC_47_TR0/TRIG_IN[23] 58 P13.6 PWM_46_N/TC_46_TR1/SCB3_SEL3/TRIG_IN[22] 57 P13.5 PWM_46/TC_46_TR0/SCB3_SEL2/ADC[1]_17 56 P13.4 PWM_45_N/TC_45_TR1/SCB3_SEL1/ADC[1]_16 55 P13.3 PWM_45/TC_45_TR0/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15 54 P13.2 PWM_44_N/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14 53 P13.1 PWM_44/TC_44_TR0/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13 52 P13.0 EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12 51 VSSD
50 VDDIO_2 49 P12.4 PWM_40/PWM_39_N/TC_40_TR0/TC_39_TR1/EXT_MUX[1]_1/ADC[1]_8 48 P12.3 PWM_39/PWM_38_N/TC_39_TR0/TC_38_TR1/EXT_MUX[1]_0/ADC[1]_7 47 P12.2 PWM_38/PWM_37_N/TC_38_TR0/TC_37_TR1/EXT_MUX[1]_EN/ADC[1]_6 46 P12.1 PWM_37/PWM_36_N/TC_37_TR0/TC_36_TR1/TRIG_IN[21]/ADC[1]_5 45 P12.0 PWM_36/TC_36_TR0/TRIG_IN[20]/ADC[1]_4 44 VREFH 43 VDDA 42 VSSA 41 VREFL 40 P11.2 ADC[2]_M 39 P11.1 ADC[1]_M 38 P11.0 ADC[0]_M 37 P8.2 PWM_21/PWM_20_N/TC_21_TR0/TC_20_TR1/LIN2_EN/TRIG_IN[15]/ADC[0]_17 36 P8.1 PWM_20/PWM_19_N/TC_20_TR0/TC_19_TR1/LIN2_TX/CAN0_0_RX/TRIG_IN[14] 35 P8.0 PWM_19/TC_19_TR0/LIN2_RX/CAN0_0_TX 34 P7.5 PWM_17/TC_17_TR0/SCB5_SEL2 33 P7.4 PWM_16_N/TC_16_TR1/SCB5_SEL1/ADC[0]_12 32 P7.3 PWM_16/TC_16_TR0/SCB5_CTS/SCB5_SEL0/ADC[0]_11 31 P7.2 PWM_15_N/TC_15_TR1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN 30 P7.1 PWM_15/PWM_M_4_N/TC_15_TR0/TC_M_4_TR1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_9 29 P7.0 PWM_M_4/TC_M_4_TR0/SCB5_RX/SCB5_MISO/LIN4_RX/ADC[0]_8 28 VCCD 27 VSSD 26 VSSD
Figure 9-2 100-LQFP pin assignment with alternate functions
Datasheet
28
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
VSSD 61 P19.0 62 P19.1 63 P21.0 64 P21.1 65 P21.2 66 P21.3 67 XRES_L 68 VDDD 69 VSSD 70 VSSD 71 VCCD 72 P22.0 73 P22.1 74 P23.3 75 P23.4 76 P23.5 77 P23.6 78 P23.7 79 VDDD 80
40 VDDIO_2 39 P12.3 38 P12.2 37 P12.1 36 P12.0 35 VREFH 34 VDDA 33 VSSA 32 VREFL 31 P11.2 30 P11.1 29 P11.0 28 P8.2 27 P8.1 26 P8.0 25 P7.3 24 P7.2 23 P7.1 22 P7.0 21 VSSD
VSSD 1 P0.0 2 P0.1 3 P0.2 4 P0.3 5 P2.0 6 P2.1 7 P2.2 8 P2.3 9 P5.0 10 P5.1 11
P5.2 12 P5.3 13 P6.0 14 P6.1 15 P6.2 16 P6.3 17 P6.4 18 P6.5 19
VDDIO_1 20
80-LQFP
Figure 9-3 80-LQFP pin assignment
60 VDDD 59 P18.7 58 P18.6 57 P18.5 56 P18.4 55 P18.3 54 P18.2 53 P18.1 52 P18.0 51 P14.1 50 P14.0 49 P13.7 48 P13.6 47 P13.5 46 P13.4 45 P13.3 44 P13.2 43 P13.1 42 P13.0 41 VSSD
Datasheet
29
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
VSSD 61 PWM_50_N/TC_50_TR1/TC_H_0_TR0/FAULT_OUT_2 P19.0 62
PWM_26/TC_26_TR0/TC_H_0_TR1/FAULT_OUT_3 P19.1 63 PWM_42/TC_42_TR0/WCO_IN P21.0
64
PWM_41/PWM_42_N/TC_41_TR0/TC_42_TR1/WCO_OUT P21.1 65
PWM_40/PWM_41_N/TC_40_TR0/TC_41_TR1/TRIG_DBG[1]/EXT_CLK/ECO_IN P21.2 66
PWM_39/PWM_40_N/TC_39_TR0/TC_40_TR1/ECO_OUT P21.3 67 XRES_L 68 VDDD 69 VSSD 70
VSSD 71 VCCD 72
PWM_34/TC_34_TR0/CAN1_1_TX P22.0 73
PWM_33/PWM_34_N/TC_33_TR0/TC_34_TR1/CAN1_1_RX P22.1 74
FAULT_OUT_3/TRIG_IN[30] P23.3 75
PWM_25/TC_25_TR0/TRIG_DBG[0]/SWJ_SWO_TDO/TRIG_IN[31] P23.4 76
PWM_24/PWM_25_N/TC_24_TR0/TC_25_TR1/SWJ_SWCLK_TCLK P23.5 77
PWM_23/PWM_24_N/TC_23_TR0/TC_24_TR1/SWJ_SWDIO_TMS P23.6 78
PWM_22/PWM_23_N/TC_22_TR0/TC_23_TR1/CAL_SUP_NZ/SWJ_SWDOE_TDI/EXT_CLK/HIBERNATE_WAKEUP[1]
P23.7 79
VDDD 80
VSSD 1 PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA
(1)/SCB0_MISO/LIN1_RX P0.0 2
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL (1)/SCB0_MOSI/LIN1_TX
P0.1 3
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/LIN1_EN/CAN0_1_TX
P0.2 4
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX P0.3
5
PWM_7/TC_7_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2]
P2.0 6 PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA
(0)/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1 7
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/SCB7_RTS/SCB7_SCL
(0)/SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4] P2.2 8
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3 9
PWM_9/TC_9_TR0 P5.0 10
PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1 P5.1 11 PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1
P5.2 12 PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1 P5.3 13
PWM_M_0/TC_M_0_TR0/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0 P6.0 14
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1
P6.1 15
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/ADC[0]_2
P6.2 16
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAL_SUP_NZ/ADC[0]_3
P6.3 17 PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4 P6.4 18
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5 P6.5 19
VDDIO_1 20
80-LQFP
60 VDDD 59 P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/TRACE_DATA_3/ADC[2]_7 58 P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/SCB1_SEL3/TRACE_DATA_2/ADC[2]_6 57 P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5 56 P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4 55 P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3 54 P18.2 PWM_55/TC_55_TR0/SCB1_RTS/SCB1_SCL/SCB1_CLK/ADC[2]_2 53 P18.1 PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/ADC[2]_1 52 P18.0 PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0 51 P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/CAN1_0_RX 50 P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/CAN1_0_TX 49 P13.7 PWM_47/TC_47_TR0/TRIG_IN[23] 48 P13.6 PWM_46_N/TC_46_TR1/SCB3_SEL3/TRIG_IN[22] 47 P13.5 PWM_46/TC_46_TR0/SCB3_SEL2/ADC[1]_17 46 P13.4 PWM_45_N/TC_45_TR1/SCB3_SEL1/ADC[1]_16 45 P13.3 PWM_45/TC_45_TR0/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15 44 P13.2 PWM_44_N/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14 43 P13.1 PWM_44/TC_44_TR0/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13 42 P13.0 EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12 41 VSSD
40 VDDIO_2 39 P12.3 PWM_39/PWM_38_N/TC_39_TR0/TC_38_TR1/EXT_MUX[1]_0/ADC[1]_7 38 P12.2 PWM_38/PWM_37_N/TC_38_TR0/TC_37_TR1/EXT_MUX[1]_EN/ADC[1]_6 37 P12.1 PWM_37/PWM_36_N/TC_37_TR0/TC_36_TR1/TRIG_IN[21]/ADC[1]_5 36 P12.0 PWM_36/TC_36_TR0/TRIG_IN[20]/ADC[1]_4 35 VREFH 34 VDDA 33 VSSA 32 VREFL 31 P11.2 ADC[2]_M 30 P11.1 ADC[1]_M 29 P11.0 ADC[0]_M 28 P8.2 PWM_21/PWM_20_N/TC_21_TR0/TC_20_TR1/LIN2_EN/TRIG_IN[15]/ADC[0]_17 27 P8.1 PWM_20/PWM_19_N/TC_20_TR0/TC_19_TR1/LIN2_TX/CAN0_0_RX/TRIG_IN[14] 26 P8.0 PWM_19/TC_19_TR0/LIN2_RX/CAN0_0_TX 25 P7.3 PWM_16/TC_16_TR0/SCB5_CTS/SCB5_SEL0/ADC[0]_11 24 P7.2 PWM_15_N/TC_15_TR1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN 23 P7.1 PWM_15/PWM_M_4_N/TC_15_TR0/TC_M_4_TR1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_9 22 P7.0 PWM_M_4/TC_M_4_TR0/SCB5_RX/SCB5_MISO/LIN4_RX/ADC[0]_8 21 VSSD
Figure 9-4 80-LQFP pin assignment with alternate functions
Datasheet
30
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
VSSD 49 P21.0 50 P21.1 51 P21.2 52 P21.3 53 XRES_L 54 VDDD 55 VSSD 56 VSSD 57 VCCD 58 P22.0 59 P23.3 60 P23.4 61 P23.5 62 P23.6 63 P23.7 64
P0.0 1 P0.1 2 P0.2 3 P0.3 4 P2.0 5 P2.1 6 P5.0 7 P5.1 8 P6.0 9 P6.1 10 P6.2 11 P6.3 12 P6.4 13 P6.5 14 P6.6 15 VDDD 16
64-LQFP
48 VDDD 47 P18.7 46 P18.6 45 P18.5 44 P18.4 43 P18.3 42 P18.1 41 P18.0 40 P14.2 39 P14.1 38 P14.0 37 P13.3 36 P13.2 35 P13.1 34 P13.0 33 VSSD
32 VDDIO_2 31 P12.1 30 P12.0 29 VREFH 28 VDDA 27 VSSA 26 VREFL 25 P11.2 24 P11.1 23 P11.0 22 P8.1 21 P8.0 20 P7.2 19 P7.1 18 P7.0 17 VSSD
Figure 9-5 64-LQFP pin assignment
Datasheet
31
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin assignment
VSSD 49 PWM_42/TC_42_TR0/WCO_IN P21.0 50
PWM_41/PWM_42_N/TC_41_TR0/TC_42_TR1/WCO_OUT P21.1 51
PWM_40/PWM_41_N/TC_40_TR0/TC_41_TR1/TRIG_DBG[1]/EXT_CLK/ECO_IN P21.2 52
PWM_39/PWM_40_N/TC_39_TR0/TC_40_TR1/ECO_OUT P21.3 53
XRES_L 54 VDDD 55 VSSD 56 VSSD 57 VCCD 58
PWM_34/TC_34_TR0/CAN1_1_TX P22.0 59 FAULT_OUT_3/TRIG_IN[30] P23.3 60
PWM_25/TC_25_TR0/TRIG_DBG[0]/SWJ_SWO_TDO/TRIG_IN[31] P23.4 61
PWM_24/PWM_25_N/TC_24_TR0/TC_25_TR1/SWJ_SWCLK_TCLK P23.5 62
PWM_23/PWM_24_N/TC_23_TR0/TC_24_TR1/SWJ_SWDIO_TMS P23.6 63
PWM_22/PWM_23_N/TC_22_TR0/TC_23_TR1/CAL_SUP_NZ/SWJ_SWDOE_TDI/EXT_CLK/HIBERNATE_WAKEUP[1]
P23.7 64
PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA (1)/SCB0_MISO/LIN1_RX
P0.0 1 PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL
(1)/SCB0_MOSI/LIN1_TX P0.1 2
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/LIN1_EN/CAN0_1_TX
P0.2 3
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX P0.3
4
PWM_7/TC_7_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2]
P2.0 5 PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA
(0)/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1 6
PWM_9/TC_9_TR0 P5.0 7 PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1 P5.1 8
PWM_M_0/TC_M_0_TR0/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0 P6.0 9
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1
P6.1 10
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/ADC[0]_2
P6.2 11
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAL_SUP_NZ/ADC[0]_3
P6.3 12 PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4 P6.4 13
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5 P6.5 14
PWM_2_N/TC_2_TR1/SCB4_SEL3/TRIG_IN[8] P6.6 15
VDDD 16
64-LQFP
48 VDDD 47 P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/TRACE_DATA_3/ADC[2]_7 46 P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/SCB1_SEL3/TRACE_DATA_2/ADC[2]_6 45 P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5 44 P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4 43 P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3 42 P18.1 PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/ADC[2]_1 41 P18.0 PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0 40 P14.2 PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/ADC[1]_22 39 P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/CAN1_0_RX 38 P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/CAN1_0_TX 37 P13.3 PWM_45/TC_45_TR0/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15 36 P13.2 PWM_44_N/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14 35 P13.1 PWM_44/TC_44_TR0/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13 34 P13.0 EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12 33 VSSD
32 VDDIO_2 31 P12.1 PWM_37/PWM_36_N/TC_37_TR0/TC_36_TR1/TRIG_IN[21]/ADC[1]_5 30 P12.0 PWM_36/TC_36_TR0/TRIG_IN[20]/ADC[1]_4 29 VREFH 28 VDDA 27 VSSA 26 VREFL 25 P11.2 ADC[2]_M 24 P11.1 ADC[1]_M 23 P11.0 ADC[0]_M 22 P8.1 PWM_20/PWM_19_N/TC_20_TR0/TC_19_TR1/LIN2_TX/CAN0_0_RX/TRIG_IN[14] 21 P8.0 PWM_19/TC_19_TR0/LIN2_RX/CAN0_0_TX 20 P7.2 PWM_15_N/TC_15_TR1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN 19 P7.1 PWM_15/PWM_M_4_N/TC_15_TR0/TC_M_4_TR1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_9 18 P7.0 PWM_M_4/TC_M_4_TR0/SCB5_RX/SCB5_MISO/LIN4_RX/ADC[0]_8 17 VSSD
Figure 9-6 64-LQFP pin assignment with alternate functions
Datasheet
32
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
High-speed I/O matrix connections
10
High-speed I/O matrix connections
Table 10-1 HSIOM connections reference
Name
Number
HSIOM_SEL_GPIO
0
HSIOM_SEL_GPIO_DSI
1
HSIOM_SEL_DSI_DSI
2
HSIOM_SEL_DSI_GPIO
3
HSIOM_SEL_AMUXA
4
HSIOM_SEL_AMUXB
5
HSIOM_SEL_AMUXA_DSI
6
HSIOM_SEL_AMUXB_DSI
7
HSIOM_SEL_ACT_0
8
HSIOM_SEL_ACT_1
9
HSIOM_SEL_ACT_2
10
HSIOM_SEL_ACT_3
11
HSIOM_SEL_DS_0
12
HSIOM_SEL_DS_1
13
HSIOM_SEL_DS_2
14
HSIOM_SEL_DS_3
15
HSIOM_SEL_ACT_4
16
HSIOM_SEL_ACT_5
17
HSIOM_SEL_ACT_6
18
HSIOM_SEL_ACT_7
19
HSIOM_SEL_ACT_8
20
HSIOM_SEL_ACT_9
21
HSIOM_SEL_ACT_10
22
HSIOM_SEL_ACT_11
23
HSIOM_SEL_ACT_12
24
HSIOM_SEL_ACT_13
25
HSIOM_SEL_ACT_14
26
HSIOM_SEL_ACT_15
27
HSIOM_SEL_DS_4
28
HSIOM_SEL_DS_5
29
HSIOM_SEL_DS_6
30
HSIOM_SEL_DS_7
31
GPIO controls ‘out’
Description
Reserved
Active functionality 0 Active functionality 1 Active functionality 2 Active functionality 3 DeepSleep functionality 0 DeepSleep functionality 1 DeepSleep functionality 2 DeepSleep functionality 3 Active functionality 4 Active functionality 5 Active functionality 6 Active functionality 7 Active functionality 8 Active functionality 9 Active functionality 10 Active functionality 11 Active functionality 12 Active functionality 13 Active functionality 14 Active functionality 15 DeepSleep functionality 4 DeepSleep functionality 5 DeepSleep functionality 6 DeepSleep functionality 7
Datasheet
33
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Package pin list and alternate functions
11
Package pin list and alternate functions
Most pins have alternate functionality, as specified in Table 11-1. Port 11 has the following additional features, · Ability to pass full-level analog signals to the SAR without clipping to VDDD in cases where VDDD < VDDA · Ability to simultaneously capture all three ADC signals with highest priority (ADC[0:2]_M) · Lower noise, for the most sensitive sensors
Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O[21]
Name HCon#0[18] I/O Type
Package
100-LQFP 80-LQFP
Pin
Pin
64-LQFP Pin
DeepSleep mapping[20]
HCon#14 DS #0[19]
HCon#29 DS #1
HCon#30 DS #2
Analog/HV
SMART I/O
P0.0 GPIO_ENH
2
2
1
SCB0_MISO
P0.1 GPIO_ENH
3
3
2
SCB0_MOSI
P0.2 GPIO_ENH
4
4
3
SCB0_SCL
SCB0_CLK
P0.3 GPIO_ENH
5
5
4
SCB0_SDA
SCB0_SEL0
P2.0 GPIO_STD
6
6
5
SWJ_TRSTN
SCB0_SEL1
P2.1 GPIO_STD
7
7
6
SCB0_SEL2
P2.2 GPIO_STD
8
8
NA
SCB0_SEL3
P2.3 GPIO_STD
9
9
NA
P3.0 GPIO_STD
10
NA
NA
P3.1 GPIO_STD
11
NA
NA
P5.0 GPIO_STD
14
10
7
P5.1 GPIO_STD
15
11
8
P5.2 GPIO_STD
16
12
NA
P5.3 GPIO_STD
17
13
NA
P6.0 GPIO_STD
18
14
9
ADC[0]_0
P6.1 GPIO_STD
19
15
10
ADC[0]_1
P6.2 GPIO_STD
20
16
11
ADC[0]_2
P6.3 GPIO_STD
21
17
12
ADC[0]_3
P6.4 GPIO_STD
22
18
13
ADC[0]_4
P6.5 GPIO_STD
23
19
14
ADC[0]_5
P6.6 GPIO_STD
NA
NA
15
P7.0 GPIO_STD
29
22
18
ADC[0]_8
P7.1 GPIO_STD
30
23
19
ADC[0]_9
P7.2 GPIO_STD
31
24
20
P7.3 GPIO_STD
32
25
NA
ADC[0]_11
P7.4 GPIO_STD
33
NA
NA
ADC[0]_12
P7.5 GPIO_STD
34
NA
NA
P8.0 GPIO_STD
35
26
21
P8.1 GPIO_STD
36
27
22
P8.2 GPIO_STD
37
28
NA
ADC[0]_17
Notes 18.HCon refers to High Speed I/O matrix connection reference as per
Table 10-1. 19.DeepSleep ordering (DS #0, DS #1, DS #2) does not have any
impact on choosing any alternate functions; the HSIOM module handles
the individual alternate function assignment. 20.All port pin functions
available in DeepSleep mode are also available in Active mode. 21.Refer to
Table 14-1 for more information on pin multiplexer abbreviations used.
Datasheet
34
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Package pin list and alternate functions
Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O[21]
Name HCon#0[18] I/O Type
Package
100-LQFP 80-LQFP
Pin
Pin
64-LQFP Pin
DeepSleep mapping[20]
HCon#14 DS #0[19]
HCon#29 DS #1
HCon#30 DS #2
Analog/HV
SMART I/O
P11.0 GPIO_STD
38
29
23
ADC[0]_M
P11.1 GPIO_STD
39
30
24
ADC[1]_M
P11.2 GPIO_STD
40
31
25
ADC[2]_M
P12.0 GPIO_STD
45
36
30
ADC[1]_4
SMARTIO12_0
P12.1 GPIO_STD
46
37
31
ADC[1]_5
SMARTIO12_1
P12.2 GPIO_STD
47
38
NA
ADC[1]_6
SMARTIO12_2
P12.3 GPIO_STD
48
39
NA
ADC[1]_7
SMARTIO12_3
P12.4 GPIO_STD
49
NA
NA
ADC[1]_8
SMARTIO12_4
P13.0 GPIO_STD
52
42
34
ADC[1]_12
SMARTIO13_0
P13.1 GPIO_STD
53
43
35
ADC[1]_13
SMARTIO13_1
P13.2 GPIO_STD
54
44
36
ADC[1]_14
SMARTIO13_2
P13.3 GPIO_STD
55
45
37
ADC[1]_15
SMARTIO13_3
P13.4 GPIO_STD
56
46
NA
ADC[1]_16
SMARTIO13_4
P13.5 GPIO_STD
57
47
NA
ADC[1]_17
SMARTIO13_5
P13.6 GPIO_STD
58
48
NA
SMARTIO13_6
P13.7 GPIO_STD
59
49
NA
SMARTIO13_7
P14.0 GPIO_STD
60
50
38
SMARTIO14_0
P14.1 GPIO_STD
61
51
39
SMARTIO14_1
P14.2 GPIO_STD
62
NA
40
ADC[1]_22
SMARTIO14_2
P14.3 GPIO_STD
63
NA
NA
ADC[1]_23
P17.0 GPIO_STD
64
NA
NA
P17.1 GPIO_STD
65
NA
NA
P17.2 GPIO_STD
66
NA
NA
P18.0 GPIO_STD
67
52
41
ADC[2]_0
P18.1 GPIO_STD
68
53
42
ADC[2]_1
P18.2 GPIO_STD
69
54
NA
ADC[2]_2
P18.3 GPIO_STD
70
55
43
ADC[2]_3
P18.4 GPIO_STD
71
56
44
ADC[2]_4
P18.5 GPIO_STD
72
57
45
ADC[2]_5
P18.6 GPIO_STD
73
58
46
ADC[2]_6
P18.7 GPIO_STD
74
59
47
ADC[2]_7
P19.0 GPIO_STD
77
62
NA
P19.1 GPIO_STD
78
63
NA
P19.2 GPIO_STD
79
NA
NA
P19.3 GPIO_STD
80
P21.0 GPIO_STD
81
P21.1 GPIO_STD
82
P21.2 GPIO_STD
83
P21.3 GPIO_STD
84
NA
NA
64
50
65
51
66
52
67
53
WCO_IN[22] WCO_OUT[22] ECO_IN[22] ECO_OUT[22]
P21.5 GPIO_STD
90
NA
NA
P22.0 GPIO_STD
91
73
59
Notes 22.I/O pins that support an oscillator function (WCO or ECO) must be configured for high-impedance if the oscillator is enabled. 23.This I/O has increased leakage to ground when the VDDD supply is below the POR threshold.
Datasheet
35
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Power pin assignments
Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O[21]
Name HCon#0[18] I/O Type
Package
100-LQFP 80-LQFP
Pin
Pin
64-LQFP Pin
DeepSleep mapping[20]
HCon#14 DS #0[19]
HCon#29 DS #1
HCon#30 DS #2
Analog/HV
SMART I/O
P22.1 GPIO_STD
92
74
NA
P22.2 GPIO_STD
93
NA
NA
P22.3 GPIO_STD
94
NA
NA
P23.3 GPIO_STD
95
75
60
P23.4 GPIO_STD
96
P23.5 GPIO_STD
97
76
61
77
62
SWJSWO TDO
SWJ_SWCLK_TCLK
P23.6 GPIO_STD
98
78
63
SWJ_SWDIO_TMS
P23.7 GPIO_STD
99
79
64
SWJ_SWDOE_TDI
HIBERNATE_WAKEUP[1]
12
Power pin assignments
Table 12-1 Power pin assignments
Name
64-LQFP
Packages 80-LQFP
VDDD
55, 48, 16
80, 69, 60
VSSD
57, 56, 49, 33, 17 71, 70, 61, 41, 21, 1
VDDIO_1
NA
20
VDDIO_2
32
40
VCCD[24]
58
72
VREFH
29
35
VREFL
26
32
VDDA
28
34
VSSA
27
33
XRES_L
54
68
100-LQFP
Remarks
100, 86, 75, 24, 12 Main digital supply
88, 87, 76, 51, 27, 26, Main digital ground 13, 1
25 50 89, 28
I/O supply for analog I/Os (except analog I/Os on VDDA)
I/O supply for analog I/Os (except analog I/Os on VDDA), P11
Main regulated supply. Driven by LDO regulator
44
High reference voltage for SAR ADCs
41
Low reference voltage for SAR ADCs
43
Main analog supply for SAR ADCs
42
Main analog ground
85
Active LOW external reset input
Note 24.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 27-2).
Datasheet
36
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Alternate function pin assignments
Datasheet
13
Alternate function pin assignments
Table 13-1 Alternate pin functions in Active mode
Name HCon#8[25] ACT #0[26] P0.0 PWM0_18 P0.1 PWM0_17 P0.2 PWM0_14 P0.3 PWM0_13 P2.0 PWM0_7 P2.1 PWM0_6 P2.2 PWM0_5 P2.3 PWM0_4 P3.0 PWM0_1 P3.1 PWM0_0 P5.0 PWM0_9 P5.1 PWM0_10 P5.2 PWM0_11 P5.3 PWM0_12 P6.0 PWM0_M_0 P6.1 PWM0_0 P6.2 PWM0_M_1 P6.3 PWM0_1 P6.4 PWM0_M_2 P6.5 PWM0_2 P6.6 P7.0 PWM0_M_4 P7.1 PWM0_15 P7.2
HCon#9 ACT #1
PWM0_22_N PWM0_18_N PWM0_17_N PWM0_14_N
PWM0_7_N PWM0_6_N PWM0_5_N
PWM0_1_N
PWM0_9_N PWM0_10_N PWM0_11_N
PWM0_M_0_N PWM0_0_N PWM0_M_1_N PWM0_1_N PWM0_M_2_N PWM0_2_N
PWM0_M_4_N PWM0_15_N
HCon#10 ACT #2
TC0_18_TR0 TC0_17_TR0 TC0_14_TR0 TC0_13_TR0 TC0_7_TR0 TC0_6_TR0 TC0_5_TR0
TC0_4_TR0 TC0_1_TR0 TC0_0_TR0 TC0_9_TR0 TC0_10_TR0 TC0_11_TR0 TC0_12_TR0
TC0_M_0_TR0 TC0_0_TR0 TC0_M_1_TR0 TC0_1_TR0 TC0_M_2_TR0 TC0_2_TR0
TC0_M_4_TR0 TC0_15_TR0
HCon#11 ACT #3
TC0_22_TR1 TC0_18_TR1 TC0_17_TR1 TC0_14_TR1
TC0_7_TR1 TC0_6_TR1 TC0_5_TR1
TC0_1_TR1
TC0_9_TR1 TC0_10_TR1 TC0_11_TR1
TC0_M_0_TR1 TC0_0_TR1 TC0_M_1_TR1 TC0_1_TR1 TC0_M_2_TR1 TC0_2_TR1
TC0_M_4_TR1 TC0_15_TR1
HCon#16 ACT #4
Active mapping
HCon#17 HCon#18
ACT #5
ACT #6
SCB0_RX
SCB7_SDA (1)
SCB0_TX
SCB7_SCL (1)
SCB0_RTS
SCB0_CTS
SCB7_RX
SCB7_TX
SCB7_SDA (0)
SCB7_RTS
SCB7_SCL (0)
SCB7_CTS
HCon#19 ACT #7
SCB7_MISO SCB7_MOSI SCB7_CLK SCB7_SEL0
HCon#20 HCon#21
ACT #8
ACT #9
LIN1_RX
LIN1_TX
LIN1_EN CAN0_1_TX
CAN0_1_RX
LIN0_RX CAN0_0_TX
LIN0_TX CAN0_0_RX
LIN0_EN
HCon#26 ACT #14
HCon#27 ACT #15
TRIG_IN[2] TRIG_IN[3] TRIG_IN[4] TRIG_IN[5]
TRIG_DBG[0] TRIG_DBG[1]
SCB4_RX SCB4_TX SCB4_RTS SCB4_CTS
SCB4_SDA SCB4_SCL
SCB5_RX SCB5_TX SCB5_RTS
SCB5_SDA SCB5_SCL
SCB4_MISO SCB4_MOSI SCB4_CLK SCB4_SEL0 SCB4_SEL1 SCB4_SEL2 SCB4_SEL3 SCB5_MISO SCB5_MOSI SCB5_CLK
LIN3_RX LIN3_TX LIN3_EN LIN4_RX LIN4_TX LIN4_EN
LIN4_RX LIN4_TX LIN4_EN
CAL_SUP_NZ TRIG_IN[8]
37
002-25756 Rev. *C
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Notes 25.High Speed I/O matrix connection (HCon) reference as per Table 10-1. 26.Active Mode ordering (ACT#0, ACT#1, and so on) does not have any impact on configuring alternate functions; the HSIOM module handles the alternate function assignments. 27.Refer to Table 14-1 for more information on pin multiplexer abbreviations used. 28.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group “n”.
2022-10-07
002-25756 Rev. *C
38
Datasheet
Table 13-1 Alternate pin functions in Active mode (continued)
Name
HCon#8[25] ACT #0[26]
P7.3 PWM0_16
P7.4
P7.5 PWM0_17
P8.0 PWM0_19
P8.1 PWM0_20
P8.2 PWM0_21
P11.0
P11.1
P11.2
P12.0 PWM0_36
P12.1 PWM0_37
P12.2 PWM0_38
P12.3 PWM0_39
P12.4 PWM0_40
P13.0
P13.1 PWM0_44
P13.2
P13.3 PWM0_45
P13.4
P13.5 PWM0_46
P13.6
P13.7 PWM0_47
P14.0 PWM0_48
P14.1 PWM0_49
P14.2 PWM0_50
P14.3 PWM0_51
P17.0
P17.1
P17.2
P18.0
P18.1
HCon#9 ACT #1
PWM0_16_N
PWM0_19_N PWM0_20_N
PWM0_36_N PWM0_37_N PWM0_38_N PWM0_39_N
PWM0_44_N PWM0_45_N PWM0_46_N PWM0_47_N PWM0_48_N PWM0_49_N PWM0_50_N
HCon#10 ACT #2
TC0_16_TR0
TC0_17_TR0 TC0_19_TR0 TC0_20_TR0 TC0_21_TR0
HCon#11 ACT #3
TC0_16_TR1
TC0_19_TR1 TC0_20_TR1
HCon#16 ACT #4
TC0_36_TR0 TC0_37_TR0 TC0_38_TR0 TC0_39_TR0 TC0_40_TR0
TC0_44_TR0
TC0_45_TR0
TC0_46_TR0
TC0_47_TR0 TC0_48_TR0 TC0_49_TR0 TC0_50_TR0 TC0_51_TR0
TC0_36_TR1 TC0_37_TR1 TC0_38_TR1 TC0_39_TR1
TC0_44_TR1
TC0_45_TR1
TC0_46_TR1
TC0_47_TR1 TC0_48_TR1 TC0_49_TR1 TC0_50_TR1
EXT_MUX[1]_EN EXT_MUX[1]_0 EXT_MUX[1]_1 EXT_MUX[2]_0 EXT_MUX[2]_1 EXT_MUX[2]_2 EXT_MUX[2]_EN
PWM0_H_2 PWM0_H_2_N PWM0_H_0 PWM0_H_0_N
Active mapping
HCon#17 HCon#18
ACT #5
ACT #6
SCB5_CTS
HCon#19 ACT #7
SCB5_SEL0 SCB5_SEL1 SCB5_SEL2
HCon#20 ACT #8
HCon#21 ACT #9
LIN2_RX LIN2_TX LIN2_EN
CAN0_0_TX CAN0_0_RX
HCon#26 ACT #14
TRIG_IN[14] TRIG_IN[15]
HCon#27 ACT #15
TRIG_IN[20] TRIG_IN[21]
SCB3_RX SCB3_TX SCB3_RTS SCB3_CTS
SCB3_SDA SCB3_SCL
SCB3_MISO SCB3_MOSI SCB3_CLK SCB3_SEL0 SCB3_SEL1 SCB3_SEL2 SCB3_SEL3
SCB1_RX SCB1_TX
SCB1_SDA
SCB1_MISO SCB1_MOSI
CAN1_0_TX CAN1_0_RX
TRIG_IN[22] TRIG_IN[23]
CAN1_1_TX CAN1_1_RX
FAULT_OUT_0 FAULT_OUT_1
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Alternate function pin assignments
2022-10-07
002-25756 Rev. *C
39
Datasheet
Table 13-1 Alternate pin functions in Active mode (continued)
Name
HCon#8[25] ACT #0[26]
P18.2 PWM0_55
P18.3 PWM0_54
P18.4 PWM0_53
P18.5 PWM0_52
P18.6 PWM0_51
P18.7 PWM0_50
P19.0
P19.1 PWM0_26
P19.2
P19.3
P21.0 PWM0_42
P21.1 PWM0_41
P21.2 PWM0_40
P21.3 PWM0_39
P21.5 PWM0_37
P22.0 PWM0_34
P22.1 PWM0_33
P22.2
P22.3
P23.3
P23.4 PWM0_25
P23.5 PWM0_24
P23.6 PWM0_23
P23.7 PWM0_22
HCon#9 ACT #1
PWM0_55_N PWM0_54_N PWM0_53_N PWM0_52_N PWM0_51_N PWM0_50_N
PWM0_26_N
PWM0_42_N PWM0_41_N PWM0_40_N
PWM0_34_N PWM0_33_N
PWM0_25_N PWM0_24_N PWM0_23_N
HCon#10 ACT #2
TC0_55_TR0 TC0_54_TR0 TC0_53_TR0 TC0_52_TR0 TC0_51_TR0 TC0_50_TR0
TC0_26_TR0
HCon#11 ACT #3
TC0_55_TR1 TC0_54_TR1 TC0_53_TR1 TC0_52_TR1 TC0_51_TR1 TC0_50_TR1
TC0_26_TR1
HCon#16 ACT #4
PWM0_H_2 PWM0_H_2_N
TC0_H_0_TR0 TC0_H_0_TR1
TC0_42_TR0 TC0_41_TR0 TC0_40_TR0 TC0_39_TR0 TC0_37_TR0 TC0_34_TR0 TC0_33_TR0
TC0_42_TR1 TC0_41_TR1 TC0_40_TR1
TC0_34_TR1 TC0_33_TR1
TC0_25_TR0 TC0_24_TR0 TC0_23_TR0 TC0_22_TR0
TC0_25_TR1 TC0_24_TR1 TC0_23_TR1
Active mapping
HCon#17 HCon#18
ACT #5
ACT #6
SCB1_RTS
SCB1_SCL
SCB1_CTS
HCon#19 ACT #7
SCB1_CLK SCB1_SEL0 SCB1_SEL1 SCB1_SEL2 SCB1_SEL3
HCon#20 ACT #8
HCon#21 ACT #9
HCon#26 ACT #14
HCon#27 ACT #15
TRIG_IN[28] TRIG_IN[29]
TRACE_CLOCK TRACE_DATA_0 TRACE_DATA_1 TRACE_DATA_2 TRACE_DATA_3 FAULT_OUT_2 FAULT_OUT_3
EXT_CLK
TRIG_DBG[1]
CAN1_1_TX CAN1_1_RX
TRIG_IN[30] TRIG_IN[31]
FAULT_OUT_3 TRIG_DBG[0]
EXT_CLK
CAL_SUP_NZ
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Alternate function pin assignments
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin mux descriptions
14
Pin mux descriptions
Table 14-1 Pin mux descriptions
Sl. No.
Pin
Module
Description
1 PWMx_y
TCPWM TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR line out, x-TCPWM block, y-counter number
2 PWMx_y_N
TCPWM TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR complementary line out (N), x-TCPWM block, y-counter number
3 PWMx_M_y
TCPWM TCPWM 16-bit PWM with motor control line out, x-TCPWM block, y-counter number
4 PWMx_M_y_N
TCPWM TCPWM 16-bit PWM with motor control complementary line out (N), x-TCPWM block, y-counter number
5 PWMx_H_y
TCPWM TCPWM 32-bit PWM, PWM_DT and PWM_PR line out, x-TCPWM block, y-counter number
6 PWMx_H_y_N
TCPWM TCPWM 32-bit PWM, PWM_DT and PWM_PR complementary line out (N), x-TCPWM block, y-counter number
7 TCx_y_TRz
TCPWM TCPWM 16-bit dedicated counter input triggers, x-TCPWM block, y-counter number, z-trigger number
8 TCx_M_y_TRz
TCPWM TCPWM 16-bit dedicated counter input triggers with motor control, x-TCPWM block, y-counter number, z-trigger number
9 TCx_H_y_TRz
TCPWM TCPWM 32-bit dedicated counter input triggers, x-TCPWM block, y-counter number, z-trigger number
10 SCBx_RX
SCB
UART Receive, x-SCB block
11 SCBx_TX
SCB
UART Transmit, x-SCB block
12 SCBx_RTS
SCB
UART Request to Send (Handshake), x-SCB block
13 SCBx_CTS
SCB
UART Clear to Send (Handshake), x-SCB block
14 SCBx_SDA
SCB
I2C Data line, x-SCB block
15 SCBx_SCL
SCB
I2C Clock line, x-SCB block
16 SCBx_MISO
SCB
SPI Master Input Slave Output, x-SCB block
17 SCBx_MOSI
SCB
SPI Master Output Slave Input, x-SCB block
18 SCBx_CLK
SCB
SPI Serial Clock, x-SCB block
19 SCBx_SELy
SCB
SPI Slave Select, x-SCB block, y-select line
20 LINx_RX
LIN
LIN Receive line, x-LIN block
21 LINx_TX
LIN
LIN Transmit line, x-LIN block
22 LINx_EN
LIN
LIN Enable line, x-LIN block
23 CANx_y_TX
CANFD CAN Transmit line, x-CAN block, y-channel number
24 CANx_y_RX
CANFD CAN Receive line, x-CAN block, y-channel number
25 CAL_SUP_NZ
CPUSS ETAS Calibration support line
26 FAULT_OUT_x
SRSS
Fault output line x-0 to 3
27 TRACE_DATA_x
SRSS
Trace dataout line x-0 to 3
28 TRACE_CLOCK
SRSS
Trace clock line
29 RTC_CAL
SRSS RTC RTC calibration clock input
30 SWJ_TRSTN
SRSS
JTAG Test reset line (Active low)
31 SWJ_SWO_TDO
SRSS
JTAG Test data output/SWO (Serial Wire Output)
Datasheet
40
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Pin mux descriptions
Table 14-1 Pin mux descriptions (continued)
Sl. No.
Pin
Module
Description
32 SWJ_SWCLK_TCLK SRSS
JTAG Test clock/SWD clock (Serial Wire Clock)
33 SWJ_SWDIO_TMS SRSS
JTAG Test mode select/SWD data (Serial Wire Data Input/Output)
34 SWJ_SWDOE_TDI
SRSS
JTAG Test data input
35 HIBERNATE_WAKEUP[x]
SRSS
Hibernate wakeup line x-0 to 1
36 ADC[x]_y
PASS SAR SAR, channel, x-SAR number, y-channel number
37 ADC[x]_M
PASS SAR SAR motor control input, x-SAR number
38 EXT_MUX[x]_y
PASS SAR External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2
39 EXT_MUX[x]_EN
PASS SAR External SAR MUX enable line
Datasheet
41
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
15
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources
Interrupt
Source
Power Mode
Description
0
cpuss_interrupts_ipc_0_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #0
1
cpuss_interrupts_ipc_1_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #1
2
cpuss_interrupts_ipc_2_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #2
3
cpuss_interrupts_ipc_3_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #3
4
cpuss_interrupts_ipc_4_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #4
5
cpuss_interrupts_ipc_5_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #5
6
cpuss_interrupts_ipc_6_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #6
7
cpuss_interrupts_ipc_7_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #7
8
cpuss_interrupts_fault_0_IRQn
DeepSleep CPUSS Fault Structure #0 Interrupt
9
cpuss_interrupts_fault_1_IRQn
DeepSleep CPUSS Fault Structure #1 Interrupt
10
cpuss_interrupts_fault_2_IRQn
DeepSleep CPUSS Fault Structure #2 Interrupt
11
cpuss_interrupts_fault_3_IRQn
DeepSleep CPUSS Fault Structure #3 Interrupt
12 srss_interrupt_backup_IRQn DeepSleep BACKUP domain Interrupt
13
srss_interrupt_mcwdt_0_IRQn
DeepSleep Multi Counter Watchdog Timer #0 interrupt
14
srss_interrupt_mcwdt_1_IRQn
DeepSleep Multi Counter Watchdog Timer #1 interrupt
15 srss_interrupt_wdt_IRQn
DeepSleep Hardware Watchdog Timer interrupt
16 srss_interrupt_IRQn
DeepSleep Other combined Interrupts for SRSS (LVD, CLKCAL)
17 scb_0_interrupt_IRQn
DeepSleep SCB0 interrupt (DeepSleep capable)
18
evtgen_0_interrupt_dpslp_IRQn
DeepSleep Event gen DeepSleep domain interrupt
19
ioss_interrupt_vdd_IRQn
DeepSleep
I/O Supply (VDDIO, VDDA, VDDD) state change Interrupt
20
ioss_interrupt_gpio_IRQn
DeepSleep
Consolidated Interrupt for GPIO_STD and GPIO_ENH, All Ports
21 ioss_interrupts_gpio_0_IRQn DeepSleep GPIO_ENH Port #0 Interrupt
23 ioss_interrupts_gpio_2_IRQn DeepSleep GPIO_STD Port #2 Interrupt
24 ioss_interrupts_gpio_3_IRQn DeepSleep GPIO_STD Port #3 Interrupt
26 ioss_interrupts_gpio_5_IRQn DeepSleep GPIO_STD Port #5 Interrupt
27 ioss_interrupts_gpio_6_IRQn DeepSleep GPIO_STD Port #6 Interrupt
28 ioss_interrupts_gpio_7_IRQn DeepSleep GPIO_STD Port #7 Interrupt
29 ioss_interrupts_gpio_8_IRQn DeepSleep GPIO_STD Port #8 Interrupt
32 ioss_interrupts_gpio_11_IRQn DeepSleep GPIO_STD Port #11 Interrupt
33 ioss_interrupts_gpio_12_IRQn DeepSleep GPIO_STD Port #12 Interrupt
34 ioss_interrupts_gpio_13_IRQn DeepSleep GPIO_STD Port #13 Interrupt
35 ioss_interrupts_gpio_14_IRQn DeepSleep GPIO_STD Port #14 Interrupt
Datasheet
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Description
38 ioss_interrupts_gpio_17_IRQn DeepSleep GPIO_STD Port #17 Interrupt
39 ioss_interrupts_gpio_18_IRQn DeepSleep GPIO_STD Port #18 Interrupt
40 ioss_interrupts_gpio_19_IRQn DeepSleep GPIO_STD Port #19 Interrupt
42 ioss_interrupts_gpio_21_IRQn DeepSleep GPIO_STD Port #21 Interrupt
43 ioss_interrupts_gpio_22_IRQn DeepSleep GPIO_STD Port #22 Interrupt
44 ioss_interrupts_gpio_23_IRQn DeepSleep GPIO_STD Port #23 Interrupt
45 cpuss_interrupt_crypto_IRQn Active Crypto Accelerator Interrupt
46 cpuss_interrupt_fm_IRQn
Active Flash Macro Interrupt
47
cpuss_interrupts_cm4_fp_IRQn
Active CM4 Floating Point operation fault
48
cpuss_interrupts_cm0_cti_0_IRQn
Active CM0+ CTI (Cross Trigger Interface) #0
49
cpuss_interrupts_cm0_cti_1_IRQn
Active CM0+ CTI #1
50
cpuss_interrupts_cm4_cti_0_IRQn
Active CM4 CTI #0
51
cpuss_interrupts_cm4_cti_1_IRQn
Active CM4 CTI #1
52 evtgen_0_interrupt_IRQn
Active Event gen Active domain interrupt
53
canfd_0_interrupt0_IRQn
Active
CAN0, Consolidated Interrupt #0 for all three channels
54
canfd_0_interrupt1_IRQn
Active
CAN0, Consolidated Interrupt #1 for all three channels
55
canfd_1_interrupt0_IRQn
Active
CAN1, Consolidated Interrupt #0 for all three channels
56
canfd_1_interrupt1_IRQn
Active
CAN1, Consolidated Interrupt #1 for all three channels
57 canfd_0_interrupts0_0_IRQn
Active CAN0, Interrupt #0, Channel #0
58 canfd_0_interrupts0_1_IRQn
Active CAN0, Interrupt #0, Channel #1
60 canfd_0_interrupts1_0_IRQn
Active CAN0, Interrupt #1, Channel #0
61 canfd_0_interrupts1_1_IRQn
Active CAN0, Interrupt #1, Channel #1
63 canfd_1_interrupts0_0_IRQn
Active CAN1, Interrupt #0, Channel #0
64 canfd_1_interrupts0_1_IRQn
Active CAN1, Interrupt #0, Channel #1
66 canfd_1_interrupts1_0_IRQn
Active CAN1, Interrupt #1, Channel #0
67 canfd_1_interrupts1_1_IRQn
Active CAN1, Interrupt #1, Channel #1
69 lin_0_interrupts_0_IRQn
Active LIN0, Channel #0 Interrupt
70 lin_0_interrupts_1_IRQn
Active LIN0, Channel #1 Interrupt
71 lin_0_interrupts_2_IRQn
Active LIN0, Channel #2 Interrupt
72 lin_0_interrupts_3_IRQn
Active LIN0, Channel #3 Interrupt
73 lin_0_interrupts_4_IRQn
Active LIN0, Channel #4 Interrupt
77 scb_1_interrupt_IRQn
Active SCB1 Interrupt
79 scb_3_interrupt_IRQn
Active SCB3 Interrupt
Datasheet
43
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2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Description
80 scb_4_interrupt_IRQn
Active SCB4 Interrupt
81 scb_5_interrupt_IRQn
Active SCB5 Interrupt
83 scb_7_interrupt_IRQn
Active SCB7 Interrupt
84
pass_0_interrupts_sar_0_IRQn
Active SAR0, Logical Channel #0 Interrupt
85
pass_0_interrupts_sar_1_IRQn
Active SAR0, Logical Channel #1 Interrupt
86
pass_0_interrupts_sar_2_IRQn
Active SAR0, Logical Channel #2 Interrupt
87
pass_0_interrupts_sar_3_IRQn
Active SAR0, Logical Channel #3 Interrupt
88
pass_0_interrupts_sar_4_IRQn
Active SAR0, Logical Channel #4 Interrupt
89
pass_0_interrupts_sar_5_IRQn
Active SAR0, Logical Channel #5 Interrupt
92
pass_0_interrupts_sar_8_IRQn
Active SAR0, Logical Channel #8 Interrupt
93
pass_0_interrupts_sar_9_IRQn
Active SAR0, Logical Channel #9 Interrupt
95
pass_0_interrupts_sar_11_IRQn
Active SAR0, Logical Channel #11 Interrupt
96
pass_0_interrupts_sar_12_IRQn
Active SAR0, Logical Channel #12 Interrupt
101
pass_0_interrupts_sar_17_IRQn
Active SAR0, Logical Channel #17 Interrupt
112
pass_0_interrupts_sar_36_IRQn
Active SAR1, Logical Channel #4 Interrupt
113
pass_0_interrupts_sar_37_IRQn
Active SAR1, Logical Channel #5 Interrupt
114
pass_0_interrupts_sar_38_IRQn
Active SAR1, Logical Channel #6 Interrupt
115
pass_0_interrupts_sar_39_IRQn
Active SAR1, Logical Channel #7 Interrupt
116
pass_0_interrupts_sar_40_IRQn
Active SAR1, Logical Channel #8 Interrupt
120
pass_0_interrupts_sar_44_IRQn
Active SAR1, Logical Channel #12 Interrupt
121
pass_0_interrupts_sar_45_IRQn
Active SAR1, Logical Channel #13 Interrupt
122
pass_0_interrupts_sar_46_IRQn
Active SAR1, Logical Channel #14 Interrupt
123
pass_0_interrupts_sar_47_IRQn
Active SAR1, Logical Channel #15 Interrupt
124
pass_0_interrupts_sar_48_IRQn
Active SAR1, Logical Channel #16 Interrupt
Datasheet
44
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Description
125
pass_0_interrupts_sar_49_IRQn
Active SAR1, Logical Channel #17 Interrupt
130
pass_0_interrupts_sar_54_IRQn
Active SAR1, Logical Channel #22 Interrupt
131
pass_0_interrupts_sar_55_IRQn
Active SAR1, Logical Channel #23 Interrupt
140
pass_0_interrupts_sar_64_IRQn
Active SAR2, Logical Channel #0 Interrupt
141
pass_0_interrupts_sar_65_IRQn
Active SAR2, Logical Channel #1 Interrupt
142
pass_0_interrupts_sar_66_IRQn
Active SAR2, Logical Channel #2 Interrupt
143
pass_0_interrupts_sar_67_IRQn
Active SAR2, Logical Channel #3 Interrupt
144
pass_0_interrupts_sar_68_IRQn
Active SAR2, Logical Channel #4 Interrupt
145
pass_0_interrupts_sar_69_IRQn
Active SAR2, Logical Channel #5 Interrupt
146
pass_0_interrupts_sar_70_IRQn
Active SAR2, Logical Channel #6 Interrupt
147
pass_0_interrupts_sar_71_IRQn
Active SAR2, Logical Channel #7 Interrupt
148
cpuss_interrupts_dmac_0_IRQn
Active CPUSS M-DMA0, Channel #0 Interrupt
149
cpuss_interrupts_dmac_1_IRQn
Active CPUSS M-DMA0, Channel #1 Interrupt
152
cpuss_interrupts_dw0_0_IRQn
Active CPUSS P-DMA0, Channel #0 Interrupt
153
cpuss_interrupts_dw0_1_IRQn
Active CPUSS P-DMA0, Channel #1 Interrupt
154
cpuss_interrupts_dw0_2_IRQn
Active CPUSS P-DMA0, Channel #2 Interrupt
155
cpuss_interrupts_dw0_3_IRQn
Active CPUSS P-DMA0, Channel #3 Interrupt
156
cpuss_interrupts_dw0_4_IRQn
Active CPUSS P-DMA0, Channel #4 Interrupt
157
cpuss_interrupts_dw0_5_IRQn
Active CPUSS P-DMA0, Channel #5 Interrupt
158
cpuss_interrupts_dw0_6_IRQn
Active CPUSS P-DMA0, Channel #6 Interrupt
159
cpuss_interrupts_dw0_7_IRQn
Active CPUSS P-DMA0, Channel #7 Interrupt
160
cpuss_interrupts_dw0_8_IRQn
Active CPUSS P-DMA0, Channel #8 Interrupt
161
cpuss_interrupts_dw0_9_IRQn
Active CPUSS P-DMA0, Channel #9 Interrupt
Datasheet
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002-25756 Rev. *C
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Description
162
cpuss_interrupts_dw0_10_IRQn
Active CPUSS P-DMA0, Channel #10 Interrupt
163
cpuss_interrupts_dw0_11_IRQn
Active CPUSS P-DMA0, Channel #11 Interrupt
164
cpuss_interrupts_dw0_12_IRQn
Active CPUSS P-DMA0, Channel #12 Interrupt
165
cpuss_interrupts_dw0_13_IRQn
Active CPUSS P-DMA0, Channel #13 Interrupt
166
cpuss_interrupts_dw0_14_IRQn
Active CPUSS P-DMA0, Channel #14 Interrupt
167
cpuss_interrupts_dw0_15_IRQn
Active CPUSS P-DMA0, Channel #15 Interrupt
168
cpuss_interrupts_dw0_16_IRQn
Active CPUSS P-DMA0, Channel #16 Interrupt
169
cpuss_interrupts_dw0_17_IRQn
Active CPUSS P-DMA0, Channel #17 Interrupt
170
cpuss_interrupts_dw0_18_IRQn
Active CPUSS P-DMA0, Channel #18 Interrupt
171
cpuss_interrupts_dw0_19_IRQn
Active CPUSS P-DMA0, Channel #19 Interrupt
172
cpuss_interrupts_dw0_20_IRQn
Active CPUSS P-DMA0, Channel #20 Interrupt
173
cpuss_interrupts_dw0_21_IRQn
Active CPUSS P-DMA0, Channel #21 Interrupt
177
cpuss_interrupts_dw0_25_IRQn
Active CPUSS P-DMA0, Channel #25 Interrupt
178
cpuss_interrupts_dw0_26_IRQn
Active CPUSS P-DMA0, Channel #26 Interrupt
179
cpuss_interrupts_dw0_27_IRQn
Active CPUSS P-DMA0, Channel #27 Interrupt
180
cpuss_interrupts_dw0_28_IRQn
Active CPUSS P-DMA0, Channel #28 Interrupt
181
cpuss_interrupts_dw0_29_IRQn
Active CPUSS P-DMA0, Channel #29 Interrupt
182
cpuss_interrupts_dw0_30_IRQn
Active CPUSS P-DMA0, Channel #30 Interrupt
185
cpuss_interrupts_dw0_33_IRQn
Active CPUSS P-DMA0, Channel #33 Interrupt
186
cpuss_interrupts_dw0_34_IRQn
Active CPUSS P-DMA0, Channel #34 Interrupt
188
cpuss_interrupts_dw0_36_IRQn
Active CPUSS P-DMA0, Channel #36 Interrupt
189
cpuss_interrupts_dw0_37_IRQn
Active CPUSS P-DMA0, Channel #37 Interrupt
194
cpuss_interrupts_dw0_42_IRQn
Active CPUSS P-DMA0, Channel #42 Interrupt
Datasheet
46
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Description
205
cpuss_interrupts_dw0_53_IRQn
Active CPUSS P-DMA0, Channel #53 Interrupt
206
cpuss_interrupts_dw0_54_IRQn
Active CPUSS P-DMA0, Channel #54 Interrupt
207
cpuss_interrupts_dw0_55_IRQn
Active CPUSS P-DMA0, Channel #55 Interrupt
208
cpuss_interrupts_dw0_56_IRQn
Active CPUSS P-DMA0, Channel #56 Interrupt
209
cpuss_interrupts_dw0_57_IRQn
Active CPUSS P-DMA0, Channel #57 Interrupt
213
cpuss_interrupts_dw0_61_IRQn
Active CPUSS P-DMA0, Channel #61 Interrupt
214
cpuss_interrupts_dw0_62_IRQn
Active CPUSS P-DMA0, Channel #62 Interrupt
215
cpuss_interrupts_dw0_63_IRQn
Active CPUSS P-DMA0, Channel #63 Interrupt
216
cpuss_interrupts_dw0_64_IRQn
Active CPUSS P-DMA0, Channel #64 Interrupt
217
cpuss_interrupts_dw0_65_IRQn
Active CPUSS P-DMA0, Channel #65 Interrupt
218
cpuss_interrupts_dw0_66_IRQn
Active CPUSS P-DMA0, Channel #66 Interrupt
223
cpuss_interrupts_dw0_71_IRQn
Active CPUSS P-DMA0, Channel #71 Interrupt
224
cpuss_interrupts_dw0_72_IRQn
Active CPUSS P-DMA0, Channel #72 Interrupt
233
cpuss_interrupts_dw0_81_IRQn
Active CPUSS P-DMA0, Channel #81 Interrupt
234
cpuss_interrupts_dw0_82_IRQn
Active CPUSS P-DMA0, Channel #82 Interrupt
235
cpuss_interrupts_dw0_83_IRQn
Active CPUSS P-DMA0, Channel #83 Interrupt
236
cpuss_interrupts_dw0_84_IRQn
Active CPUSS P-DMA0, Channel #84 Interrupt
237
cpuss_interrupts_dw0_85_IRQn
Active CPUSS P-DMA0, Channel #85 Interrupt
238
cpuss_interrupts_dw0_86_IRQn
Active CPUSS P-DMA0, Channel #86 Interrupt
239
cpuss_interrupts_dw0_87_IRQn
Active CPUSS P-DMA0, Channel #87 Interrupt
240
cpuss_interrupts_dw0_88_IRQn
Active CPUSS P-DMA0, Channel #88 Interrupt
241
cpuss_interrupts_dw1_0_IRQn
Active CPUSS P-DMA1, Channel #0 Interrupt
242
cpuss_interrupts_dw1_1_IRQn
Active CPUSS P-DMA1, Channel #1 Interrupt
Datasheet
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002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Description
243
cpuss_interrupts_dw1_2_IRQn
Active CPUSS P-DMA1, Channel #2 Interrupt
244
cpuss_interrupts_dw1_3_IRQn
Active CPUSS P-DMA1, Channel #3 Interrupt
245
cpuss_interrupts_dw1_4_IRQn
Active CPUSS P-DMA1, Channel #4 Interrupt
246
cpuss_interrupts_dw1_5_IRQn
Active CPUSS P-DMA1, Channel #5 Interrupt
247
cpuss_interrupts_dw1_6_IRQn
Active CPUSS P-DMA1, Channel #6 Interrupt
248
cpuss_interrupts_dw1_7_IRQn
Active CPUSS P-DMA1, Channel #7 Interrupt
249
cpuss_interrupts_dw1_8_IRQn
Active CPUSS P-DMA1, Channel #8 Interrupt
250
cpuss_interrupts_dw1_9_IRQn
Active CPUSS P-DMA1, Channel #9 Interrupt
251
cpuss_interrupts_dw1_10_IRQn
Active CPUSS P-DMA1, Channel #10 Interrupt
252
cpuss_interrupts_dw1_11_IRQn
Active CPUSS P-DMA1, Channel #11 Interrupt
255
cpuss_interrupts_dw1_14_IRQn
Active CPUSS P-DMA1, Channel #14 Interrupt
256
cpuss_interrupts_dw1_15_IRQn
Active CPUSS P-DMA1, Channel #15 Interrupt
257
cpuss_interrupts_dw1_16_IRQn
Active CPUSS P-DMA1, Channel #16 Interrupt
258
cpuss_interrupts_dw1_17_IRQn
Active CPUSS P-DMA1, Channel #17 Interrupt
259
cpuss_interrupts_dw1_18_IRQn
Active CPUSS P-DMA1, Channel #18 Interrupt
260
cpuss_interrupts_dw1_19_IRQn
Active CPUSS P-DMA1, Channel #19 Interrupt
263
cpuss_interrupts_dw1_22_IRQn
Active CPUSS P-DMA1, Channel #22 Interrupt
264
cpuss_interrupts_dw1_23_IRQn
Active CPUSS P-DMA1, Channel #23 Interrupt
265
cpuss_interrupts_dw1_24_IRQn
Active CPUSS P-DMA1, Channel #24 Interrupt
266
cpuss_interrupts_dw1_25_IRQn
Active CPUSS P-DMA1, Channel #25 Interrupt
267
cpuss_interrupts_dw1_26_IRQn
Active CPUSS P-DMA1, Channel #26 Interrupt
268
cpuss_interrupts_dw1_27_IRQn
Active CPUSS P-DMA1, Channel #27 Interrupt
269
cpuss_interrupts_dw1_28_IRQn
Active CPUSS P-DMA1, Channel #28 Interrupt
Datasheet
48
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Description
270
cpuss_interrupts_dw1_29_IRQn
Active CPUSS P-DMA1, Channel #29 Interrupt
274 tcpwm_0_interrupts_0_IRQn
Active TCPWM0 Group #0, Counter #0 Interrupt
275 tcpwm_0_interrupts_1_IRQn
Active TCPWM0 Group #0, Counter #1 Interrupt
276 tcpwm_0_interrupts_2_IRQn
Active TCPWM0 Group #0, Counter #2 Interrupt
278 tcpwm_0_interrupts_4_IRQn
Active TCPWM0 Group #0, Counter #4 Interrupt
279 tcpwm_0_interrupts_5_IRQn
Active TCPWM0 Group #0, Counter #5 Interrupt
280 tcpwm_0_interrupts_6_IRQn
Active TCPWM0 Group #0, Counter #6 Interrupt
281 tcpwm_0_interrupts_7_IRQn
Active TCPWM0 Group #0, Counter #7 Interrupt
283 tcpwm_0_interrupts_9_IRQn
Active TCPWM0 Group #0, Counter #9 Interrupt
284 tcpwm_0_interrupts_10_IRQn Active TCPWM0 Group #0, Counter #10 Interrupt
285 tcpwm_0_interrupts_11_IRQn Active TCPWM0 Group #0, Counter #11 Interrupt
286 tcpwm_0_interrupts_12_IRQn Active TCPWM0 Group #0, Counter #12 Interrupt
287 tcpwm_0_interrupts_13_IRQn Active TCPWM0 Group #0, Counter #13 Interrupt
288 tcpwm_0_interrupts_14_IRQn Active TCPWM0 Group #0, Counter #14 Interrupt
289 tcpwm_0_interrupts_15_IRQn Active TCPWM0 Group #0, Counter #15 Interrupt
290 tcpwm_0_interrupts_16_IRQn Active TCPWM0 Group #0, Counter #16 Interrupt
291 tcpwm_0_interrupts_17_IRQn Active TCPWM0 Group #0, Counter #17 Interrupt
292 tcpwm_0_interrupts_18_IRQn Active TCPWM0 Group #0, Counter #18 Interrupt
293 tcpwm_0_interrupts_19_IRQn Active TCPWM0 Group #0, Counter #19 Interrupt
294 tcpwm_0_interrupts_20_IRQn Active TCPWM0 Group #0, Counter #20 Interrupt
295 tcpwm_0_interrupts_21_IRQn Active TCPWM0 Group #0, Counter #21 Interrupt
296 tcpwm_0_interrupts_22_IRQn Active TCPWM0 Group #0, Counter #22 Interrupt
297 tcpwm_0_interrupts_23_IRQn Active TCPWM0 Group #0, Counter #23 Interrupt
298 tcpwm_0_interrupts_24_IRQn Active TCPWM0 Group #0, Counter #24 Interrupt
299 tcpwm_0_interrupts_25_IRQn Active TCPWM0 Group #0, Counter #25 Interrupt
300 tcpwm_0_interrupts_26_IRQn Active TCPWM0 Group #0, Counter #26 Interrupt
307 tcpwm_0_interrupts_33_IRQn Active TCPWM0 Group #0, Counter #33 Interrupt
308 tcpwm_0_interrupts_34_IRQn Active TCPWM0 Group #0, Counter #34 Interrupt
310 tcpwm_0_interrupts_36_IRQn Active TCPWM0 Group #0, Counter #36 Interrupt
311 tcpwm_0_interrupts_37_IRQn Active TCPWM0 Group #0, Counter #37 Interrupt
312 tcpwm_0_interrupts_38_IRQn Active TCPWM0 Group #0, Counter #38 Interrupt
313 tcpwm_0_interrupts_39_IRQn Active TCPWM0 Group #0, Counter #39 Interrupt
314 tcpwm_0_interrupts_40_IRQn Active TCPWM0 Group #0, Counter #40 Interrupt
315 tcpwm_0_interrupts_41_IRQn Active TCPWM0 Group #0, Counter #41 Interrupt
316 tcpwm_0_interrupts_42_IRQn Active TCPWM0 Group #0, Counter #42 Interrupt
318 tcpwm_0_interrupts_44_IRQn Active TCPWM0 Group #0, Counter #44 Interrupt
319 tcpwm_0_interrupts_45_IRQn Active TCPWM0 Group #0, Counter #45 Interrupt
320 tcpwm_0_interrupts_46_IRQn Active TCPWM0 Group #0, Counter #46 Interrupt
321 tcpwm_0_interrupts_47_IRQn Active TCPWM0 Group #0, Counter #47 Interrupt
Datasheet
49
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Interrupts and wake-up assignments
Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power Mode
Description
322 tcpwm_0_interrupts_48_IRQn Active TCPWM0 Group #0, Counter #48 Interrupt
323 tcpwm_0_interrupts_49_IRQn Active TCPWM0 Group #0, Counter #49 Interrupt
324 tcpwm_0_interrupts_50_IRQn Active TCPWM0 Group #0, Counter #50 Interrupt
325 tcpwm_0_interrupts_51_IRQn Active TCPWM0 Group #0, Counter #51 Interrupt
326 tcpwm_0_interrupts_52_IRQn Active TCPWM0 Group #0, Counter #52 Interrupt
327 tcpwm_0_interrupts_53_IRQn Active TCPWM0 Group #0, Counter #53 Interrupt
328 tcpwm_0_interrupts_54_IRQn Active TCPWM0 Group #0, Counter #54 Interrupt
329 tcpwm_0_interrupts_55_IRQn Active TCPWM0 Group #0, Counter #55 Interrupt
337
tcpwm_0_interrupts_256_IRQn
Active TCPWM0 Group #1, Counter #0 Interrupt
338
tcpwm_0_interrupts_257_IRQn
Active TCPWM0 Group #1, Counter #1 Interrupt
339
tcpwm_0_interrupts_258_IRQn
Active TCPWM0 Group #1, Counter #2 Interrupt
341
tcpwm_0_interrupts_260_IRQn
Active TCPWM0 Group #1, Counter #4 Interrupt
349
tcpwm_0_interrupts_512_IRQn
Active TCPWM0 Group #2, Counter #0 Interrupt
351
tcpwm_0_interrupts_514_IRQn
Active TCPWM0 Group #2, Counter #2 Interrupt
Datasheet
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002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Core interrupt types
16
Core interrupt types
Table 16-1 Interrupt 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Core interrupt types Source
CPUIntIdx0_IRQn[29] CPUIntIdx1_IRQn[29] CPUIntIdx2_IRQn CPUIntIdx3_IRQn
CPUIntIdx4_IRQn CPUIntIdx5_IRQn CPUIntIdx6_IRQn CPUIntIdx7_IRQn Internal0_IRQn
Internal1_IRQn Internal2_IRQn Internal3_IRQn Internal4_IRQn Internal5_IRQn
Internal6_IRQn Internal7_IRQn
Power mode DeepSleep DeepSleep DeepSleep DeepSleep DeepSleep DeepSleep DeepSleep DeepSleep Active Active Active Active Active Active Active Active
Description CPU User Interrupt #0 CPU User Interrupt #1 CPU User Interrupt #2 CPU User Interrupt #3 CPU User Interrupt #4 CPU User Interrupt #5 CPU User Interrupt #6 CPU User Interrupt #7 Internal Software Interrupt #0 Internal Software Interrupt #1 Internal Software Interrupt #2 Internal Software Interrupt #3 Internal Software Interrupt #4 Internal Software Interrupt #5 Internal Software Interrupt #6 Internal Software Interrupt #7
Note 29.User interrupt cannot be used for CM0+ application, as it is used internally by system calls. Note, this does not impact CM4 application.
Datasheet
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2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Trigger multiplexer
17
Trigger multiplexer
16 P-DMA0: PDMA0_TR_OUT[0:15] P-DMA1: PDMA1_TR_OUT[0:7] 8
M-DMA: MDMA_TR_OUT[0:1] 2
3:6 0:15
7:10
16:31
TCPWM[0]32: TCPWM_32_TR_OUT0{[0],[2]} 2 TCPWM[0]32: TCPWM_32_TR_OUT1{[0],[2]} 2
TCPWM[0]16M: TCPWM_16M_TR_OUT0{[0:2],[4]} 4 TCPWM[0]16M: TCPWM_16M_TR_OUT1{[0:2],[4]} 4
TCPWM[0]16: TCPWM_16_TR_OUT0{[0:2],[4:7],[9:26],[33:34],[36:42],[44:55]} TCPWM[0]16: TCPWM_16_TR_OUT1{[0:2],[4:7],[9:26],[33:34],[36:42],[44:55]}
46 63
CPUSS: FAULT_TR_OUT[0:3] 6 CPUSS: CTI_TR_OUT[0:1] EVTGEN[0]:
EVTGEN_TR_OUT[0:10] 11
HSIOM: HSIOM_IO _INPUT[0:31] 32
PASS[0]: PASS_GEN_TR_OUT[0:5] 6
PASS[0]: PASS_CH_DONE_TR_OUT{[0:5],[8:9],[11:12],[17]} PASS[0]: PASS_CH_DONE_TR_OUT{[36:40],[44:49],[54:55]}
32
PASS[0]: PASS_CH_DONE_TR_OUT[64:71]
PASS[0]: PASS_CH_RANGEVIO_TR_OUT{[0],[4:5],[8:9],[11],[17]} PASS[0]: PASS_CH_RANGEVIO_TR_OUT{[36:40],[49],[54:55]}
20
PASS[0]: PASS_CH_RANGEVIO_TR_OUT{[64],[68:71]}
CAN[0:1]: CAN0_DBG_TR_OUT/CAN1_DBG_TR_OUT[0:1] CAN[0:1]: CAN0_FIFO0_TR_OUT/CAN1_FIFO0_TR_OUT[0:1] 12 CAN[0:1]: CAN0_FIFO1_TR_OUT/CAN1_FIFO1_TR_OUT[0:1] CAN[0]: CAN0_TT_TR_OUT[0:1] 4 CAN[1]: CAN1_TT_TR_OUT[0:1]
P-DMA0: PDMA0_TR_OUT{[16],[19]} 2 P-DMA1: PDMA1_TR_OUT{[24],[27]} 2
SCB{[0:1],[3:5],[7]}: SCB_TX_TR_OUT SCB{[0:1],[3:5],[7]}: SCB_RX_TR_OUT
18
SCB{[0:1],[3:5],[7]}: SCB_I2C_SCL_TR_OUT
All Triggers 245
0:1,4:5,7, 13,20:24,33, 38:39,48:51 0:2 3:10
0:2
SCB_TX_TR_OUT, SCB_RX_TR_OUT P-DMA0, SCB, CANFD, CPUSS, TCPWM_TR_OUT0*
0:2,4:7
0:2,4
P-DMA1, M-DMA, PASS, EVTGEN, TCPWM_TR_OUT1*
Figure 17-1 Trigger multiplexer[30]
Green numbers indicate mux group number
16
Orange numbers indicate 1:1 group number
8
2
6
0
8
P-DMA0: PDMA0_TR_IN[0:7]
4
16
16
8
2
6 4
1
16
6
8
P-DMA1: PDMA1_TR_IN[0:7]
2
2
2
4
3
46
Mux #4 only 7
4
4
2
M-DMA: MDMA_TR_IN[0:1]
8
P-DMA0: PDMA0_TR_IN[8:15]
16
TCPWM[0]: TCPWM_ALL_CNT_TR_IN[0:15]
0
1
16
8
2
6
8
18
5
32
6
12
16
32
4
6 3
6
2
6
2
3
4 5
4
7
6
7
8
146
9
99
10
5
8
5
4
LIN[0]: LIN0_CMD_TR_IN{[0:2],[4]}
21
PASS[0]: PASS0_CH_TR_IN{[0:2],[4:5],[8:9],[11],[17]} PASS[0]: PASS0_CH_TR_IN{[36:40],[49],[54:55]}
PASS[0]: PASS0_CH_TR_IN[68:71]
11
TCPWM[0]: TCPWM_ALL_CNT_TR_IN[16:26]
9
PASS[0]: PASS_GEN_TR_IN{[0:5],[8:9],[11]}
32
P-DMA0: PDMA0_TR_IN{[25:30],[33:34],[36:37],[42],[53:57],[61:66],
[71:72],[81:88]}
2
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN{[0],[2]}
18
TCPWM[0]16: TCPWM0_16_ONE_CNT_TR_IN[0:1],[4:5],[7],[13],[20:24],
[33],[38:39],[48:51]}
6
P-DMA0: PDMA0_TR_IN[16:21]
6
P-DMA1: PDMA1_TR_IN[24:29]
4
CAN[0]: CAN0_TT_TR_IN[0:1]
CAN[1]: CAN1_TT_TR_IN[0:1]
2
CAN[0]: CAN0_DBG_TR_ACK[0:1]
2
CAN[1]: CAN1_DBG_TR_ACK[0:1]
12
P-DMA1: PDMA1_TR_IN{[8:11],[14:19],[22:23]}
2
CPUSS: CTI_TR_IN[0:1]
1
TCPWM[0]: TCPWM_DEBUG_FREEZE_TR_IN
1
PERI: PERI_DEBUG_FREEZE_TR_IN
1 PASS[0]: PASS_DEBUG_FREEZE_TR_IN
3
SRSS: SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0:1]
2
HSIOM: HSIOM_IO_OUTPUT[0:1]
Note 30.The diagram shows only the TRIGLABEL, final trigger formation is
based on the formula TRIG{PREFIX(IN/OUT)}_{MUXx}{TRIGLA-
BEL} / TRIG{PREFIX(IN_1TO1/OUT1TO1)}{x}_{TRIG_LABEL} and the below
mentioned tables Table 18-1, Table 19-1, and Table 20-1.
Datasheet
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002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
18
Triggers group inputs
Table 18-1 Trigger inputs
Input
Trigger label (TRIG_LABEL)
Description
MUX Group 0: PDMA0_TR (P-DMA0_0_15 trigger multiplexer)
1:16[31] PDMA0_TR_OUT[0:15]
Allow P-DMA0 to chain to itself, useful for triggering once per
row for 2D transfer
17:24
PDMA1_TR_OUT[0:7]
Cross connections from P-DMA1 to P-DMA0, Channels 0-7 are used
25:26
MDMA_TR_OUT[0:1]
Cross connections from M-DMA0 to P-DMA0
29:32
FAULT_TR_OUT[0:3]
Allow faults to initiate data transfer for debug purposes
33:34
CTI_TR_OUT[0:1]
Trace events
35:38
EVTGEN_TR_OUT[3:6]
EVTGEN triggers
39:54
HSIOM_IO_INPUT[0:15]
I/O inputs
MUX Group 1: PDMA1_TR (P-DMA1 trigger multiplexer)
1:16
PDMA0_TR_OUT[0:15]
Allow P-DMA0 to trigger P-DMA1
17:24
PDMA1_TR_OUT[0:7]
Allow P-DMA1 to chain to itself, useful for triggering once per row for 2D transfer
25:26
MDMA_TR_OUT[0:1]
Allow M-DMA0 to trigger P-DMA0
29:32
FAULT_TR_OUT[0:3]
Allow faults to initiate data transfer for debug purposes
33:34
CTI_TR_OUT[0:1]
Trace events
35:38
EVTGEN_TR_OUT[7:10]
EVTGEN triggers
39:54
HSIOM_IO_INPUT[16:31] I/O inputs
55:60
PASS_GEN_TR_OUT[0:5] PASS SAR events
MUX Group 2: MDMA (M-DMA0 trigger multiplexer)
1:2
MDMA_TR_OUT[0:1]
Allow M-DMA0 to trigger itself
MUX Group 3: TCPWM_TO_PDMA0 (TCPWM0 to P-DMA0 trigger multiplexer)
1
TCPWM_32_TR_OUT0[0] 32-bit TCPWM0 Group #2, Counter #0 counters
3
TCPWM_32_TR_OUT0[2] 32-bit TCPWM0 Group #2, Counter #2 counters
5
TCPWM_16M_TR_OUT0[0] 16-bit Motor enhanced TCPWM0 Group #1, Counter #0 counters
6
TCPWM_16M_TR_OUT0[1] 16-bit Motor enhanced TCPWM0 Group #1, Counter #1 counters
7
TCPWM_16M_TR_OUT0[2] 16-bit Motor enhanced TCPWM0 Group #1, Counter #2 counters
9
TCPWM_16M_TR_OUT0[4] 16-bit Motor enhanced TCPWM0 Group #1, Counter #4 counters
17
TCPWM_16_TR_OUT0[0] TCPWM0 Group #0, Counter #0
18
TCPWM_16_TR_OUT0[1] TCPWM0 Group #0, Counter #1
19
TCPWM_16_TR_OUT0[2] TCPWM0 Group #0, Counter #2
21
TCPWM_16_TR_OUT0[4] TCPWM0 Group #0, Counter #4
22
TCPWM_16_TR_OUT0[5] TCPWM0 Group #0, Counter #5
23
TCPWM_16_TR_OUT0[6] TCPWM0 Group #0, Counter #6
24
TCPWM_16_TR_OUT0[7] TCPWM0 Group #0, Counter #7
Note 31.”a:b” depicts a range starting from a’ throughb’.
Datasheet
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002-25756 Rev. *C
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TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 50 51 53 54 55 56 57 58
59 61 62 63 64 65 66 67 68 69 70 71 72
Trigger inputs (continued) Trigger label (TRIG_LABEL)
TCPWM_16_TR_OUT0[9] TCPWM_16_TR_OUT0[10] TCPWM_16_TR_OUT0[11]
TCPWM_16_TR_OUT0[12] TCPWM_16_TR_OUT0[13] TCPWM_16_TR_OUT0[14]
TCPWM_16_TR_OUT0[15] TCPWM_16_TR_OUT0[16] TCPWM_16_TR_OUT0[17]
TCPWM_16_TR_OUT0[18] TCPWM_16_TR_OUT0[19] TCPWM_16_TR_OUT0[20]
TCPWM_16_TR_OUT0[21] TCPWM_16_TR_OUT0[22] TCPWM_16_TR_OUT0[23]
TCPWM_16_TR_OUT0[24] TCPWM_16_TR_OUT0[25] TCPWM_16_TR_OUT0[26]
TCPWM_16_TR_OUT0[33] TCPWM_16_TR_OUT0[34] TCPWM_16_TR_OUT0[36]
TCPWM_16_TR_OUT0[37] TCPWM_16_TR_OUT0[38] TCPWM_16_TR_OUT0[39]
TCPWM_16_TR_OUT0[40] TCPWM_16_TR_OUT0[41] TCPWM_16_TR_OUT0[42]
TCPWM_16_TR_OUT0[44] TCPWM_16_TR_OUT0[45] TCPWM_16_TR_OUT0[46]
TCPWM_16_TR_OUT0[47] TCPWM_16_TR_OUT0[48] TCPWM_16_TR_OUT0[49]
TCPWM_16_TR_OUT0[50] TCPWM_16_TR_OUT0[51] TCPWM_16_TR_OUT0[52]
TCPWM_16_TR_OUT0[53] TCPWM_16_TR_OUT0[54] TCPWM_16_TR_OUT0[55]
Description
TCPWM0 Group #0, Counter #9 TCPWM0 Group #0, Counter #10 TCPWM0 Group #0,
Counter #11 TCPWM0 Group #0, Counter #12 TCPWM0 Group #0, Counter #13 TCPWM0
Group #0, Counter #14 TCPWM0 Group #0, Counter #15 TCPWM0 Group #0, Counter
16 TCPWM0 Group #0, Counter #17 TCPWM0 Group #0, Counter #18 TCPWM0 Group #0,
Counter #19 TCPWM0 Group #0, Counter #20 TCPWM0 Group #0, Counter #21 TCPWM0 Group #0, Counter #22 TCPWM0 Group #0, Counter #23 TCPWM0 Group #0, Counter
24 TCPWM0 Group #0, Counter #25 TCPWM0 Group #0, Counter #26 TCPWM0 Group #0,
Counter #33 TCPWM0 Group #0, Counter #34 TCPWM0 Group #0, Counter #36 TCPWM0 Group #0, Counter #37 TCPWM0 Group #0, Counter #38 TCPWM0 Group #0, Counter
39 TCPWM0 Group #0, Counter #40 TCPWM0 Group #0, Counter #41 TCPWM0 Group #0,
Counter #42 TCPWM0 Group #0, Counter #44 TCPWM0 Group #0, Counter #45 TCPWM0 Group #0, Counter #46 TCPWM0 Group #0, Counter #47 TCPWM0 Group #0, Counter
48 TCPWM0 Group #0, Counter #49 TCPWM0 Group #0, Counter #50 TCPWM0 Group #0,
Counter #51 TCPWM0 Group #0, Counter #52 TCPWM0 Group #0, Counter #53 TCPWM0 Group #0, Counter #54 TCPWM0 Group #0, Counter #55
Datasheet
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002-25756 Rev. *C 2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1 Trigger inputs (continued)
Input
Trigger label (TRIG_LABEL)
Description
80
CAN0_TT_TR_OUT[0]
CAN0, channel#0 TT Sync Outputs
81
CAN0_TT_TR_OUT[1]
CAN0, channel#1 TT Sync Outputs
83
CAN1_TT_TR_OUT[0]
CAN1, channel#0 TT Sync Outputs
84
CAN1_TT_TR_OUT[1]
CAN1, channel#1 TT Sync Outputs
MUX Group 4: TCPWM_OUT (TCPWM0 loop back multiplexer)
1
TCPWM_32_TR_OUT0[0] 32-bit TCPWM0 Group #2, Counter #0 counters
3
TCPWM_32_TR_OUT0[2] 32-bit TCPWM0 Group #2, Counter #2 counters
5
TCPWM_16M_TR_OUT0[0] 16-bit Motor enhanced TCPWM0 Group #1, Counter #0 counters
6
TCPWM_16M_TR_OUT0[1] 16-bit Motor enhanced TCPWM0 Group #1, Counter #1 counters
7
TCPWM_16M_TR_OUT0[2] 16-bit Motor enhanced TCPWM0 Group #1, Counter #2 counters
9
TCPWM_16M_TR_OUT0[4] 16-bit Motor enhanced TCPWM0 Group #1, Counter #4 counters
17
TCPWM_16_TR_OUT0[0] TCPWM0 Group #0, Counter #0
18
TCPWM_16_TR_OUT0[1] TCPWM0 Group #0, Counter #1
19
TCPWM_16_TR_OUT0[2] TCPWM0 Group #0, Counter #2
21
TCPWM_16_TR_OUT0[4] TCPWM0 Group #0, Counter #4
22
TCPWM_16_TR_OUT0[5] TCPWM0 Group #0, Counter #5
23
TCPWM_16_TR_OUT0[6] TCPWM0 Group #0, Counter #6
24
TCPWM_16_TR_OUT0[7] TCPWM0 Group #0, Counter #7
26
TCPWM_16_TR_OUT0[9] TCPWM0 Group #0, Counter #9
27
TCPWM_16_TR_OUT0[10] TCPWM0 Group #0, Counter #10
28
TCPWM_16_TR_OUT0[11] TCPWM0 Group #0, Counter #11
29
TCPWM_16_TR_OUT0[12] TCPWM0 Group #0, Counter #12
30
TCPWM_16_TR_OUT0[13] TCPWM0 Group #0, Counter #13
31
TCPWM_16_TR_OUT0[14] TCPWM0 Group #0, Counter #14
32
TCPWM_16_TR_OUT0[15] TCPWM0 Group #0, Counter #15
33
TCPWM_16_TR_OUT0[16] TCPWM0 Group #0, Counter #16
34
TCPWM_16_TR_OUT0[17] TCPWM0 Group #0, Counter #17
35
TCPWM_16_TR_OUT0[18] TCPWM0 Group #0, Counter #18
36
TCPWM_16_TR_OUT0[19] TCPWM0 Group #0, Counter #19
37
TCPWM_16_TR_OUT0[20] TCPWM0 Group #0, Counter #20
38
TCPWM_16_TR_OUT0[21] TCPWM0 Group #0, Counter #21
39
TCPWM_16_TR_OUT0[22] TCPWM0 Group #0, Counter #22
40
TCPWM_16_TR_OUT0[23] TCPWM0 Group #0, Counter #23
41
TCPWM_16_TR_OUT0[24] TCPWM0 Group #0, Counter #24
42
TCPWM_16_TR_OUT0[25] TCPWM0 Group #0, Counter #25
43
TCPWM_16_TR_OUT0[26] TCPWM0 Group #0, Counter #26
50
TCPWM_16_TR_OUT0[33] TCPWM0 Group #0, Counter #33
51
TCPWM_16_TR_OUT0[34] TCPWM0 Group #0, Counter #34
53
TCPWM_16_TR_OUT0[36] TCPWM0 Group #0, Counter #36
Datasheet
55
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1 Trigger inputs (continued)
Input
Trigger label (TRIG_LABEL)
Description
54
TCPWM_16_TR_OUT0[37] TCPWM0 Group #0, Counter #37
55
TCPWM_16_TR_OUT0[38] TCPWM0 Group #0, Counter #38
56
TCPWM_16_TR_OUT0[39] TCPWM0 Group #0, Counter #39
57
TCPWM_16_TR_OUT0[40] TCPWM0 Group #0, Counter #40
58
TCPWM_16_TR_OUT0[41] TCPWM0 Group #0, Counter #41
59
TCPWM_16_TR_OUT0[42] TCPWM0 Group #0, Counter #42
61
TCPWM_16_TR_OUT0[44] TCPWM0 Group #0, Counter #44
62
TCPWM_16_TR_OUT0[45] TCPWM0 Group #0, Counter #45
63
TCPWM_16_TR_OUT0[46] TCPWM0 Group #0, Counter #46
64
TCPWM_16_TR_OUT0[47] TCPWM0 Group #0, Counter #47
65
TCPWM_16_TR_OUT0[48] TCPWM0 Group #0, Counter #48
66
TCPWM_16_TR_OUT0[49] TCPWM0 Group #0, Counter #49
67
TCPWM_16_TR_OUT0[50] TCPWM0 Group #0, Counter #50
68
TCPWM_16_TR_OUT0[51] TCPWM0 Group #0, Counter #51
69
TCPWM_16_TR_OUT0[52] TCPWM0 Group #0, Counter #52
70
TCPWM_16_TR_OUT0[53] TCPWM0 Group #0, Counter #53
71
TCPWM_16_TR_OUT0[54] TCPWM0 Group #0, Counter #54
72
TCPWM_16_TR_OUT0[55] TCPWM0 Group #0, Counter #55
80
TCPWM_16_TR_OUT1[0] TCPWM0 Group #1, Counter #0
81
TCPWM_16_TR_OUT1[1] TCPWM0 Group #1, Counter #1
82
TCPWM_16_TR_OUT1[2] TCPWM0 Group #1, Counter #2
84
TCPWM_16_TR_OUT1[4] TCPWM0 Group #1, Counter #4
85
TCPWM_16_TR_OUT1[5] TCPWM0 Group #1, Counter #5
86
TCPWM_16_TR_OUT1[6] TCPWM0 Group #1, Counter #6
87
TCPWM_16_TR_OUT1[7] TCPWM0 Group #1, Counter #7
88
CAN0_TT_TR_OUT[0]
CAN0, channel#0 TT Sync Outputs
89
CAN0_TT_TR_OUT[1]
CAN0, channel#1 TT Sync Outputs
91
CAN1_TT_TR_OUT[0]
CAN1, channel#0 TT Sync Outputs
92
CAN1_TT_TR_OUT[1]
CAN1, channel#1 TT Sync Outputs
MUX Group 5: TCPWM_IN (TCPWM0 Trigger Multiplexer)
1:16
PDMA0_TR_OUT[0:15]
General-purpose P-DMA0 triggers
17:24
PDMA1_TR_OUT[0:7]
General-purpose P-DMA1 triggers
25:26
MDMA_TR_OUT[0:1]
M-DMA0 triggers
29:30
CTI_TR_OUT[0:1]
Trace events
31:34
FAULT_TR_OUT[0:3]
Fault events
35:40
PASS_GEN_TR_OUT[0:5] PASS SAR events
41:72
HSIOM_IO_INPUT[0:31]
I/O inputs
73
SCB_TX_TR_OUT[0]
SCB0 TX trigger
74
SCB_RX_TR_OUT[0]
SCB0 RX trigger
Datasheet
56
002-25756 Rev. *C 2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1 Trigger inputs (continued)
Input 75
Trigger label (TRIG_LABEL)
SCB_I2C_SCL_TR_OUT[0]
SCB0 I2C trigger
Description
76
SCB_TX_TR_OUT[1]
SCB1 TX trigger
77
SCB_RX_TR_OUT[1]
SCB1 RX trigger
78
SCB_I2C_SCL_TR_OUT[1] SCB1 I2C trigger
82
SCB_TX_TR_OUT[3]
SCB3 TX trigger
83
SCB_RX_TR_OUT[3]
SCB3 RX trigger
84
SCB_I2C_SCL_TR_OUT[3] SCB3 I2C trigger
85
SCB_TX_TR_OUT[4]
SCB4 TX trigger
86
SCB_RX_TR_OUT[4]
SCB4 RX trigger
87
SCB_I2C_SCL_TR_OUT[4] SCB4 I2C trigger
88
SCB_TX_TR_OUT[5]
SCB5 TX trigger
89
SCB_RX_TR_OUT[5]
SCB5 RX trigger
90
SCB_I2C_SCL_TR_OUT[5] SCB5 I2C trigger
94
SCB_TX_TR_OUT[7]
SCB7 TX trigger
95
SCB_RX_TR_OUT[7]
SCB7 RX trigger
96
SCB_I2C_SCL_TR_OUT[7] SCB7 I2C trigger
97:98
CAN0_DBG_TR_OUT[0:1] CAN0 M-DMA0 events
100:101 CAN0_FIFO0_TR_OUT[0:1] CAN0 FIFO0 events
103:104 CAN0_FIFO1_TR_OUT[0:1] CAN0 FIFO1 events
106:107 CAN1_DBG_TR_OUT[0:1] CAN1 M-DMA0 events
109:110 CAN1_FIFO0_TR_OUT[0:1] CAN1 FIFO0 events
112:113 CAN1_FIFO1_TR_OUT[0:1] CAN1 FIFO1 events
115:122 EVTGEN_TR_OUT[3:10]
EVTGEN triggers
MUX Group 6: PASS (PASS SAR trigger multiplexer)
1:16
PDMA0_TR_OUT[0:15]
General-purpose P-DMA0 triggers
17:18
CTI_TR_OUT[0:1]
Trace events
19:22
FAULT_TR_OUT[0:3]
Fault events
23:25
EVTGEN_TR_OUT[0:2]
EVTGEN triggers
26:31
PASS_GEN_TR_OUT[0:5] PASS SAR done signals
32:63
HSIOM_IO_INPUT[0:31]
I/O inputs
64
TCPWM_32_TR_OUT1[0] 32-bit TCPWM0 Group #2, Counter #0 counters
66
TCPWM_32_TR_OUT1[2] 32-bit TCPWM0 Group #2, Counter #2 counters
68
TCPWM_16M_TR_OUT1[0] 16-bit Motor enhanced TCPWM0 Group #1, Counter #0 counters
69
TCPWM_16M_TR_OUT1[1] 16-bit Motor enhanced TCPWM0 Group #1, Counter #1 counters
70
TCPWM_16M_TR_OUT1[2] 16-bit Motor enhanced TCPWM0 Group #1, Counter #2 counters
72
TCPWM_16M_TR_OUT1[4] 16-bit Motor enhanced TCPWM0 Group #1, Counter #4 counters
MUX Group 7: CAN TT sync triggers
1:2
CAN0_TT_TR_OUT[0:1]
CAN0 TT Sync Outputs
4:5
CAN1_TT_TR_OUT[0:1]
CAN1 TT Sync Outputs
Datasheet
57
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1 Trigger inputs (continued)
Input
Trigger label (TRIG_LABEL)
Description
MUX Group 8: DebugMain (Debug Multiplexer)
1:5
TR_GROUP9_OUTPUT[0:4] Output from debug reduction multiplexer #1
6:10
TR_GROUP10_OUTPUT[0:4] Output from debug reduction multiplexer #2
MUX Group 9: DebugReduction1 (Debug Reduction #1)
1
PDMA0_TR_OUT[0]
P-DMA0 triggers
2
PDMA0_TR_OUT[1]
P-DMA0 triggers
3
PDMA0_TR_OUT[2]
P-DMA0 triggers
4
PDMA0_TR_OUT[3]
P-DMA0 triggers
5
PDMA0_TR_OUT[4]
P-DMA0 triggers
6
PDMA0_TR_OUT[5]
P-DMA0 triggers
7
PDMA0_TR_OUT[6]
P-DMA0 triggers
8
PDMA0_TR_OUT[7]
P-DMA0 triggers
9
PDMA0_TR_OUT[8]
P-DMA0 triggers
10
PDMA0_TR_OUT[9]
P-DMA0 triggers
11
PDMA0_TR_OUT[10]
P-DMA0 triggers
12
PDMA0_TR_OUT[11]
P-DMA0 triggers
13
PDMA0_TR_OUT[12]
P-DMA0 triggers
14
PDMA0_TR_OUT[13]
P-DMA0 triggers
15
PDMA0_TR_OUT[14]
P-DMA0 triggers
16
PDMA0_TR_OUT[15]
P-DMA0 triggers
17
PDMA0_TR_OUT[16]
P-DMA0 triggers
18
PDMA0_TR_OUT[17]
P-DMA0 triggers
19
PDMA0_TR_OUT[18]
P-DMA0 triggers
20
PDMA0_TR_OUT[19]
P-DMA0 triggers
21
PDMA0_TR_OUT[20]
P-DMA0 triggers
22
PDMA0_TR_OUT[21]
P-DMA0 triggers
26
PDMA0_TR_OUT[25]
P-DMA0 triggers
27
PDMA0_TR_OUT[26]
P-DMA0 triggers
28
PDMA0_TR_OUT[27]
P-DMA0 triggers
29
PDMA0_TR_OUT[28]
P-DMA0 triggers
30
PDMA0_TR_OUT[29]
P-DMA0 triggers
31
PDMA0_TR_OUT[30]
P-DMA0 triggers
34
PDMA0_TR_OUT[33]
P-DMA0 triggers
35
PDMA0_TR_OUT[34]
P-DMA0 triggers
37
PDMA0_TR_OUT[36]
P-DMA0 triggers
38
PDMA0_TR_OUT[37]
P-DMA0 triggers
43
PDMA0_TR_OUT[42]
P-DMA0 triggers
54
PDMA0_TR_OUT[53]
P-DMA0 triggers
55
PDMA0_TR_OUT[54]
P-DMA0 triggers
Datasheet
58
002-25756 Rev. *C
2022-10-07
TRAVEOTM T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4 dual
Triggers group inputs
Table 18-1
Input
56 57 58 62 63 64 65 66 67 72 73 82 83 84 85 86 87 88 89 90 91 93 94 95 97 98
99 101 102 103 105 106 107 109 110 111 113 114:115 117:118
Trigger inputs (continued) Trigger label (TRIG_LABEL)
PDMA0_TR_OUT[55] PDMA0_TR_OUT[56] PDMA0_TR_OUT[57] PDMA0_TR_OUT[61]
PDMA0_TR_OUT[62] PDMA0_TR_OUT[63] PDMA0_TR_OUT[64] PDMA0_TR_OUT[65]
PDMA0_TR_OUT[66] PDMA0_TR_OUT[71] PDMA0_TR_OUT[72] PDMA0_TR_OUT[81]
PDMA0_TR_OUT[82] PDMA0_TR_OUT[83] PDMA0_TR_OUT[84] PDMA0_TR_OUT[85]
PDMA0_TR_OUT[86] PDMA0_TR_OUT[87] PDMA0_TR_OUT[88] SCB_TX_TR_OUT[0]
SCB_TX_TR_OUT[1] SCB_TX_TR_OUT[3] SCB_TX_TR_OUT[4] SCB_TX_TR_OUT[5]
SCB_TX_TR_OUT[7] SCB_RX_TR_OUT[0] SCB_RX_TR_OUT[1] SCB_RX_TR_OUT[3]
SCB_RX_TR_OUT[4] SCB_RX_TR_OUT[5] SCB_RX_TR_OUT[7] SCB_I2C_SCL_TR_OUT[0]
SCB_I2C_SCL_TR_OUT[1] SCB_I2C_SCL_TR_OUT[3] SCB_I2C_SCL_TR_OUT[4]
SCB_I2C_SCL_TR_OUT[5] SCB_I2C_SCL_TR_OUT[7] CAN0_DBG_TR_OUT[0:1]
CAN0_FIFO0_TR_OUT[0:1]
Description
P-DMA0 triggers P-DMA0 triggers P-DMA0 triggers P-DMA0 triggers P-DMA0
triggers P-DMA0 triggers P-DMA0 triggers P-DMA0 triggers P-DMA0 triggers
P-DMA0 triggers P-DMA0 triggers P-DMA0 triggers P-DMA0 triggers P-DMA0
triggers P-DMA0 triggers P-DMA0 triggers P-DMA0 triggers P-DMA0 triggers
P-DMA0 triggers SCB0 TTCAN tx Triggers SCB1 TTCAN tx Triggers SCB3 TTCAN tx
Triggers SCB4 TTCAN tx Triggers SCB5 TTCAN tx Triggers SCB7 TTCAN tx Triggers
SCB0 TTCAN rx Triggers SCB1 TTCAN rx Triggers SCB3 TTCAN rx Triggers SCB4
TTCAN rx Triggers SCB5 TTCAN rx Triggers SCB7 TTCAN rx Trig
References
- Semiconductor & System Solutions - Infineon Technologies
- Semiconductor & System Solutions - Infineon Technologies
- Support: Live Chat Online, Tech Support & FAQ - Infineon Technologies
- Support: Live Chat Online, Tech Support & FAQ - Infineon Technologies
- Semiconductor & System Solutions - Infineon Technologies
- Semiconductor & System Solutions - Infineon Technologies
- Infineon Technologies Distributor | Mouser
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