Microsemi SmartFusion2 MSS DDR Bridge Installation Guide
- June 9, 2024
- Microsemi
Table of Contents
SmartFusion2 MSS
DDR Bridge Configuration
Configuration Options
The DDR bridge is a data bridge between four AHB bus masters and a single AXI bus slave. It accumulates AHB writes into write combining buffers prior to bursting out to external DDR memory. It also includes read combining buffers, enabling AHB masters to efficiently read data from the external DDR memory from a local buffer. The DDR bridge optimizes reads and writes from multiple masters to a single external DDR memory. Data coherency rules between the four masters and the external DDR memory are implemented in the hardware.
The DDR bridge contains three write combining / Read buffers and one read buffer. All buffers within the DDR bridge are implemented with latches and are not subject to the single event upsets (SEU’s) that SRAM exhibits. For complete details please refer to the Microsemi SmartFusion2 User’s Guide.
Configuration Options
Write Buffer Timing Out Counter – This is a 10-bit timer interface used to configure the timeout register in the write buffer module (Figure 1). Once the timer reaches the timeout value, a flush request is generated by the flush controller and if the response has been received for a previous write request from the write arbiter, this request is posted to the write arbiter. This register is common for all buffers.
Figure 1 · Configuring DDR Bridge
Non Bufferable Region Size – Use this option to set the size of non- bufferable address region.
Non Bufferable Region Address – Use this option to set the base address of a non-bufferable address region. Bits [15:(N – 1)] of this signal are compared with AHB address [31:(N + 15)] to check whether address is in non- bufferable region. The value of N depends on the non-bufferable region size, so the base address is defined according to the DDRB_NB_SZ register that holds the non-bufferable region size value defined in this configurator.
Enabling Write Combining Buffer – Use these options to enable the Write Combining Buffers for the DS, HPDMA and AHB Bus (SWITCH) Masters.
Enabling Read Buffer – Use these options to enable the Read Buffers for the DS, HPDMA and AHB Bus (SWITCH) and IDC Masters.
DDR Burst Size For Read/Write Buffers – Use this to configure the write buffer and read buffer size as per DDR burst size. The IDC read buffer has a fixed size of 32 bytes. Other buffers can be configured to 16-byte or 32-byte size.
A - Product Support
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Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization.
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Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more information and support. Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the website.
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Contacting the Customer Technical Support Center
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You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request.
The technical support email address is [email protected].
My Cases
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Outside the U.S.
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ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.
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References
- Microsemi | Semiconductor & System Solutions | Power Matters
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
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- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology