Microsemi DG0637 SmartFusion2 SoC FPGA CoreTSE_AHB User Guide

DG0637 SmartFusion2 SoC FPGA CoreTSE_AHB
User Guide

DG0637
Demo Guide
SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T
Loopback – Libero SoC v11.8

DG0637 SmartFusion2 SoC FPGA CoreTSE_AHB

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Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.
1.1 Revision 3.0
The following is a summary of the changes in revision 2.0 of this document.

• Libero SoC version was updated in the software requirements and in the demo design details. For more information, see Design Requirements, page 2, and Demo Design, page 3, respectively.

1.2 Revision 2.0
The following is a summary of the changes in revision 2.0 of this document.

• Libero SoC, Flash Pro, and Soft Console design requirements were updated. For more information, see Design Requirements, page 2.
• Throughout the document, the names of Soft Console projects used in the demo design and all the associated figures were updated.

1.3 Revision 1.0
Revision 1.0 was the first publication of this document.

SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo

Microsemi Triple-Speed Ethernet MAC, CoreTSE_AHB is a configurable soft intellectual property (IP) core that complies with the IEEE 802.3 standard.
This demo design provides an Ethernet solution for the Smart Fusion ® 2 SoC FPGA and implements a CoreTSE_AHB-based 1000 Base-T loopback design on the SmartFusion2 Security Evaluation Kit. CoreTSE_AHB enables system designers to implement a broad range of Ethernet designs, from low-cost 10/100 Ethernet to higher-performance 1 gigabit ports. CoreTSE_AHB suits networking equipment’s such as switches, routers, and data acquisition systems. Cortes is also available in a version that works with IGLOO ® 2 FPGA family.

CoreTSE_AHB has the following interfaces:

• 10/100/1000 Mbps Ethernet MAC with a gigabit media independent interface (GMII) and ten bit interface (TBI) to support serial gigabit media independent interface  (SGMII), 1000BASE-T, and 1000BASE-X
• GMII or TBI physical layer interface connects to Ethernet PHY
• MAC data path interface
• Advanced peripheral bus (APB) slave interface for MAC configuration registers and status counter access

CoreTSE_AHB can be configured as GMII or TBI for Ethernet network at 10/100/1000 Mbps data transfer rates (line speeds).
The Core TSE IP is available in two different versions:

• CoreTSE_AHB: Uses AHB interface for both the transmit and receive paths. This IP works for SmartFusion2 SoC FPGA.
• Core TSE (Non-AMBA): Uses direct access to the MAC with a streaming packet interface. This IP works for IGLOO2 FPGA and SmartFusion2 SoC FPGA.
  Core TSE and CoreTSE_AHB are identical to MSS hard Ethernet MAC in SmartFusion2 with respect to the supported features, register configuration, and register  addresses. Multiple instances of the Core TSE IP can be used to achieve Ethernet solutions in SmartFusion2 devices. The CoreTSE_AHB IP, along with MSS Ethernet  MAC, can be used to support multiple Ethernet interfaces for SmartFusion2 devices. For more information about CoreTSE_AHB, see to the CoreTSE_AHB  Handbook.
  For more information about Ethernet applications, see the AC423: SmartFusion2/IGLOO2 Ethernet Application Note.

Note: CoreTSE_AHB requires a license for use in the Libero® SoC design suite. For license request, send an email to soc_marketing@microsemi.com.

2.1 Design Requirements
The following table lists the design requirements for running the demo.
Table 1 • Design Requirements

SmartFusion2 Security Evaluation Kit:
• 12 V adapter
• FlashPro4 programmer| Rev D or later
Host PC or Laptop (12 GB RAM)| Windows 64-bit Operating System
Spirent Test Center (Optional)|
Software Requirements|
---|---
Libero SoC| 11.8
FlashPro Programming Software| 11.8
SoftConsole| v4.0
Cat Karat Packet Generator Software Wireshark Software| Provided with design files
Wireshark Software| Provided with design files
IP Requirements|
CoreTSE_AHB| License provided on request. Send an email to soc_marketing@microsemi.com.

2.2 Demo Design
The demo design files are available for download at: http://soc.microsemi.com/download/rsc/?f=m2s_dg0637_liberov11p8_df
The demo design files include:

• Libero project
• Programming files
• Source files
• Readme.txt file

See the Readme.txt file for the complete directory structure.
The following figure shows the top-level structure of the design files.

The following figure shows the demo design block diagram.

In this demo design, CoreTSE_AHB is instantiated in the FPGA fabric and connected to the on-board Ethernet PHY using high-speed serial interface (SERDES_IF).
In the previous figure, the dotted arrow in red shows the transfer of Ethernet packet from the host PC to the internal LSRAM and the dotted arrow in blue shows the  retransmission of packet from LSRAM to the host.
2.2.1 Design Features
The demo design performs Ethernet loopback using CoreTSE_AHB in TBI 1000 Base-T on hardware and also in simulation.
Following are the demo design features:
• Simulation model for CoreTSE_AHB loopback design.
• CoreTSE_AHB loopback design on SmartFusion2 Security Evaluation Kit.
The following section explains the initialization and configuration of CoreTSE_AHB, SERDES_IF, and the loopback mechanism.
2.2.1.1 High-Speed Serial Interface Configuration
During the design process, CoreTSE_AHB was configured to present a Ten Bit Interface (TBI) to the
SERDESIF block, which is configured for External Physical Coding Sub Layer (EPCS) operation using
lane 3 to create an SGMII link to the external physical-layer (PHY) device.
2.2.1.2 CoreTSE_AHB IP MAC Initialization
At power-up, firmware running on the Cortex-M3 processor will initialize control registers in
CoreTSE_AHB and the external PHY device to place them in 1000 Base-T mode.
2.2.1.3 Ethernet Packet Loopback Mechanism
The following Ethernet loopback mechanism is used in this demo:
2.2.1.3.1 Ethernet Packet Reception
CoreTSE_AHB receives the Ethernet packet from the on-board Ethernet PHY through high-speed SERDES_IF.
CoreTSE_AHB receive (RX) path is connected to LSRAM through the AHB interface. The Cortex- M3 processor moves the Ethernet packet data to the LSRAM memory using DMA.
2.2.1.3.2 Ethernet Packet Transmission
To loop back the Ethernet packet, the Cortex-M3processor reads the Ethernet packet data from LSRAM memory through AHB interface and forwards it to it on the  CoreTSE_AHB transmit (TX) path.
CoreTSE_AHB transmits the Ethernet packet to the on-board Ethernet PHY through high-speed SERDES.
2.2.1.4 Ethernet Test Solution
There are many ways to evaluate the CoreTSE_AHB 1000 Base-T loopback demo on the SmartFusion2 Security Evaluation board.
2.2.1.4.1 Solution 1

• The Cat Karat packet generator software installed on the host PC is used to transmit the Ethernet packet through RJ45 Ethernet copper cable.
• The Wireshark packet receiver software installed on the host PC captures the Ethernet packet (loopback) through RJ45 Ethernet copper cable.

2.2.1.4.2 Solution 2
Spirent test center or an equivalent solution can be used to test the CoreTSE_AHB loopback demo. For more information, see Appendix: Running the Demo Design Using Spirent Test Center, page 14.
2.2.2 Design Description
This demo design is implemented by configuring the CoreTSE_AHB for the TBI mode. The following figure shows the Libero SoC hardware implementation for this demo design.

Libero hardware project uses the following resources:

• CoreTSE_AHB
• Cortex M3 (microcontroller sub system) to configure CoreTSE_AHB and on-board Ethernet PHY
• High-speed serial interface (SERDES_IF) configured for EPCS lane 3 mode
• Soft Console – application for initializing the CoreTSE_AHB and for transferring the Ethernet packet data to/from LSRAM
• Dedicated input pad 0 as the clock source

2.3 Simulating the Design
A test bench design is created for CoreTSE_AHB loopback demo. The test bench transmits the Ethernet packet to CoreTSE_AHB loopback demo design and receives the loopback Ethernet packet from the CoreTSE_AHB loopback demo design.
The design uses bus functional model (BFM) simulation for initializing the Core TSE with the required configuration. The user.bfm file under the