Microsemi UG0950 DDR AXI4 Arbiter IP User Guide

Microsemi UG0950 DDR AXI4 Arbiter IP

Product Information

The Microsemi DDR_AXI4_Arbiter is a hardware implementation device that is commonly used in video and graphics applications. It is designed to support Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) for fast processing in video systems.
The device is equipped with key features such as design description, inputs and outputs, configuration parameters, and timing diagram for efficient functionality.

Key Features

• Supports DDR SDRAM
• Efficient design description
• Multiple inputs and outputs
• Configurable parameters for customization
• Timing diagram for accurate performance evaluation

Supported Families

The DDR_AXI4_Arbiter is designed to support a wide range of families for video and graphics applications.

Product Usage Instructions

To use the Microsemi DDR_AXI4_Arbiter device, follow the installation instructions provided in the user manual. The device should be installed by a qualified technician to ensure proper functionality. Once installed, the device can be configured using the configuration parameters provided in the user manual. The timing diagram should be used to evaluate the performance of the device. In case of any issues or queries regarding the device, contact Microsemi sales support through the provided contact information.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.
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Revision History
The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.
Revision 1.0
The first publication of this document.

Introduction

Memories are an integral part of any typical video and graphics application. They are used for buffering video pixel data. One common buffering example displays frame buffers in which the complete video pixel data for a frame is buffered in the memory.
Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is one of the commonly used memories in video applications for buffering. SDRAM is used because of its speed which is required for fast processing in video systems.

Hardware Implementation

Design Description

The DDR AXI4 Arbiter provides an AXI4 master interface to the DDR on-chip controllers. The arbiter supports up to eight write channels and eight read channels. The block arbitrates between eight read channels to provide access to the AXI read channel in a first-come first-serve manner. The same way the block arbitrates between eight write channels to provide access to the AXI write channel in a first-come first-serve manner. All the eight read and write channels have equal priority. The AXI4 master interface of the Arbiter IP can be configured for various data widths ranging from 32 bits to 512 bits.
The following figure shows the top-level pin-out diagram of the DDR AXI4 Arbiter.
Top-level pin-out block diagram for Native Arbiter Interface
Top-level block diagram for Arbiter Bus Interface
A read transaction is triggered by setting the input signal r(x)_req_i high on a particular read channel. The arbiter responds by acknowledgment when it is ready to service the read request. Then it samples the starting AXI address and read burst size which are input from the external master. The channel processes the inputs and generates the required AXI transactions to read data from the DDR memory. The read data output from arbiter is common to all the read channels. During data read out, the read data valid of the corresponding channel goes high. The end of the read transaction is denoted by a read done signal when all the requested bytes are sent out.
Similar to a read transaction, a write transaction is triggered by setting the input signal w(x)_req_i high. Along with the request signal, the write start address and the burst length must be provided during the request. When the arbiter is available to service the write request, it responds by sending an acknowledgment signal on corresponding channel. Then the user has to provide the write data along with the data valid signal on the channel. The number of clocks the data valid high period should match the burst length. The arbiter completes the write operation and sets the write done signal high denoting the completion of write transaction.

Inputs and Outputs

The following table lists the inputs and output ports of the DDR AXI4 Arbiter for Bus interface.
Input and Output Ports for Arbiter Bus Interface








Input and Output ports for Native Arbiter Interface

Configuration Parameters

The following table lists the configuration parameters used in the hardware implementation of the DDR AXI4 Arbiter. These are generic parameters and can be varied based on the application requirements.

Timing Diagram

The following figure shows the connection of the read and write request inputs, starting memory address, write inputs from the external master, read or write acknowledgment, and read or write completion inputs given by arbiter.
Timing Diagram for Signals used in Writing/Reading through AXI4 Interface
The following figure shows the connection between the write data input from the external master along with the data input valid. This is same for eight write channels.
Timing Diagram for Writing into Internal Memory
The following figure shows the connection between the read data output towards the external master along with the data output valid for all the eight read channels.
Timing Diagram for Data Received through DDR AXI4 Arbiter for Read Channels
License
The IP can be used in RTL mode without any license.

Installation Instructions

The core must be installed into Libero software. It is done automatically through the Catalog update function in Libero, or the CPZ file can be manually added using the Add Core catalog feature. Once the CPZ file is installed in Libero, the core can be configured, generated, and instantiated within SmartDesign for inclusion in the Libero project.
For further instructions on core installation, licensing, and general use, refer to the Libero SoC Online Help.

Resource Utilization

DDR AXI4 Arbiter block is implemented on a PolarFire® FPGA (MPF300T -1FCG1152E package) for four write channels and four read channels configuration.

References

• Microsemi | Semiconductor & System Solutions | Power Matters
• microsemi.com/index.php?option=com_docman&task=doc_download&gid=132044

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