Actel SmartDesign MSS ACE Simulation User Guide

Actel SmartDesign MSS ACE Simulation

Product Information: SmartDesign MSS ACE Simulation

The SmartDesign MSS ACE Simulation is a feature that allows simulation of the ACE functionality in ModelSimTM. It provides users with a way to verify that their configuration works based on their system input. This tool is a part of the SmartFusion MSS, and it includes a library of analog drivers functions. The tool provides a simple example of simulating ACE, and the user manual provides detailed instructions for users to get started.

Creating the Design

To create a design using the SmartDesign MSS ACE Simulation tool, users will need to follow these steps:

1. Configure MSS: Disable peripherals that are not needed and create a simple ACE configuration.
2. Create a top-level SmartDesign wrapper and instantiate the configured MSS component.
3. Prepare the testbench: Customize the basic testbench to include ACE simulations.

Configuring MSS

In this step, users will need to disable the peripherals that are not needed for their specific configuration. The following peripherals can be disabled:

• UARTs
• SPIs
• I2Cs
• MAC
• Fabric Interface
• External Memory Controller

After disabling unnecessary peripherals, users can create a simple ACE configuration consisting of a single ADC Direct Input service with a few flags and a sampling sequence loop. The Flag mapping feature can be used to determine which Flag register and bits flags were mapped to. Once the configuration is complete, the MSS design can be generated.

Preparing the Testbench

The final step is to prepare the testbench. SmartDesign automatically generates a testbench.v file that is useful for basic simulations. However, users will need to customize this file to include ACE simulations. Users can create a custom testbench by following these steps:

1. Open the Files tab in the Project Manager to view the file hierarchy.
2. Locate the testbench.v file and customize it to include ACE simulations.

Once the testbench is customized, users can simulate the ACE functionality in ModelSimTM.

SmartDesign MSS
ACE Simulation

Introduction

The ACE functionality can be simulated in ModelSim™ to verify that your configuration works based on your system input. This document walks through a simple example of simulating the ACE. Please refer to Simulating the Microcontroller Subsystem for a more general overview of the simulation strategy for SmartFusion MSS. Details about the analog driver functions that are available in the SmartFusion library are at the end of this document in the Analog Drivers section.

Creating the Design
We will create a simple SmartFusion MSS and ACE configuration to demonstrate how you can simulate the ACE.

Configuring MSS
We’ll disable the following peripherals since we will not be using them in this example:

• UARTs
• SPIs
• I2Cs
• MAC
• Fabric Interface
• External Memory Controller

We’ll create a simple ACE configuration consisting of a single “ADC Direct Input” service with a few flags, and a simple sampling sequence loop. The configuration is shown below.

We use the Flags tab to determine which Flag register and bits our flags were mapped to. This is useful when we write our BFM script later (as shown in the figure below).

The Flag mapping tells us that

• OVER1V was mapped to PPE_FLAGS0 register, bit 0
• OVER2V was mapped to PPE_FLAGS0 register, bit 1
• UNDER1V was mapped to PPE_SFFLAGS0 register, bit 0

Our MSS design should look like this after configuration:

Generate the MSS
Creating Top Level SmartDesign Wrapper
Create a top level SmartDesign component and instantiate our newly configured MSS component. Set the top level SmartDesign as root, and generate the SmartDesign.

Preparing the Testbench

Now that the design is generated, let’s open up two files that we’ll need for simulation purposes.
Go to the Libero® IDE Project Manager Files tab and open the testbench.v and user.bfm from your MSS component (as shown in the figure below).

Creating a Custom Testbench

The testbench.v file that is automatically generated by SmartDesign is useful for basic simulations, but for ACE simulations we will need to customize this basic testbench.
To create a new testbench:

1. From the Libero IDE Project Manager choose File > New.
   a. Select HDL Stimulus File
   b. Name the file ace_testbench and click OK.

2. Copy and paste the contents of testbench.v to ace_testbench. We now have a testbench that we can customize for ACE simulations.

3. Add a simple SmartFusion CAE library analog driver function to drive our analog input service ADCDirectInput. The following code fragment should be added to your testbench. A voltage value is ramped up, then down.

Notice the drive_analog_input function that is used to convert the real value into a value that can be driven into the analog port. Refer to the CAE Analog Drivers section for more details.

Modifying our BFM Script
We will create a simple BFM script that just loops and reads our PPE registers. This mimics a Cortex M3 polling scheme. The addresses of the PPE_FLAGSn and PPE_SFFLAGS registers are available in the SmartFusion Handbook. It is also shown in the Flags tab in the ACE configurator, in addition to the bit in which the flag is assigned to in the register.
In the user.bfm script file, we will add these commands:

In this script, we continually read the PPE_FLAGS0 and PPE_SFFLAGS register addresses into 2 data variables. If we wanted to create a more complex scenario, we could take those values and write them to GPIOs or perform other actions in our BFM commands based upon their value.

Associating our Custom Testbench with our Design
We need to tell the Libero IDE to use our custom testbench for simulation instead of the system generated one.

1. Right-click the SDTOP component in the Project Manager Design Hierarchy and choose Organize Stimulus
2. We want to use ace_testbench instead of testbench.v. So select testbench.v from the right panel and click Remove. Then select ace_testbench.v from the left panel and click Add.
3. Click OK

Simulate
Now we’re ready to simulate.

• In the Project Manager Project Flow window click the ModelSim button.
• In ModelSim’s command window type run 3ms. In our example, we are running for 3ms because we have a long hardcoded delay in our testbench, because we want to ensure that the ADC calibration is completed before we begin processing.

CAE Analog Drivers

• Analog ports are represented by a 1-bit wide port in both the Verilog and VHDL simulation models. Driver modules are developed to drive a real value through a 1-bit port and to read an analog value from a 1-bit port.
• The drive module/function serializes and streams the real value represented in floating point representation (64-bit value) in zero simulation time, using delta delays. The read module deserializes a stream into a 64-bit value.

Interfaces of all the drivers are given later in respective testbenches

• drive_analog_io and drive_analog_input can drive an analog input. Input is provided to this module as 64 bit value.
• read_analog_io can read any analog signal coming from the Analog Block. Output is provided as a 64 bit value.
• drive_temperature_monitor is used to drive the temperature pad. This module takes temperature in Celsius and converts it into a voltage and drives it over the digital input.
• drive_current_monitor or drive_current_inputs can be used to drive the current pad that will be used for Current Monitoring. As an input it takes the voltage at AT pad, the resistor and current values, to calculate the voltage on the AC quad.
  • Equation is AC(V) = AT(V) + Resistor * current
  • Interface information of both the drivers is given below

Connecting Analog Ports with Verilog

Use $realtobits function to convert the real value to 64 bit value or $bitstoreal function can be used to convert the data from 64 bit to real value.
The following shows the analog drivers that are available in Verilog:

The following testbench demonstrates the usage of all drivers.

Connecting Analog Ports with VHDL
realtobits function (equivalent to $realtobits system task in verilog) and bitstoreal function (equivalent to $bitstoreal in verilog ) are available in float_pkg package present in smartfusion library. Notice that this package is added to the testbench at the beginning. realtobits can be used to convert the real value to 64 bit floating point representation. bitstoreal function is available in float_pkg package to convert this 64 bit value to a real value.
The following testbench demonstrates the usage of all drivers.

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References

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