Microsemi SmartFusion2 DDR Controller and Serial High Speed Controller User Guide

SmartFusion2
DDR Controller and Serial High Speed Controller
Initialization Methodology
User Guide

Introduction

When creating a design using a SmartFusion2 device, if you use one of the two DDR controllers (FDDR or MDDR) or any of the Serial High speed controller (SERDESIF) blocks, you must initialize the configuration registers of these blocks at run-time before they can be used. For example, for the DDR controller, you must set the DDR mode (DDR3/DDR2/LPDDR), PHY width, burst mode and ECC.
Similarly, for the SERDESIF block used as a PCIe endpoint, you must set the PCIE BAR to AXI (or AHB) window.
This document describes the steps necessary to create a Libero design that automatically initializes the DDR controller and SERDESIF blocks at power up. It also describes how to generate the firmware code from Libero SOC that is used in the embedded design flow.
A detailed description of the theory of operations is provided first.
The next section describes how to create such a design using the Libero SoC System Builder, a powerful design tool that, among other features, creates the ‘initialization’ solution for you if you are using DDR or SERDESIF blocks in your design.
The next section describes how to put a complete ‘initialization’ solution together without using the SmartFusion2 System Builder. This helps explain what needs to be done if you do not wish to use the System Builder, and also describes what the System Builder tool actually generates for you. This section addresses:

• The creation of the configuration data for DDR controller and SERDESIF configuration registers
• The creation of the FPGA logic required to transfer the configuration data to the different ASIC configuration registers

Finally we describe the generated files related to:

• The creation of firmware ‘initialization’ solution.
• The simulation of the design for the DDR ‘initialization’ solution.

For details about the DDR controller and SERDESIF configuration registers, refer to the Microsemi SmartFusion2 High Speed Serial and DDR Interfaces User’s Guide.

Theory of Operation

The Peripheral initialization solution uses the following major components:

• The CMSIS SystemInit() function, which runs on the Cortex-M3 and orchestrates the initialization process.
• The CoreConfigP soft IP core, which initializes the peripherals’ configuration registers.
• The CoreResetP soft IP core, which manages the reset sequence of the MSS, DDR controllers, and SERDESIF blocks..

The peripheral initialization process works as follows:

1. Upon reset, the Cortex-M3 runs the CMSIS SystemInit() function. This function is automatically executed before the application’s main() function is executed.
   The CoreResetP output signal MSS_HPMS_READY is asserted at the beginning of the initialization process, indicating that the MSS and all the peripherals (except MDDR) are ready for communication.

2. The SystemInit() function writes configuration data to the DDR controllers and SERDESIF configuration registers via the MSS FIC_2 APB3 bus. This interface is connected to the soft CoreConfigP core instantiated in the FPGA fabric.

3. After all the registers are configured, the SystemInit() function writes to the CoreConfigP control registers to indicate the completion of the register configuration phase; the CoreConfigP output signals CONFIG1_DONE and CONIG2_DONE are then asserted.
   There are two phases of register configuration (CONFIG1 and CONFIG2) depending upon the peripherals used in the design.

4. If one or both of MDDR/FDDR are used, and none of the SERDESIF blocks are used in the design, there is only one register configuration phase. Both the CoreConfigP output signals CONFIG1_DONE and CONIG2_DONE are asserted one after the other without any wait/delay.
   If one or more SERDESIF blocks in non-PCIe mode are used in the design, there is only one phase of register configuration. CONFIG1_DONE and CONIG2_DONE are asserted one after the other without any wait/delay.
   If one or more SERDESIF blocks in PCIe mode are used in the design, there are two phases of register configuration. CONFIG1_DONE is asserted after the first phase of register configuration is complete. SERDESIF system and lane registers are configured in this phase. If SERDESIF is configured in a non- PCIE mode, CONFIG2_DONE signal is also asserted immediately.

5. The second phase of register configuration then follows (if SERDESIF is configured in PCIE mode). The following are the different events that happen in the second phase:
   – CoreResetP de-asserts PHY_RESET_N and CORE_RESET_N signals corresponding to each of the SERDESIF blocks used. It also asserts an output signal SDIF_RELEASED after all the SERDESIF blocks are out of reset. This SDIF_RELEASED signal is used to indicate to the CoreConfigP that the SERDESIF core is out of reset and is ready for the second phase of register configuration.
   – Once the SDIF_RELEASED signal is asserted, the SystemInit() function starts polling for the assertion of PMA_READY on the appropriate SERDESIF lane. Once the PMA_READY is asserted, the second set of SERDESIF registers (PCIE registers) are configured/written by the SystemInit() function.

6. After all the PCIE registers are configured, the SystemInit() function writes to the CoreConfigP control registers to indicate the completion of the second phase of register configuration; the CoreConfigP output signal CONIG2_DONE is then asserted.

7. Apart from the above signal assertions/de-assertions, CoreResetP also manages the initialization of the various blocks by performing the following functions:
   – De-asserting the FDDR core reset
   – De-asserting the SERDESIF blocks PHY and CORE resets
   – Monitoring of the FDDR PLL (FPLL) lock signal. The FPLL must have locked to guarantee that the FDDR AXI/AHBLite data interface and the FPGA fabric can communicate correctly.
   – Monitoring of the SERDESIF block PLL (SPLL) lock signals. The SPLL must have locked to guarantee that the SERDESIF blocks AXI/AHBLite interface (PCIe mode) or XAUI interface can communicate properly with the FPGA fabric.
   – Waiting for the external DDR memories to settle and be ready to be accessed by the DDR controllers.

8. When all peripherals have completed their initialization, CoreResetP asserts the INIT_DONE signal; the CoreConfigP internal register INIT_DONE is then asserted.
   If one or both of MDDR/FDDR are used, and the DDR initialization time is reached, CoreResetP output signal DDR_READY is asserted. Assertion of this signal DDR_READY can be monitored as an indication that the DDR (MDDR/FDDR) is ready for communication.
   If one or more SERDESIF blocks are used, and the second phase of register configuration is successfully completed, CoreResetP output signal SDIF_READY is asserted. Assertion of this signal SDIF_READY can be monitored as an indication that all the SERDESIF blocks are ready for communication.

9. The SystemInit() function, which has been waiting for INIT_DONE to be asserted, completes, and the application’s main() function is executed. At that time, all used DDR controllers and SERDESIF blocks have been initialized, and the firmware application and the FPGA fabric logic can reliably communicate with them.

The methodology described in this document relies on the Cortex-M3 executing the initialization process as part of the system initialization code executed before the application’s main()function.
See the Flow Charts in Figure 1-1, Figure 1-2 and Figure 1-3 for the Initialization steps of FDDR/MDDR, SEREDES(non-PCIe mode) and SERDES (PCIe mode).
Figure 1-4 shows a Peripheral Initialization timing diagram.

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Figure 1-3 • SERDESIF (PCIe) Initialization Flow Chart
The initialization procedure described in this document requires you to run Cortex-M3 during the initialization process, even if you are not planning on running any code on the Cortex-M3. You must create a basic firmware application that does nothing (a simple loop, for example) and load that executable in the embedded Non Volatile Memory (eNVM) so the DDR controllers and SERDESIF blocks are initialized when the Cortex-M3 boots.

Using System Builder to Create a Design Using DDR and SERDESIF Blocks

The SmartFusion2 System Builder is a powerful design tool that helps you capture your system-level requirements and produces a design implementing those requirements. A very important function of the System Builder is the automatic creation of the Peripheral Initialization sub-system. “Using SmartDesign to Create a Design Using DDR and SERDESIF Blocks” on page 17 describes in detail how to create such a solution without the System Builder.
If you are using System Builder, you must perform the following tasks to create a design that initializes your DDR controllers and SERDESIF blocks at power up:

1. In the Device Features page (Figure 2-1), specify which DDR controllers are used and how many SERDESIF blocks are used in your design.
2. In the Memory page, specify the type of DDR (DDR2/DDR3/LPDDR) and the configuration data for your external DDR memories. See the Memory Page section for details.
3. In the Peripherals page, add fabric masters configured as AHBLite/AXI to the Fabric DDR Subsystem and/or MSS DDR FIC Subsystem (optional).
4. In the Clock Settings page, specify the clock frequencies for the DDR sub-systems.
5. Complete your design specification and click Finish. This generates the System Builder created design, including the logic necessary for the ‘initialization’ solution.
6. If you are using SERDESIF blocks, you must instantiate the SERDESIF blocks in your design and connect their initializations ports to those of the System Builder generated core.

System Builder Device Features Page
In the Device Features page, specify which DDR controllers (MDDR and/or FDDR) are used and how many SERDESIF blocks are used in your design (Figure 2-1).

Figure 2-1 • System Builder Device Features Page

System Builder Memory Page
To use the MSS DDR (MDDR) or Fabric DDR (FDDR), select the Memory Type from the drop-down list (Figure 2-2).

Figure 2-2 • MSS External Memory

You must:

1. Select the DDR type (DDR2, DDR3 or LPDDR).
2. Define the DDR memory settling time. Consult your external DDR Memory Specifications to set the correct memory setting time. The DDR memory may fail to initialize correctly if the memory settling time is not correctly set.
3. Either import the DDR register configuration data or set your DDR Memory Parameters. For details, refer to the Microsemi SmartFusion2 High Speed Serial and DDR Interfaces User’s Guide.

This data is used to generate the DDR register BFM and firmware configuration files as described in the “Creating and Compiling the Firmware Application” on page 26 and “BFM Files Used for Simulating the Design” on page 27. For details on DDR controller configuration registers, refer to the Microsemi SmartFusion2 High Speed Serial and DDR Interfaces User’s Guide.
An example of the configuration file syntax is shown in Figure 2-3. The register names used in this file are the same as those described in the Microsemi SmartFusion2 High Speed Serial and DDR Interfaces User’s Guide

Figure 2-3 • Configuration File Syntax Example
System Builder Peripherals Page
In the Peripherals page, for each DDR controller a separate subsystem is created (Fabric DDR Subsystem for FDDR and MSS DDR FIC Subsystem for MDDR). You can add a Fabric AMBA Master (configured as AXI/AHBLite) core to each of these subsystems to enable fabric master access to the DDR controllers. Upon generation, System Builder automatically instantiates bus cores (depending on the type of AMBA Master added) and exposes the master BIF of the bus core and the clock and reset pins of the corresponding subsystems (FDDR/MDDR) under appropriate pin groups, to the top. All you have to do is connect the BIFs to the appropriate Fabric Master cores that you would instantiate in the design. In the case of MDDR, it is optional to add a Fabric AMBA Master core to the MSS DDR FIC Subsystem; Cortex-M3 is a default master on this subsystem. Figure 2-4 shows the System Builder Peripherals Page.

Figure 2-4 • System Builder Peripherals Page

System Builder Clock Settings Page
In the Clock Settings page, for each DDR controller, you must specify the clock frequencies related to each DDR (MDDR and/or FDDR) sub-system.
For MDDR, you must specify:

• MDDR_CLK – This clock determines the operating frequency of the DDR Controller and should match the clock frequency you wish your external DDR memory to run at. This clock is defined as a multiple of the M3_CLK (Cortex-M3 and MSS Main Clock, Figure 2-5). The MDDR_CLK must be less than 333 MHz.
• DDR_FIC_CLK – If you have chosen to also access the MDDR from the FPGA fabric, you need to specify the DDR_FIC_CLK. This clock frequency is defined as ratio of the MDDR_CLK and should match the frequency at which the FPGA fabric sub-system that accesses the MDDR is running.

Figure 2-5 • Cortex-M3 and MSS Main Clock; MDDR Clocks

For FDDR, you must specify:

• FDDR_CLK – Determines the operating frequency of the DDR Controller and should match the clock frequency at which you wish your external DDR memory to run. Note that this clock is defined as a multiple of the M3_CLK (MSS and Cortex-M3 clock, Figure 2-5). The FDDR_CLK must be within 20 MHz and 333 MHz.
• FDDR_SUBSYSTEM_CLK – This clock frequency is defined as a ratio of the FDDR_CLK and should match the frequency at which the FPGA fabric sub-system that accesses the FDDR is running.

Figure 2-6 • Fabric DDR Clocks
SERDESIF Configuration
The SERDESIF blocks are not instantiated in the System Builder generated design. However, for all the SERDESIF blocks, initialization signals are available at the interface of the System Builder core and can be connected to the SERDESIF cores at the next level of hierarchy, as shown in Figure 2-7. Figure 2-7 • SERDESIF Peripheral Initialization Connectivity
Similar to the DDR configuration registers, each SERDES block also has configuration registers that must be loaded at runtime. You can either import these register values or use the High Speed Serial Interface Configurator (Figure 2-8) to enter your PCIe or EPCS parameters and the register values are automatically computed for you. For details, refer to the SERDES Configurator User’s Guide. Figure 2-8 • High Speed Serial Interface Configurator
Once you have integrated your user logic with the System Builder block and SERDES block, you can generate your top level SmartDesign. This generates all HDL and BFM files that are necessary to implement and simulate your design. You can then proceed with the rest of the Design Flow.

Using SmartDesign to Create a Design Using DDR and SERDESIF Blocks

This section describes how to put a complete ‘initialization’ solution together without using the SmartFusion2 System Builder. The goal is to help you understand what you must do if you do not wish to use the System Builder. This section also describes what the System Builder tool actually generates for you. This section describes how to:

• Input the configuration data for DDR controller and SERDESIF configuration registers.
• Instantiate and connect the Fabric Cores required to transfer the configuration data to the DDR controllers and SERDESIF configuration registers.

DDR Controller Configuration
The MSS DDR (MDDR) and Fabric DDR (FDDR) controllers must be configured dynamically (at runtime) to match the external DDR memory configuration requirements (DDR mode, PHY width, burst mode, ECC, etc.). Data entered in MDDR/FDDR configurator is written to the DDR controller configuration registers by the CMSIS SystemInit() function. The Configurator has three different tabs for entering different types of configuration data:

• General data (DDR mode, Data Width, Clock Frequency, ECC, Fabric Interface, Drive Strength)
• Memory Initialization data (Burst Length, Burst Order, Timing Mode, Latency, etc.)
• Memory Timing data

Refer to the specifications of your external DDR memory and configure the DDR Controller to match the requirements of your external DDR memory.
For details on DDR configuration, refer to the SmartFusion2 MSS DDR Configuration User Guide.
SERDESIF Configuration
Double-click the SERDES block in the SmartDesign canvas to open the Configurator to configure the SERDES (Figure 3-1). You can either import these register values or use the SERDES configurator to enter your PCIe or EPCS parameters and the register values is automatically computed for you. For details, refer to the SERDES Configurator User’s Guide. Figure 3-1 • High Speed Serial Interface Configurator
Creating the FPGA Design Initialization Sub-System
To initialize the DDR and SERDESIF blocks, you must create the initialization subsystem in the FPGA fabric. The FPGA fabric initialization subsystem moves data from the Cortex-M3 to the DDR and SERDESIF configuration registers, manages the reset sequences required for these blocks to be operational and signals when these blocks are ready to communicate with the rest of your design. To create the initialization subsystem, you must:

• Configure FIC_2 inside the MSS
• Instantiate and configure the CoreConfigP and CoreResetP cores
• Instantiate the on-chip 25/50MHz RC oscillator
• Instantiate the System Reset (SYSRESET) macro
• Connect these components to each peripheral’s configuration interfaces, clocks, resets and PLL lock ports

MSS FIC_2 APB Configuration
To configure the MSS FIC_2:

1. Open the FIC_2 configurator dialog box from the MSS configurator (Figure 3-2).

2. Select Initialize peripherals using Cortex-M3.

3. Depending on your system, check one or both of the following checkboxes:
   – MSS DDR
   – Fabric DDR and/or SERDES Blocks

4. Click OK and proceed to generate the MSS (you may defer this action until you have fully configured the MSS to your design requirements). The FIC_2 ports (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK and FIC_2_APB_M_RESET_N) are now exposed at the MSS interface and can be connected to the CoreConfigP and CoreResetP cores.

Figure 3-2 • MSS FIC_2 Configurator

CoreConfigP
To configure CoreConfigP:

1. Instantiate CoreConfigP into your SmartDesign (typically the one where the MSS is instantiated).
   This core can be found in the Libero Catalog (under Peripherals).

2. Double-click the core to open the configurator.

3. Configure the core to specify which peripherals need to be initialized (Figure 3-3)

Figure 3-3 • CoreConfigP Dialog Box

CoreResetP
To configure CoreResetP:

1. Instantiate CoreResetP into your SmartDesign (typically the one where the MSS is instantiated).
   This core can be found in the Libero Catalog, under Peripherals.

2. Double-click the core inside the SmartDesign Canvas to open the Configurator (Figure 3-4).

3. Configure the core to:
   – Specify the external reset behavior (EXT_RESET_OUT asserted). Choose one of four options:
   o EXT_RESET_OUT is never asserted
   o EXT_RESET_OUT is asserted if power up reset (POWER_ON_RESET_N) is asserted
   o EXT_RESET_OUT is asserted if FAB_RESET_N is asserted
   o EXT_RESET_OUT is asserted if power up reset (POWER_ON_RESET_N) or FAB_RESET_N is asserted
   – Specify the Device Voltage. The selected value should match the voltage you selected in the Libero Project Settings dialog box.
   – Check the appropriate checkboxes to indicate which peripherals you are using in your design.
   – Specify the external DDR memory setting time. This is the maximum value for all DDR memories used in your application (MDDR and FDDR). Refer to the external DDR memory vendor datasheet to configure this parameter. 200us is a good default value for DDR2 and DDR3 memories running at 200MHz. This is a very important parameter to guarantee a working simulation and a working system on silicon. An incorrect value for the settling time may result in simulation errors. Refer to the DDR memory vendor datasheet to configure this parameter.
   – For each SERDES block in your design, check the appropriate boxes to indicate whether:
   o PCIe is used
   o Support for PCIe Hot Reset is required
   o Support for PCIe L2/P2 is required

Note: If you are using the 090 die(M2S090) and your design uses SERDESIF, you do not have to check any of the following checkboxes: ‘Used for PCIe’, ‘Include PCIe HotReset support’ and ‘Include PCIe L2/P2 support’. If you are using any non-090 device and using one or more SERDESIF blocks, you have to check all four checkboxes under the appropriate SERDESIF section.
Note: For details on the options available to you in this configurator, refer to the CoreResetP Handbook.

Figure 3-4 • CoreResetPConfigurator

25/50MHz Oscillator Instantiation
CoreConfigP and CoreResetP are clocked by the on-chip 25/50MHz RC oscillator. You must instantiate a 25/50MHz Oscillator and connect it to these cores.

1. Instantiate the Chip Oscillators core into your SmartDesign (typically the one where the MSS is instantiated). This core can be found in the Libero Catalog under Clock & Management.
2. Configure this core such that the RC oscillator drives the FPGA fabric, as shown in Figure 3-5.

Figure 3-5 • Chip Oscillators Configurator

System Reset (SYSRESET) Instantiation
The SYSRESET macro provides device level reset functionality to your design. The POWER_ON_RESET_N output signal is asserted/de-asserted whenever the chip is powered up or the external pin DEVRST_N is asserted/de-asserted (Figure 3-6).
Instantiate the SYSRESET macro into your SmartDesign (typically the one where the MSS is instantiated). This macro can be found in the Libero Catalog under Macro Library.No configuration of this macro is necessary.

Figure 3-6 • SYSRESET Macro

Overall Connectivity
After you have instantiated and configured the MSS, FDDR, SERDESIF, OSC, SYSRESET, CoreConfigP and CoreResetP cores in your design, you need to connect them to form the Peripheral Initialization subsystem. To simplify the connectivity description in this document, it is broken into the APB3 compliant configuration data path connectivity associated with the CoreConfigP and the CoreResetP related connections.
Configuration Data Path Connectivity
Figure 3-7 shows how to connect the CoreConfigP to the MSS FIC_2 signals and the peripherals’ APB3 compliant configuration interfaces.
Table 3-1 • Configuration Data Path Port/BIF Connections

FROM
Port/Bus Interface
(BIF)/ Component| TO
Port/Bus Interface (BIF)/Component
---|---
APB S PRESET N/ CoreConfigP| APB S PRESET N/ SDIF<0/1/2/3>| APB S PRESET N/
FDDR| MDDR APB S PRESE T N/MSS
APB S PCLK/ CoreConfigP| APB S PCLK/SDIF<O/ 1/2/3>| APB S PCLK/FDDR| MDDR APB S POLK/ MSS
MDDR APBmslave/ CoreConfig| | | MDDR APB SLAVE (BIF)/MSS
SDIF<0/1/2/ 3> APBmslave/Config| APB SLAVE (BIF)/ SDIF<0/1/2/3>| |
FDDR APBmslave| | APB SLAVE (BIF)/ FDDR|
FIC 2 APBmmaster/ CoreConfigP| | | FIC 2 APB MASTER/ MSS

Figure 3-7 • FIC_2 APB3 Sub-System Connectivity

Clocks and Resets Connectivity
Figure 3-8 shows how to connect the CoreResetP to the external reset sources and the peripherals’ core reset signals. It also shows how to connect the CoreResetP to the peripherals’ clock synchronization status signals (PLL lock signals). In addition, it shows how the CoreConfigP and CoreResetP are connected.

Figure 3-8 • Core SF2Reset Sub-System Connectivity

Creating and Compiling the Firmware Application

When you export the firmware from LiberoSoC (Design Flow Window > Export Firmware > Export Firmware), Libero generates the following files in the