intel UG-20093 ModelSim FPGA Edition Simulation User Guide

intel UG-20093 ModelSim FPGA Edition Simulation

ModelSim* – Intel® FPGA Edition Simulation Quick-Start Intel® Quartus®

Prime Pro Edition

This document demonstrates how to simulate an Intel® Quartus® Prime Pro Edition design in the ModelSim* – Intel FPGA Edition simulator. Design simulation verifies your design before device programming. The Intel Quartus Prime software generates simulation files for supported EDA simulators during design compilation.
Figure 1. ModelSim – Intel FPGA Edition

Design simulation involves generating simulation files, compiling simulation models, running the simulation, and viewing the results. The following steps describe this flow:

1. Open the Example Design on page 4
2. Specify EDA Tool Settings on page 4
3. Generate a Simulator Setup Script Template on page 5
4. Modify the Simulator Setup Script on page 6
5. Compile and Simulate the Design on page 8
6. View Signal Waveforms on page 9
7. Add Signals to the Simulation on page 11
8. Rerun Simulation on page 12
9. Modify the Simulation Testbench on page 12

Open the Example Design

The PLL_RAM example design includes Intel FPGA IP cores to demonstrate the basic simulation flow. Download the example design files and open the project in the Intel Quartus Prime software.
Note: This Quick-Start requires a basic understanding of hardware description language syntax and the Intel Quartus Prime design flow, as the Intel Quartus Prime Pro Edition Foundation Online Training describes.

1. Download and unzip the Quartus_Pro_PLL_RAM.zip design example.
2. Launch the Intel Quartus Prime Pro Edition software version 19.4 or later.
3. To open the example design project, click File ➤ Open Project, select the pll_ram.qpf project file, and then click OK.

Figure 2. pll_ram Project in the Intel Quartus Prime Pro Edition

Specify EDA Tool Settings

Specify EDA tool settings to generate simulation files for supported simulators.

1. In the Intel Quartus Prime software, click Assignments ➤ Settings ➤ EDA Tool Settings.
2. Under Simulation, select ModelSim-Intel FPGA as the Tool name. Retain the default settings for Format for output netlist and Output directory.

Generate a Simulator Setup Script Template

Simulator setup scripts help you to simulate the IP cores in your design. Follow these steps to generate the vendor-specific simulator setup script template for the IP modules in the example design. You can then customize this template for your specific simulation goals.

1. To compile the design, click Processing ➤ Start Compilation. The Messages window indicates when compilation is complete.
2. Click Tools ➤ Generate Simulator Setup Script for IP. Retain the default Output directory and Use relative paths whenever possible setting for the setup script file. The setup script template generates in the directory that you specify.

Figure 3. Generate Simulator Setup Scripts IP Dialog Box

Modify the Simulator Setup Script

Modify the generated simulator setup script to enable specific commands that simulate the IP cores in the project.

1. In a text editor, open the /PLL_RAM/mentor/msim_setup.tcl file.
2. Create a new text file with the name mentor_example.do and save it in the /PLL_RAM/mentor/ directory.
3. In the msim_setup.tcl file, copy the section of code enclosed within the TOP-LEVEL TEMPLATE – BEGIN and TOP-LEVEL TEMPLATE – END comments, and then paste this code into the new mentor_example.do file.
4. In the mentor_example.do file, delete the single pound (#) characters preceding the following highlighted lines to enable compilation commands:

Figure 4. Uncomment Highlighted Simulation Commands in the Script

1. Replace the following lines in the mentor_example.do script:

Table 1. Specify Values in the mentor_example.do Script

set QSYS_SIMDIR