ALTERA 100G Interlaken Design Example User Guide

: June 4, 2024
: ALTERA

Table of Contents

INTRODUCTION
Directory Structure
Design Example Description
Document Revision History for 100G Interlaken Design Example User Guide
Read User Manual Online (PDF format)
Download This Manual (PDF format)

**ALTERA 100G Interlaken Design Example User Guide

**

INTRODUCTION

The Intel® Arria®10 variations of the 100G Interlaken IP core feature a simulating testbench and a hardware example design that supports compilation and hardware testing, to help you understand usage.

When you generate the example design, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to the Intel Arria 10 GX Transceiver Signal Integrity Development Kit. The testbench and demonstration example design are available for a wide range of parameters. However, they do not cover all possible parameterizations of the 100G Interlaken IP Core.

In addition, for most IP core variations, Intel provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1-1: Development Steps

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

Directory Structure

Figure 1-2: Directory Structure for the Generated Example Design

The hardware configuration, simulation, and test files are located in / example_design_a10.

Design Components

Figure 1-3: Example Design Block Diagram

Generating the Design

Figure 1-4: Procedure

Follow these steps to generate the Intel Arria 10 hardware example design and testbench:

In the IP Catalog (Tools > IP Catalog), select the Intel Arria 10 target device family. Note: The Quick Start hardware example design is only supported in Intel Arria 10 devices. The testbench is available for variations that target Intel Arria 10 devices or Stratix® V devices.
In the IP Catalog, locate and double-click 100G Interlaken. The New IP Variation window appears.
Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named .qsys.
You must select a specific Intel Arria 10 device in the Device field, or keep the default Intel Quartus® Prime software device selection.
Click OK. The parameter editor appears.
Figure 1-5: 100G Interlaken Parameter Editor
On the IP tab, specify the parameters for your IP core variation.
On the Example Design tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware example design.
Note: At least one of the Simulation and Synthesis check boxes from Example Design Files must be selected to allow generation of Example Design Files.
For Generated HDL Format, only Verilog is available.
For Target Development Kit select the Intel Arria 10 GX Transceiver Signal Integrity Development
Kit. If you select a development kit, then the target device (selected in step

for Example Design is changed to match the device on target board.

Click the Generate Example Design button.

Related Information
100G Interlaken IP Core Parameter Settings
Provides information about the 100G Interlaken IP core customization by specifying parameters.

Simulating the Design

Figure 1-6: Procedure

Follow these steps to simulate the testbench:

Change to the testbench simulation directory /example_ design_a10/testbench.
Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Your script should check that the SOP and EOP counts match after simulation is complete. Refer to the table Steps to Run Simulation.
Analyze the results.

Table 1-1: Steps to Run Simulation

Simulator Instructions

ModelSim SE or Questa or Questa- Intel FPGA Edition| In the command line, type vsim -do vlog_pro.do
If you prefer to simulate without bringing up the GUI, type vsim -c -do vlog_pro.do
VCS*| In the command line, type sh vcstest.sh

A successful simulation ends with the following message:

Test PASSED

Compiling and Testing the Design

To compile and run a demonstration test on the hardware example design, follow these steps:

Ensure hardware example design generation is complete.
Open the Intel Quartus Prime project /example_design_a10/quartus/ example_design.qpf, where is the directory location you specified when you generated the testbench and hardware example design.
On the Processing menu, click Start Compilation.
After successful compilation, a .sof file will be generated in your specified directory. Follow these steps to program the hardware example design on the Intel Arria 10:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Intel Arria 10 GX Transceiver Signal Integrity Development Kit to which your
  Intel Quartus Prime session can connect.
- Ensure that Mode is set to JTAG.
- Select the Arria 10 device and click Add Device. The Programmer displays a block diagram of the
  connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.
After the hardware example design is configured on the Intel Arria 10 device, in the Intel Quartus
Prime software, on the Tools menu, click System Debugging Tools > System Console.
In the Tcl Console pane, type sysconsole_testbench.tcl.
Type run_example_design.

Design Example Description

The example design demonstrate the functionalities of the 100G Interlaken IP core. You can generate the design from the Example Design tab of the 100G Interlaken graphical user interface (GUI) in the IP parameter editor.

Features

Internal TX to RX serial loopback mode.
Automatically generates fixed size packets.
Basic packet checking capabilities.
You can use system console to reset the design for re-testing purpose.

Hardware and Software Requirements

Altera uses the following hardware and software to test the example design:

Quartus Prime software
System Console
VCS, ModelSim SE, Questa, or Questa-Intel FPGA Edition simulator
Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing

Functional Description

The hardware example design connects system and PLL reference clocks and required design components. After you program the device on the Arria 10 GX transceiver signal integrity development board, the example design configures the IP core in internal loopback mode and generates packets on the IP core TX user data transfer interface. The IP core sends these packets on the internal loopback path through the transceiver. After the IP core receiver receives the packets on the loopback path, it processes the Interlaken packets and transmits them on the RX user data transfer interface. The example design checks that the packets it receives on the IP core RX user data transfer interface are consistent with the packets sent in.

Figure 2-1: Arria 10 100G Interlaken IP Core Example Design Block Diagram

The hardware example design includes external PLLs. You can examine the clear text files to view sample code that implements one possible method to connect external PLLs to the 100G Interlaken IP core. The hardware example design packs six Interlaken lanes in a transceiver block, and connects all of the channels in the same transceiver block to a single ATX PLL. The IP core connects ATX PLL to the 100G Interlaken IP core tx_pll_locked and tx_pll_powerdown ports. This simple connection model is only one of many options available to you for configuring and connecting the external PLLs in your 100G Interlaken design.

Arria 10 GX Transceiver Signal Integrity Development Kit product webpage
100G Interlaken MegaCore Function User Guide

Example Design Behavior

Immediately following configuration on the Arria 10 device, when you type run_example_design in system console, the 100G Interlaken IP core hardware example design performs the following actions:

Resets the 100G Interlaken IP core.
Configures the 100G Interlaken IP core in internal loopback mode.
Sends a sequence of 100 256-byte Interlaken packets with predefined data in the payload to the TX user data transfer interface of the IP core.
Note: If the IP core is in dual segment mode, the hardware example design sends 65-byte bursts on the TX user data transfer interface. If the IP core is in single segment, Interleaved mode, the
hardware example design sends 128-byte bursts.
Checks the received packets and reports the status.
The packet checker included in the hardware example design provides the following basic packet checking capabilities:
- Checks that the transmitted packet sequence is not violated
- Checks that the received data matches expected values

Interface Signals

Table 2-1: Arria 10 100G Interlaken IP Core Hardware Example Design Signals

Port Name	Direction	Width (Bits)	Description
pll_ref_clk	Input	1	Transceiver reference clock. Drives the RX CDR PLL.
rx_pin	Input	Number of lanes	Receiver SERDES data pin.
tx_pin	Output	Number of lanes	Transmit SERDES data pin.
sys_pll_reset_n	Input	1	System reset.

Register Map

Table 2-2: Example Design Register Map

Offset Name	Access	Description
8’h00	Reserved
8’h01	Reserved
Offset Name	Access	Description
---	---	---
8’h02	System PLL reset	RO

and enable value:

Bit [0] – sys_pll_rst_req
Bit [1] – sys_pll_rst_en

Bit [3] – TX underflow signal
Bit [2] – TX overflow signal
Bit [1] – RX overflow signal

Loss of lane alignment
Illegal control word
Illegal framing pattern
Missing SOP or EOP indicator

Note:

Example design register address starts with 0x20 while the 100G Interlaken core register
address starts with 0x10.
Access code: RO—Read Only, and RW—Read/Write.
System console reads the example design registers and reports the test status on the screen.

Document Revision History for 100G Interlaken Design Example User Guide

Date Changes

2021.10.04| Updated simulator information in section: Simulating the Design and Hardware and Software Requirements.

2018.03.22

| Made following changes to Simulating the Design section:

Corrected simulation directory location.
Updated command to simulate the testbench in NCSim and VCS simulators.
Updated simulation ends display message.

2016.10.31

|

Changed the title to 100G Interlaken Design Example User Guide.
Corrected the Figure: Arria 10 100G Interlaken IP Core Example Design Block Diagram.
Updated the Figure: Directory Structure for the Generated Example Design.

2016.05.02| Initial release

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of other.