ALTERA Arria 10 Hybrid Memory Cube Controller Design Example User Guide

Design Example Components

The HMC Controller hardware design example includes the following components:

• HMC Controller IP core with CDR reference clock set to 125 MHz and with default RX mapping and TX mapping settings.
  Note : The design example requires these settings to operate properly on the Arria 10 GX FPGA Development Kit with the HMC daughter card.

• Client logic that coordinates the programming of the IP core, and packet generation and checking.

• JTAG controller that communicates with the Altera System Console. You communicate with the client logic through the System Console.

Lists the key files that implement the example testbench.

Testbench Scripts

Note: Use the provided Makefile to generate these scripts.

/sim/run_vsim.do| The ModelSim script to run the testbench.
/sim/run_vcs.sh| The Synopsys VCS script to run the testbench.
/sim/run_ncsim.sh| The Cadence NCSim script to run the testbench.

**Generating the Design Example

**

Figure 1-5: Example Design Tab in Hybrid Memory Cube Controller Parameter Editor

Follow these steps to generate the Arria 10 hardware design example and testbench:

1. In the IP Catalog (Tools > IP Catalog), select the Arria 10 target device family.

2. In the IP Catalog, locate and select Hybrid Memory Cube Controller. The New IP Variation window appears.

3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named .qsys.

4. You must select a specific Arria 10 device in the Device field, or keep the default device the Quartus Prime software selects.

5. Click OK. The IP parameter editor appears.

6. On the IP tab, specify the parameters for your IP core variation.

7. On the Example Design tab, choose the following settings for the design example:

8. For Select Design, select the HMCC Daughter Board option.

9. For Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.

10. For Generated HDL Format, only Verilog is available.

11. For Target Development Kit select the Arria 10 GX FPGA Development Kit (Production Silicon).
    Note : When you choose this kit, the hardware design example overwrites your previous device selection with the device on the target board. When you generate the design example, the Intel Quartus Prime software creates Intel
    Quartus Prime project, setting, and pin assignments for the board you selected. If you do not want the software to target a specific board, select None.

12. Click the Generate Example Design button

Understanding the Testbench

Altera provides an design example with the HMC Controller IP core. The design example is available both for simulation of your IP core and for compilation. The design example in simulation functions as the HMC Controller IP core testbench.
If you click Generate Example Design in the HMC Controller parameter editor, the Quartus Prime software generates a demonstration testbench. The parameter editor prompts you for the desired location of the testbench.
To simulate the testbench, you must provide your own HMC bus functional model (BFM). Altera tests the design example testbench with the Micron Hybrid Memory Cube BFM. The testbench does not include an I2C master module, because the Micron HMC BFM does not support and does not require configuration by an I2C module.
In simulation, the testbench controls a TX PLL and the data path interfaces to perform the following sequence of actions:

1. Configures the HMC BFM with the HMC Controller IP core data rate and channel width, in Response Open Loop Mode.
2. Establishes the link between the BFM and the IP core.
3. Directs each of the IP core’s four ports to write four packets of data to the BFM.
4. Directs the IP core to read back the data from the BFM.
5. Checks that the read data matches the write data.
6. If the data matches, displays TEST_PASSED.

Simulating the Design Example Testbench
Figure 1-6: Procedure

Follow these steps to simulate the testbench:

1. At the command line, change to the /sim directory.
2. Type make scripts.
3. Type one of the following commands, depending on your simulator:
4. To view simulation results:
5. When you run the testbench in any of the three supported simulators, the script executes the testbench sequence and logs the simulator activity in /example_ design/sim/.log. is “vsim”, “ncsim”, or “vcs”.
6. When you run the testbench in any of the three supported simulators, the script generates a waveform file. You can run the command make _gui to load the waveform in the simulator-specific waveform viewer.
   To view the waveform file in your simulator, type one of the following commands: Simulator License

Mentor Graphics ModelSim

| Command Line

make vsim_gui

| Waveform File

< design example directory>/example_design/sim/ mentor/hmcc_wf.wlf

---|---|---
Synopsys Discovery Visual Environment| make vcsgui| < design example directory>_/example_design/sim/ hmcc_wf.vpd
Cadence SimVision Waveform| make ncsimgui| < design example directory>_/example_design/sim/ cadence/hmcc_wf.shm
5. Analyze the results. The successful testbench sends and receives ten packets per port, and displays Test_PASSED”

Setting Up the Board

Set up the board to run the hardware design example.
Note : Ensure that power is turned off before you change any settings.

1. Set the DIP switches on the daughter card as follows:
2. Set DIP switch SW1 to indicate cube ID 0:
   Switch| Function| Setting
   ---|---|---
   1| CUB[0]| Open
   2| CUB[1]| Open
   3| CUB[2]| Open
   4| —| Don’t Care

Set DIP switch SW2 to specify clock settings:

• Connect the HMC daughter card to the Arria 10 FPGA Development Kit using the daughter card’s J8 and J10 connectors.
• Set the jumpers on the Arria 10 GX FPGA Development Kit:
• Add shunts to the J8 jumper to select 1.5 V as the VCCIO setting for FMC connector B.
• Add shunts to the J11 jumper to select 1.8 V as the VCCIO setting for FMC connector A.

Compiling and Testing the Design Example in Hardware

To compile and run a demonstration test on the hardware design example, follow these steps

1. Ensure hardware design example generation is complete.

2. In the Quartus Prime software, open the Quartus Prime project /example_design/par/hmcc_example.qpf.

3. In the Compilation Dashboard, click Compile Design (Intel Quartus Prime Pro Edition) or choose Processing > Start Compilation (Intel Quartus Prime Standard Edition).

4. After you generate a .sof, follow these steps to program the hardware design example on the Arria 10 device:

5. Choose Tools > Programmer.

6. In the Programmer, click Hardware Setup.

7. Select a programming device.

8. Select and add the Arria 10 GX FPGA Development Kit to which your Quartus Prime session can connect.

9. Ensure that Mode is set to JTAG.

10. Click Auto Detect and choose any device.

11. Double-click the Arria 10 device.

12. Open the .sof in /exampledesign/par/output files,
    Note : The Quartus Prime software changes the device to the one in the .sof.

13. In the row with your .sof, check the box in the Program/Configure column.

14. Click Start.

15. After the software configures the device with the hardware design example, observe the board LEDs:

16. A blinking red LED signifies the design is running.

17. Two green LEDs near the red blinking LED signifies that the HMC link is initialized and the test passed.

18. One red LED near the red blinking LED signifies that the test failed.

19. Optional. Use the System Console testbench to observe additional test output.
    Note: Use the System Console to monitor status signals in the design example when the board is connected to your computer via the JTAG interface. The System Console shows the board’s LED status for remote monitoring, the initialization status for each step, and the status of each port’s request generator and response checker. The System Console also provides an interface to start or re-start the test.

20. Choose Tools > System Debugging Tools > System Console.

21. In the System Console, choose File > Execute Script.

22. Open the file /exampledesign/par/sysconsole testbench.tcl.

23. The software loads graphical test output. Choose Re-start to run the test again.

Compiling and Testing the Design Example in Hardware

Hybrid Memory Cube Controller Design

Design Example Description

The design example demonstrates the functionality of the Hybrid Memory Cube Controller IP core. You can generate the design from the Example Design tab of the Hybrid Memory Cube Controller graphical user interface (GUI) in the IP parameter editor.

Features

• I2C master and I2C initialization state machine for HMC daughter card and HMC configuration
• ATX PLL and transceiver recalibration state machine
• Request generator
• Request monitor
• System Console interface

Hardware and Software Requirements
Altera uses the following hardware and software to test the design example:

• Intel Quartus Prime software
• System Console
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL only), or VCS simulator
• Arria 10 GX FPGA Development Kit
• HMC daughter card

Functional Description

Altera provides a compilation-ready design example with the HMC Controller IP core. This design example targets the Arria 10 GX FPGA Development Kit with an HMC daughter card connected through the FMC connectors.
You can use the design as an example for correct connection of your IP core to your design, or as a starter design you can customize for your own design requirements. The design example includes an I2C master module, a PLL/CDR recalibration module, one external transceiver PLL IP core, and logic to generate and check transactions. The design example assumes a Micron HMC 15G- SR HMC device, which is a fourlink device, on the daughter card. The design example includes one instance of the IP core and connects to a single link on the HMC device. Figure 2-1: HMC Controller Design Example Block Diagram

After you configure the Arria 10 FPGA with the design example, the I2C controller configures the on-board clock generators and the HMC device. When calibration completes, the design example calibrates the ATX PLL. During operation, the request generator generates read and write commands that the HMC Controller IP core then processes. The request monitor captures the responses from the IP core and checks them for correctness.

Interface Signals
Table 2-1: HMC Controller IP Core Design Example Signals

Signal Name

clk_50

| Direction

Input

| Width (Bits)

1

| Description

50 MHz input clock.

---|---|---|---
hssi_refclk| Input| 1| CDR reference clock for HMC and HMCC IP core.
Signal Name

hmc_lxrx

| Direction

Input

| Width (Bits)

Channel Count (16

or 8)

| Description

FPGA transceiver receive pins.

---|---|---|---
hmc_lxtx| Output| Channel Count (16

or 8)

| FPGA transceiver transmit pins.
hmc_ctrl_lxrxps| Input| 1| FPGA transceiver power save control.
hmc_ctrl_lxtxps| Output| 1| HMC transceiver power save control.
hmc_ctrl_ferr_n| Input| 1| HMC FERR_N output.
hmc_ctrl_p_rst_n| Output| 1| HMC P_RST_N input.
hmc_ctrl_scl| Bi-Directional| 1| HMC I2C configuration clock.
hmc_ctrl_sda| Bi-Directional| 1| HMC I2C configuration data.
fmc0_scl| Output| 1| Unused. Driven low to protect the FPGA I/O pins from the 3.3 V pullup on the daughter card.
fmc0_sda| Output| 1| Unused. Driven low to protect the FPGA I/O pins from the 3.3 V pullup on the daughter card.
push_button| Input| 1| Push button input used for reset.
heart_beat_n| Output| 1| Heartbeat LED output.
link_init_complete_n| Output| 1| Link initialization complete LED output.
test_passed_n| Output| 1| Test passed LED output.
test_failed_n| Output| 1| Test failed LED output.

Design Example Register Map
Table 2-2: HMC Controller IP Core Design Example Register Map

Writing to these registers resets the design.

Bits

1:0

| Field Name

Port Count

| Type

RO

| Value on Reset

Varies

| Description

Number of ports for the IP core instance.

---|---|---|---|---
7:2| Reserved| RO| 0x00|

Table 2-4: BOARD_LEDs Register
This register reflects the status of the board’s LEDs

Bits

0

| Field Name

Test Failed

| Type

RO

| Value on Reset

0x00

| Description

Test failed.

---|---|---|---|---
1| Test Passed| RO| 0x00| Test passed.
2| HMCC Link Initialization Complete| RO| 0x00| HMC link initialization complete and ready for traffic.
3| Heartbeat| RO| 0x00| Toggles when the design is running.
7:4| Reserved| RO| 0x00|

Table 2-5: TEST_INITIALIZATION_STATUS Register

Bits

0

| Field Name

I2C Clock Generator Set

| Type

RO

| Value on Reset

0x00

| Description

On- board    clock   generators configured.

---|---|---|---|---
1| ATX PLL and Transceiver Recalibration Complete| RO| 0x00| ATX PLL and transceivers re- calibrated to the input clock.
2| I2C HMC

Configuration Complete

| RO| 0x00| HMC device configuration over I2C complete.
3| HMC Link Initialization Complete| RO| 0x00| HMC link initialization complete and ready for traffic.
7:4| Reserved| RO| 0x00|

Table 2-6: PORT_STATUS Register

Bits

0

| Field Name

Port 0 Requests OK

| Type

RO

| Value on Reset

0x00

| Description

Port 0 request generation complete.

---|---|---|---|---
1| Port 0 Responses OK| RO| 0x00| Port 0 response checking passed.
2| Port 1 Requests OK| RO| 0x00| Port 1 request generation complete.
3| Port 1 Responses OK| RO| 0x00| Port 1 response checking passed.
Bits

4

| Field Name

Port 2 Requests OK

| Type

RO

| Value on Reset

0x00

| Description

Port 2 request generation complete.

---|---|---|---|---
5| Port 2 Responses OK| RO| 0x00| Port 2 response checking passed.
6| Port 3 Requests OK| RO| 0x00| Port 3 request generation complete.
7| Port 4 Responses OK| RO| 0x00| Port 3 response checking passed.

Additional Information

HMC Controller Design Example User Guide Revision History
Table A-1: Document Revision History
Summarizes the new features and changes in the design example user guide for the HMC Controller IP core.

How to Contact Intel
Table A-2: How to Contact Intel
To locate the most up-to-date information about Intel products, refer to this table. You can also contact your local Intel sales office or sales representative.

www.altera.com/support

Technical training

| Website| www.altera.com/training
Email| FPGATraining@intel.com
Product literature| Website| www.altera.com/literature
Nontechnical support: general| Email| nacomp@altera.com
Contact

Nontechnical support: software licensing

| Contact Method

Email

| Address

authorization@altera.com

---|---|---

Related Information

• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• authorization@altera.com

Typographic Conventions

Table A-3: Typographic Conventions
Lists the typographic conventions this document uses

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Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Other names and brands may be claimed as the property of others
101 Innovation Drive, San Jose, CA 95134

Last updated for Quartus Prime Design Suite: 16.0
UG-20027
2016.05.02
101 Innovation Drive
San Jose, CA 95134
www.altera.com

References

• FPGA Documentation Index
• Intel Field Programmable Gate Array (FPGA) Support Resources | Intel
• Intel ISO 9001:2015 Registrations
• Intel Field Programmable Gate Arrays (FPGA) Technical Training | Intel
• PSG Documentation
• 1. Hybrid Memory Cube Controller Design Example Quick Start Guide

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