DIODES PAM2319 WDFN EV Board User Guide

PAM2319
EVB User Guide

PAM2319 WDFN EV Board

PAM2319 WDFN EV Board User Guide
AE Department

Revision Information

PAM2319 General Description

The PAM2319 is a dual step-down current-mode, DC-DC converter. At heavy load, the constant frequency PWM control performs excellent stability and transient response. To ensure the longest battery life in portable applications, the PAM2319 provides a power – saving Pulse-Skipping Modulation (PSM) mode to reduce quiescent current under light load operation.
The PAM2319 supports a range of input voltages from 2.5V to 5.5V, allowing the use of a single Li+/Lipolymer cell, multiple Alkaline/NiMH cell, USB, and other standard power sources. The dual output voltages are adjustable from 0.6V to 3.3V .Both channels employ internal power switch and synchronous rectifier for to minimize external part count and realize high efficiency. During shutdown, the input is disconnected from the output and the shutdown current is less than 0.1 A. Other key features include under-voltage lockout, soft-start, short circuit protection and thermal shutdown.

Key Features

• Supply Voltage:2.5V to 5.5V

• Output Voltage: V1 ADJ/1000mA (ADJ: 0.6V to 3.3V)
  VO2 ADJ/2000mA (ADJ: 0.6V to 3.3V)

• Low Quiescent Current: 40uA Per-channel

• High Efficiency:

• 3MHz Switching Frequency

• Internal Synchronous Rectifier

• Soft Start

• Under-Voltage Lockout

• Short Circuit Protection

• Thermal Shutdown

• Small WDFN3X3-12L Pb-Free/Halogen Free Package

• RoHS/REACH Compliant

EV Board Schematic

EVB PAM2310 EB09AA Description

PAM2319 EB18AA is an evaluation board for the PAM2319 WDFN, a DC/DC converter. The board is targeted to be used in providing a simple and convenient evaluation environment for the PAM2319.
Requires parts, power supply connectors etc. on the board, which makes it easy to be evaluated.

EV Board View

External Compnents Selection

Input & output Capacitors (C1, C4, C5; C2, C7)

1. For lower output ripple, low ESR is required.
2. Low leakage current needed, X5R/X7R ceramic recommend, multiple capacitor parallel connection.

Feed forward capacitor (C3，C6)

1. Lower the output ripple
2. Low leakage current needed, 100pF, COH/CH ceramic recommend

Output Voltage programmer resistors (R1, R2; R3,R4)

1. For programmer output voltage
2. For accurate output voltage, 1% tolerance is required.

Inductor (L1;L2)

1. Low DCR for good efficiency
2. Inductance saturate current must higher than the output current

Evaluation Board BOM List:

Item| Value| Type| Rating| Description| Vender and Part No.
---|---|---|---|---|---
C4| 10µF| X5R/X7R, Ceramic/0805| 10V| Input coupling CAP| TAIYO YUDEN
EMK212ABJ106KD-T
C1, C5| 1µF| X5R/X7R, Ceramic/0603| 25V| Input coupling CAP| TAIYO YUDEN
TMK107 BJ105KA-T
C2, C7| 10µF| X5R/X7R, Ceramic/0805| 10V| Output CAP| TAIYO YUDEN
EMK212ABJ106KD-T
C3, C6| 100pF| COH/CH, Ceramic/0402| 50V| Feed forward CAP| TAIYO YUDEN
UMK105CH101JV-F
L1| 1µH| | >1.5A| Inductor| 744042001 Wurth
L2| 0.47µH| | >3A| Inductor| 74404300047 Wurth
R1| 300K| 0603| 1%| Voltage set RES|
R2| 150K| 0603| 1%|
R3| 150K| 0603| 1%|
R4| 150K| 0603| 1%|
IC1| | PAM2319| WDFN3X3- 12L| |
PCB| | PAM2319 EB18AA| | |

PCB Layout Guideline

The following guidelines should be used to help ensure a proper layout:

1. The input capacitor should be close to IC as close as possible.
2. Minimize the switching loop area to avoid excessive switching noise.
3. Two parts GND should be separately layout to avoid disturbing by each other.
4. Must put a small decoupling capacitor between Vin2 Pin and AGND2 Pin.
5. Vo2 output capacitor should be close to output connector to minimize PCB trace resistance affect on ripple voltage. Recommend use two output capacitor, one close to inductor and IC, another close to output connector.
6. PGND1 Pin should not directly connect to the thermal pad (PGND), it should connect to input capacitor GND then to other GND.
7. AGND should connect to PGND at input capacitor GND.
8. For the good thermal dissipation, PAM2316 has a heat dissipate pad in the bottom side, it should be soldered to PCB surface. For the copper area can’t be large in the component side, so we can use multiple vias connect to other side of the PCB.
9. Avoid using vias in the high-current paths. If vias are unavoidable, use multiple vias in parallel to reduce resistance and inductance.

PCB Layout Example

This application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice.
No liability isassumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

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