HOPERF AN286 CMT216xA Register Instruction Manual
- June 16, 2024
- HOPERF
Table of Contents
HOPERF AN286 CMT216xA Register
Product Information
Specifications:
- Product Models: CMT2160A, CMT2162A, CMT2163A, CMT2165A, CMT2168A
- Single-end PA
- Differential PA
- 12-Bit ADC: 4-ch (CMT2160A), 8-ch (CMT2162A), 9-ch (CMT2163A), 12-ch (CMT2165A, CMT2168A)
- Operational Low-frequency Amplifier
- Wakeup External 32.768 kHz
- Packaging: SOP14, SSOP20, TSSOP28, TSSOP28, QFN32
Product Usage Instructions
1. Register Introduction
The register sets of the CMT216xA series SoC chip are located in 2 areas, Block 0 and Block 1, which have different functions and operation methods.
Block 0:
The access address range of this area is 0x00 ~ 0x7F, partially inaccessible to users. The inaccessible part is used to store on-chip system key parameters. Users are prohibited from accessing and modifying this part, which is indicated in gray in Section 2.1 Block0 Area Register Detailed List in this document. For the accessible part of Block 0, users can access it through the API functions rather than access through direct addressing.
2. Register Details
2.1 Block 0 Area Register Details
This section provides detailed information about the registers in Block 0 area. It includes the register addresses, functions, and descriptions. Please note that some registers in this area are inaccessible to users.
2.2 Block 1 Area Register List
This section provides a list of registers in Block 1 area. It includes the sub-areas and their corresponding registers. The registers in Bank 0 and Bank 1 are listed separately.
2.2.1 Bank 0 Sub-area Register List
This subsection lists the registers in Bank 0 sub-area of Block 1. It includes the register addresses, functions, and descriptions.
2.2.2 Bank 1 Sub-area Register List
This subsection lists the registers in Bank 1 sub-area of Block
1. It includes the register addresses, functions, and descriptions.
3. Register Details
This section provides additional register details that were not covered in the previous sections. It includes the register addresses, functions, and descriptions.
4. Revise History
This section provides the revision history of the user manual or instructions document.
5. Contacts
This section provides contact information for any inquiries or support related to the product.
FAQs
- Q: Where can I find the performance and parameter details of each chip model?
- A: The performance and parameter details, as well as the package size, silk screen, and ordering information of each chip model, are not covered in this document. Please refer to the datasheet document of each chip model for details.
- Q: Where can I find specific function details of the CMT216xA series?
- A: For specific function details of the CMT216xA series, please refer to the CMT216xA User Guide.
CMT216xA Register Introduction
AN286
Overview
This document discusses CMT216xA register details for users to query and view
CMT216xA register details. The product models covered in this document are
shown in the table below.
Product Model CMT2160A CMT2162A CMT2163A CMT2165A CMT2168A
Single-end PA
Table 1. Product Models Covered in This Document
Differential PA
12-Bit ADC 4-ch 8-ch 9-ch 12-ch 12-ch
Operational Low-frequency
Amplifier
Wakeup
External 32.768 kHz
Packaging
SOP14 SSOP20 TSSOP28 TSSOP28 QFN32
Notes: The performance and parameter details as well as the package size, silk screen and ordering information of each chip model are NOT covered in this document, please refer to the datasheet document of each chip model for details. For specific function details of the CMT216xA series, please refer to CMT216xA User Guide.
Copyright © By HOPERF
Rev 0.6 | 2/102
AN286
Register Introduction
The register sets of the CMT216xA series SoC chip are located in 2 areas, Block 0 and Block 1, which have different functions and operation methods.
Block 0: the access address range of this area is 0x00 ~ 0x7F, partially inaccessible to users. The inaccessible part is used to store on-chip system key parameters. Users are prohibited from accessing and modifying this part, which is Indicated in gray in Section 2.1 Block0 Area Register Detailed List in this document. For the accessible part of Block 0, users can access it through the API functions rather than access through direct addressing.
Function Name
Description
sys_write_hv_reg
Write by address
sys_read_hv_reg
Read by address
sys_set_hv_reg
Set by bit address (set bit value)
Notes:
1. These 3 functions provide direct operations on Block 0 area (directly access via API functions). See AN282 CMT216xA API
Library Usage Guide for details.
2. The associated API functions of the CMT216xA peripheral modules will access the corresponding inperipheral registers in
Block 0 as well, which is invisible to users.
Block 1: this area contains two sub-areas, Bank 0 and Bank 1 with an access address range of 0x80 ~ 0xFF, which is partially accessible to users as well. The inaccessible part is used to store on-chip system key parameters. Users are prohibited from accessing and modifying this part, which is Indicated in gray in Section 2.2 Block 1 Area Register Detailed List in this document. For the accessible part of Block 1, users can access it th rough direct addressing, however, users need to ensure that the correct switching between Bank0 and Bank1 before accessing, otherwise it will result in incorrect access to the sub-areas.
Notes: 1. In the Block 1 area, Bank 0 and Bank 1 switching is performed by
calling the API function sys_set_sfr_bank. 2. When operating Block1 directly
in the software, it is highly recommended to switch the target bank of the
corresponding
register, since the CMT216xA API functions will perform corresponding bank
switch as required during function call, however there’s no bank switching
back operation to save function execution time. Fortunately, users rarely
access Block 1 registers directly, in fact most of the registers are accessed
through API function calling.
3. The registers related to the 8051 core in Bank0 of Block1 (marked in
orange in Section 2.2.1 Bank0 Sub-Registrar Register
Detailed List) can be accessed directly at any time without concerning bank
switching.
Rev 0.6 | 3/102
www.hoperf.com
The CMT216xA register area arrangement is shown in the below figure.
AN286
High-Voltage Domain
BLOCK 0
Rang: 0x00 – 0x7F
Main Domain
BLOCK 1
Rang: 0x80 – 0xFF
Bank 0
sys_set_sfr_bank(0)
Access example: unsigned char tmp; tmp = sys_read_hv_reg(0x12); tmp &= 0xF7; Sys_write_hv_reg(0x12);
Access example: sys_set_sfr_bank(0); CLK_SYS_DIV = 0x05; sys_set_sfr_bank(1); TBCH = 0x04;
//CLK_SYS_DIV @ Bank0_0x8F //TBCH @ Bank1_0xD9
Bank 1
sys_set_sfr_bank(1)
Figure1. CMT216xA Register Area Arrangement
Notes: 1. The Block 0 SFR registers in the high-voltage domian do not change
with the operating state of the CMT216xA (operating,
sleep, etc.). So it just needs to be configured once upon first power-up with
no need for repeated configurations for saving software initialization time.
2. The Block 1 SFR registers in the main domian will be lost when CMT216xA
entering Shut Down (short for SDN, by calling the API function sys_shutdown),
namely the register contents will be restored to default values. They need to
be configured again upon next wake-up (code loading). Therefore, every time
the program re-runs, they need to be configured again, rather than just be
configure once upon the first power-up. 3. For more details on the terms of
ShutDown, first power-up, etc, please see CMT216xA Datasheet or related AN
documents.
Rev 0.6 | 4/102
www.hoperf.com
AN286
Register Details
2.1 Block 0 Area Register Details
Addr
TYP
0x00
RW
0x01
RW
0x02
RW
0x03
RW
0x04
RW
0x05
RW
0x06
RW
0x07
RW
0x08
RW
0x09
RW
0x0A
RW
0x0B
RW
0x0C
RW
0x0D
RW
0x0E
RW
0x0F
RW
0x10
RW
0x11
RW
0x12
RW
0x13
RW
0x14
RW
Name CUS_AFE1 CUS_AFE2 CUS_AFE3 CUS_AFE4 CUS_AFE5 CUS_AFE6 CUS_AFE7 CUS_AFE8 CUS_AFE9 CUS_AFE10 CUS_AFE11 CUS_AFE12 CUS_AFE13 CUS_AFE14 CUS_AFE15 CUS_AFE16 CUS_AFE17 CUS_AFE18 CUS_LFRX3 CUS_LFRX4 CUS_LFRX5
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
AFE_IA2_GX[1:0]
AFE_IA1_GX[2:0]
AFE_SEN_CHX[2:0]
HFOSC_CLK_EN[1:0]
LFOSC_LFXO_SEL
PD_LFXO
PD_LFOSC
LPOA0_VCM_DIS
LPOA1_VCM_DIS
AFE_IA_VCMX
AFE_OA_VCMX[1:0]
AFE_OA_OUTX[1:0]
AFE_IA1_CX
AFE_OA0_OX
AFE_OA0_NX[1:0]
AFE_OA0_PX[2:0]
AFE_OA0_NA_GX[1:0]
SAR_DIRECT_DIS
AFE_OA1_OX[1:0]
AFE_OA1_NX[1:0]
AFE_OA1_PX[2:0]
LDO_PIR_RAILB
AFE_OA2_OX[1:0]
AFE_OA2_NX[1:0]
AFE_OA2_PX[2:0]
LDO_PIR_VO_SEL[1:0]
SAR_INX[3:0]
SAR_REFX[1:0]
PD_AFE_OACMI
PIR_ST
PD_AFE_OSADJ
PD_AFE_IACMO
PD_SAR
PD_AFE_OA2
PD_AFE_OA1
PD_AFE_OA0
LDO_SAR_VO_SEL[1:0]
LDO_SAR_RAILB
PD_BG
SAR_LBD_DIS
SAR_REF_DIS
PD_LDO_SAR
PD_AFE_VTR
SAR_MBC0
SAR_MBC1
SAR_STM[1:0]
PD_LDO_PIR
PD_PIR_VTR
PD_LPOA1
PD_LPOA0
HDRV_SEL[4:0]
DRV_ENH
DRV_MAN_EN
PD_DRV
NDRV_SEL[3:0]
NDRV_EN
HDRV_EN
LDO_PIR_OE
PD_P25
PD_P50
LFRX_AGC_IN[1:0]
LFRX_AGC_VHREF[3:0]
PD_PULLUP2
LFRX_AGC_CNT[1:0]
LFRX_AGC_VLREF[3:0]
LFRX_CADET_WIN[1:0]
LFRX_CADET_OK_CNT[1:0]
LFRX_PEAKDET_CLK[1:0]
LFRX_DATA_CLK[1:0]
Rev 0.6 | 5/102
AN286
Addr
TYP
0x15
RW
0x16
RW
0x17
RW
0x18
RW
0x19
RW
0x1A
RW
0x1B
RW
0x1E
RW
0x1F
RW
0x20
RW
0x21
RW
0x22
RW
0x23
R
0x24
RW
0x25
RW
0x26
RW
0x27
RW
0x28
RW
0x29
RW
0x2A
RW
0x2B
RW
0x2C
RW
0x2D
RW
0x2E
RW
Name CUS_LFRX6 CUS_LFRX7 CUS_LFRX8
CUS_LFRX9
CUS_LFRX10
CUS_LFRX11 CUS_LFRX12
CUS_SNOOZE1 CUS_SNOOZE2 CUS_SNOOZE3 CUS_SNOOZE4 CUS_SNOOZE5 CUS_SNOOZE6
CUS_PADCTL1 CUS_PADCTL2 CUS_PADCTL3 CUS_PADCTL4 CUS_PADCTL5 CUS_PADCTL6
CUS_PADCTL7 CUS_PADCTL8 CUS_PADCTL9 CUS_PADCTL10 CUS_PADCTL11
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LFRX_DATA_R0[1:0]
LFRX_DATA_R1[1:0]
LFRX_PEAKDET_C[1:0]
LFRX_DATA_C1[3:0]
LFRX_DATA_C0[3:0]
LFRX_DATA_C3[3:0]
LFRX_DATA_C2[3:0]
LFRX_CMPNOISE MASK
LFRX_CMP_SW
LFRX_RSSIAMP_IBIAS[2:0]
LFRX_PGA_IBIAS[2:0]
LFRX_CMP_REF[3:0]
LFRX_DEMOD_TH_H OLD
LFRX_RSSIREC_IBIAS[2:0]
LFRX_SNRDET_INVALID_WIN[1:0]
LFRX_SNRDET_VALID_WIN[1:0]
LFRX_SNRDET_SNR[3:0]
LFRX_MEAS_SOURCE
LFRX_OSC_VREF[1:0]
LFRX_CH_Z
LFRX_CH_Y
LFRX_CH_X
LFRX_STARTUP_MANUAL[1:0]
0x1C ~ 0x1D, inaccessible to users
SNOOZE_TIMER_M_SLEEP[7:0]
SNOOZE_UTH[9:8]
SNOOZE_DTH[9:8]
SNOOZE_TIMER_R_SLEEP[3:0]
SNOOZE_UTH[7:0]
SNOOZE_DTH[7:0]
SAR_CKX[1:0]
DWTH_WK_EN
UPTH_WK_EN
WOUT_WK_EN
WIN_WK_EN
GPIO_HOLD
DWTH_WK_INT
UPTH_WK_INT
WOUT_WK_INT
WIN_WK_INT
GPIO3_MODE[1:0]
GPIO2_MODE[1:0]
GPIO1_MODE[1:0]
GPIO0_MODE[1:0]
GPIO7_MODE[1:0]
GPIO6_MODE[1:0]
GPIO5_MODE[1:0]
GPIO4_MODE[1:0]
GPIO11_MODE[1:0]
GPIO10_MODE[1:0]
GPIO9_MODE[1:0
GPIO8_MODE[1:0]
GPIO15_MODE[1:0]
GPIO14_MODE[1:0]
GPIO13_MODE[1:0]
GPIO12_MODE[1:0]
GPIO7_CNF
GPIO6_CNF
GPIO5_CNF
GPIO4_CNF
GPIO3_CNF
GPIO2_CNF
GPIO1_CNF
GPIO0_CNF
GPIO15_CNF
GPIO14_CNF
GPIO13_CNF
GPIO12_CNF
GPIO11_CNF
GPIO10_CNF
GPIO9_CNF
GPIO8_CNF
GPIO7_IOC
GPIO6_IOC
GPIO5_IOC
GPIO4_IOC
GPIO3_IOC
GPIO2_IOC
GPIO1_IOC
GPIO0_IOC
GPIO15_IOC
GPIO14_IOC
GPIO13_IOC
GPIO12_IOC
GPIO11_IOC
GPIO10_IOC
GPIO9_IOC
GPIO8_IOC
GPIO7_IDR
GPIO6_IDR
GPIO5_IDR
GPIO4_IDR
GPIO3_IDR
GPIO2_IDR
GPIO1_IDR
GPIO0_IDR
GPIO15_IDR
GPIO14_IDR
GPIO13_IDR
GPIO12_IDR
GPIO11_IDR
GPIO10_IDR
GPIO9_IDR
GPIO8_IDR
GPIO7_ODR
GPIO6_ODR
GPIO5_ODR
GPIO4_ODR
GPIO3_ODR
GPIO2_ODR
GPIO1_ODR
GPIO0_ODR
Rev 0.6 | 6/102
AN286
Addr 0x2F
0x34 0x35 0x36 0x37
0x44 0x45 0x46 0x47
0x50
0x51 0x52 0x53 0x54 0x55
0x56 0x57 0x58 0x59
TYP
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RW
CUS_PADCTL12
GPIO15_ODR
GPIO14_ODR
GPIO13_ODR
GPIO12_ODR
GPIO11_ODR
GPIO10_ODR
GPIO9_ODR
GPIO8_ODR
0x30 ~ 0x33inaccessible to users
RW
CAL_LFRX_TCAP2
LFRX_TCAP_Z[4:0]
RW
CAL_LFRX_TCAP1
LFRX_TCAP_Y[4:0]
RW
CAL_LFRX_TCAP0
LFRX_TCAP_X[4:0]
CAL_LFRX_OSC_CO RW
DE
LFRX_OSC_IBIAS[6:0]
0x38 ~ 0x43, inaccessible to users
RW
INT_SYSCTL3
S3S_DISABLE
RW
RW
CUS_SYSCTL1
TIMER_M_SLEEP[7:0]
RW
CUS_SYSCTL2
TIMER_M_SLEEP[11:8]
TIMER_R_SLEEP[3:0]
0x48 ~ 0x4F, 8 Bytes HVRAM for user
RW
CUS_SYSCTL3
LED_INV
AFE_IR_EN
SNOOZE_EN
SNOOZE_ DEBUG_EN
LFRX_DEBUG_EN
LFRX_EN
SLPT_WAKEUP _MODE
SLEEP_TIMER_E N
RW
CUS_SYSCTL4
LFRX_MODE[1:0]
LFRX_SIGNAL _OK_TYPE
LFRX_TIMER_EXTEND_MODE[1:0]
DUTY_CYCLE _METHOD
LFRXDUTY CYCLE_EN
ALWAYS_LFRX
RW
CUS_SYSCTL5
LFRX_TIMER_M_RX_T1[4:0]
LFRX_TIMER_R_RX_T1[2:0]
RW
CUS_SYSCTL6
LFRX_TIMER_M_RX_T2[4:0]
LFRX_TIMER_R_RX_T2[2:0]
RW
CUS_SYSCTL7
LFRX_TIMER_M_SLEEP[7:0]
RW
CUS_SYSCTL8
LFRXWAKEUP AUTOCLR_DIS
LFRX_WAKEUP_MODE[1:0]
LFRX_TIMER_R_SLEEP[2:0]
LFRX_RSSIMEAS
RW
CUS_SYSCTL9
LFRX_DBUF_DIS
DIS
LFRX_SNRDET_WIN[2:0]
LFRX_MEAS_WIN[2:0]
RW
CUS_SYSCTL10
GO_LFRX_DECODE
GO_LFRX_LISTEN
GO_LFSLEEP
RW
CUS_LFRX15
LFRX_DBUF_LENGTH[2:0]
LFRX_WKID_EN
LFRX_WKID_LENGTH[1:0]
LFRX_SYNC_LENGTH[1:0]
RW
CUS_LFRX16
LFRX_ANT_MODE[1:0]
LFRX_HOLD_RST_S LFRX_SNRDET_REF
LFRX_MAN_TYPE
LFRX_WKID_MAN_E LFRX_DIG_DATAOU LFRX_DATA_MA
Rev 0.6 | 7/102
www.hoperf.com
AN286
Addr
TYP
0x5A
RW
0x5B
RW
0x5C
RW
0x5D
RW
0x5E
RW
0x5F
RW
0x60
RW
0x61
RW
0x62
RW
0x63
RW
0x64
RW
0x65
RW
0x66
RW
0x67
RW
0x68
RW
0x69
R
0x6A
RW
0x6B
R
0x6C
R
0x6D
RW
0x6E
R
0x6F
RW
Name
CUS_LFRX17 CUS_LFRX18 CUS_LFRX19 CUS_LFRX20 CUS_LFRX21 CUS_LFRX22 CUS_LFRX23
CUS_LFRX24
CUS_LFRX25
CUS_LFRX26
CUS_LFRX27
CUS_LFRX28 CUS_LFRX29 CUS_LFRX30
CUS_SYSCTL11
CUS_SYSCTL12 CUS_SYSCTL13 CUS_SYSCTL14 CUS_SYSCTL15 CUS_SYSCTL16 CUS_SYSCTL17
CUS_SYSCTL18
Bit7
Bit6
Bit5
EL
LFRX_DATAOUT _SEL
LFRX_DECODE
LFRX_SIGNALOK
_SEQ
AUTOCLR_DIS
LFRX_DQRES[3:0]
LFRX_DR_SEL[3:0]
SLPT_MANU_RSTN
LBD_STATUS(IN)
SNOOZE_WAKEUP LBD_FINISH(IN)
LBD_AVG_SEL
Bit4
Bit3
IN_SEL
LFRX_SYNC_VALUE[7:0]
LFRX_SYNC_VALUE[15:8]
LFRX_SYNC_VALUE[23:16]
LFRX_SYNC_VALUE[31:24]
LFRX_WKID_VALUE[7:0]
LFRX_WKID_VALUE[15:8]
LFRX_WKID_VALUE[23:16]
LFRX_WKID_VALUE[31:24]
Bit2
Bit1
Bit0
N
T_SEL
N_EN
LFRX_AGC_EN
LFRX_AGC_STEP
LFRX_AGC_CNT_TH[2:0]
LFRX_CADET_TH_H[7:0]
LFRX_CADET_TH_L[7:0]
LFRX_SIGNAL_OK_CLR_TH[7:0]
SNOOZE_ MANU_CLR
LBD_MANU_CLR
WKID_PASS
SYNC_PASS
LBD_ENABLE
SAR_DATA_UPDATE
SAR_DATA[11:4]
LBD_TH[7:0] LBD_RESULT[7:0] PAD_GROUP2_EN
LFRX_AGC_MIN_INDEX[3:0] LFRXENABLE
MODE
LFRXAGC START_SEL
LFRX_MANU_CLR
SLPT_MANU_CLR BUT_MANU_CLR
LFRX_SIGNAL_OK SAR_MSTART
SLEEP_TIMESUP SAR_TRIGGER
KEY_LAUNCH SAR_CLK_EN
SAR_DATA[3:0]
PAD_GROUP1_EN
LFOSC_CLKOUT_EN
HFOSC_CLKOUT _EN
Rev 0.6 | 8/102
AN286
Addr
TYP
0x70
RW
0x71
RW
0x72
RW
0x73
RW
0x74
RW
0x75
RW
0x76
RW
0x77
RW
0x78
RW
0x79
RW
0x7A
RW
Name CUS_SYSCTL19 CUS_SYSCTL20
CUS_LFRX31
CUS_LFRX32
CUS_LFRX33 CUS_RESV0 CUS_RESV1 CUS_RESV2 CUS_RESV3 CUS_RESV4 CUS_RESV5
Bit7 LFRX_OSC_OUT_EN
MAN_DECODE _ERR_FLAG
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IRLED_DOUT_EN
OTP_CP_VCC_SELN[1:0]
OTP_CP_VTH_SEL
GPIO16_ODR
GPIO16_ODR
GPIO16_MODE[1:0]
LFRX_AGC_INDEX5:0
LFRX_MEAS_OUT[2:0]
LFRXIBIAS CAL_OVTS_FLAG
LFRX_TCAP2/1/0_CAL_OVTS_FLAG
LFRX_DATA_LENGTH[7:0]
Reserved, can be use as HVRAM for user
LPOA0_PIN_DIS
LPOA1_PIN_DIS
inaccessible to users
inaccessible to users
WDT_REFRESH
WDT_START
0x7B ~ 0x7Finaccessible to users
WDT_RESET_TH[2:0]
WDT_DIS
Notes: This color indicates inaccessible areas This color indicates it can be used to store variables that cannot be lost, namely it supports to save variable values in ShutDown mode and they can be read again upon next wake-up.
Rev 0.6 | 9/102
www.hoperf.com
2.2 Block 1 Area Register List
2.2.1 Bank 0 Sub-area Register List
Addr TYP
Bit7
Bit6
0x80 RW
P0
0x81 RW
SP
0x82 RW
DPL
0x83 RW
DPH
0x87 RW 0x88 RW 0x89 RW 0x8A RW 0x8B RW 0x8C RW 0x8D RW 0x8E RW 0x8F RW 0x90 RW 0x91 RW 0x92 RW 0x93 RW 0x94 RW 0x95 RW 0x96 RW 0x97 RW 0x98 RW
PCON TCON TMOD
TL1
TH1
CLK_SYS_DIV
SPI_CTL1_H SPI_CTL1_L SPI_CTL2_H
SPI_DATA_H SPI_DATA_L USART_CTL
SCON0
SMOD1 TF1
GATE1
BIDI_MODE LSB_FIRST
FE0/SM00
SMOD0 TR1 C_T1
LFRX_MCU_RCLK BIDI_OE SPE
SM10
Bit5
Bit4
Bit3
P0_IN[7:0] or P0_OUT[7:0]
SP[7:0]
DPTR[7:0]
DPTR[15:8]
0x84 ~ 0x86, inaccessible to users
GF1
IE1
M1[1:0]
inaccessible to users
TL1[7:0]
inaccessible to users
TH1[7:0]
inaccessible to users
LFRX_MCU_RDATA
inaccessible to users
RX_ONLY
DFF
TXDMAEN
BR[2:0]
inaccessible to users SPI_TXDATA[15:8] SPI_TXDATA[7:0]
SM20
REN0
TB80
Rev 0.6 | 10/102
AN286
Bit2
Bit1
Bit0
GF0
STOP
IDLE
IT1
IE0
IT0
CLK_SYS_DIV[3:0]
SSOE MSTR
SSM CPOL
SSI CPHA
RB80
USART_SEL
TI0
RI0
Addr TYP
0x99 RW
0x9A RW
0x9B RW
0x9C RW
0x9D RW
0x9E R
0x9F
R
0xA0 RW
0xA1 RW
0xA2 RW
0xA3 RW
0xA4 RW
0xA5 RW
0xA6 RW
0xA7 RW
0xA8 RW
0xA9 RW
0xAA RW
0xAB RW
0xAC RW
0xAD RW
0xAE RW
0xAF RW
0xB0 RW
0xB1 RW
0xB2 RW
0xB3 RW
SBUF0 TACLK_DIV_H TACLK_DIV_L TACH TACL TACNT_H TACNT_L
TACCR0H TACCR0L TACCTL0H TACCTL0L TACCR1H TACCR1L
IEN0 TACCTL1H TACCTL1L TACCR2H TACCR2L TACCTL2H TACCTL2L IRQ0_SEL IRQ1_SEL
IRQ2_SEL IRQ3_SEL IRQ4_SEL
Bit7
TACCR0_SCS EA
TACCR1_SCS TACCR2_SCS
AN286
Bit6
TACCR0_CCI
TACCR1_CCI TACCR2_CCI
IRQ_SW[0] IRQ_SW[1] IRQ_SW[2] IRQ_SW[3] IRQ_SW[4]
Bit5
Bit4
Bit3
Bit2
Bit1
SBUF0[7:0]
TACLK_DIV[15:8]
TACLK_DIV[7:0]
TA_START
TACCI3
TA_CNT_MODE[1:0]
TA_CLR
TMR_IE
TIMERA_CNT[15:8]
TIMERA_CNT[7:0]
inaccessible to users
TACCR0[15:8]
TACCR0[7:0]
TACCR0_SCCI
TACCR0_CM[1:0]
TACCR0_CCIS[1:0]
TACCR0_OUTMODE[2:0]
TACCR0_IE
TACCR0_OUT
TACCR0_COV
TACCR1[15:8]
TACCR1[7:0]
inaccessible to users
ES0
ET1
EX1
TACCR1_SCCI
TACCR1_CM[1:0]
TACCR1_CCIS[1:0]
TACCR1_OUTMODE[2:0]
TACCR1_IE
TACCR1_OUT
TACCR1_COV
TACCR2[15:8]
TACCR2[7:0]
TACCR2_SCCI
TACCR2_CM[1:0]
TACCR2_CCIS[1:0]
TACCR2_OUTMODE[2:0]
TACCR2_IE
TACCR2_OUT
TACCR2_COV
IRQ0_SEL[5:0]
IRQ1_SEL[5:0]
IRQ2_SEL[5:0]
IRQ3_SEL[5:0]
IRQ4_SEL[5:0]
Bit0
TACCI2 TMR_IFG
TACCR0_CAP TACCR0_IFG
EX0 TACCR1_CAP TACCR1_IFG
TACCR2_CAP TACCR2_IFG
Rev 0.6 | 11/102
Addr TYP
0xB4 RW
IRQ5_SEL
0xB5 RW
IRQ6_SEL
0xB6 RW
IRQ7_SEL
0xB7 RW TIMER_IN_SEL
0xB8 RW
IPL0
0xB9 RW
TACCI_SEL
0xBA RW
SPI_IN_SEL0
0xBB RW
SPI_IN_SEL1
0xBC RW
P0_IN_SEL0
0xBD RW
P0_IN_SEL1
0xBE RW
P0_IN_SEL2
0xBF RW
P0_IN_SEL3
0xC0 RW
GPIO_IN_R_H
0xC1 RW
GPIO_IN_R_L
0xC2 RW GPIO_OUT_R_H
0xC3 RW GPIO_OUT_R_L
0xC4 RW GPIO_OUT_SEL0
0xC5 RW GPIO_OUT_SEL1
0xC6 RW GPIO_OUT_SEL2
0xC7 RW GPIO_OUT_SEL3
0xC8 RW GPIO_OUT_SEL4
0xC9 RW GPIO_OUT_SEL5
0xCA RW GPIO_OUT_SEL6
0xCB RW GPIO_OUT_SEL7
0xCC RW
LED_CTL
Bit7 SAR_DATA_UPDATE
0xD0 RW
PSW
CY
AN286
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
IRQ_SW[5]
IRQ5_SEL[5:0]
IRQ_SW[6]
IRQ6_SEL[5:0]
IRQ_SW[7]
IRQ7_SEL[5:0]
T1_GPIO_SEL[3:0]
RXD0_IN_GPIO_SEL[3:0]
IPL0.4
IPL0.3
IPL0.2
IPL0.1
TACCI1_GPIO_SEL[3:0]
TACCI0_GPIO_SEL[3:0]
SCK_IN_SEL[3:0]
NSS_IN_SEL[3:0]
MOSI_IN_SEL[3:0]
MISO_IN_SEL[3:0]
PORT01_IN_GPIO_SEL[3:0]
PORT00_IN_GPIO_SEL[3:0]
PORT03_IN_GPIO_SEL[3:0]
PORT02_IN_GPIO_SEL[3:0]
PORT05_IN_GPIO_SEL[3:0]
PORT04_IN_GPIO_SEL[3:0]
PORT07_IN_GPIO_SEL[3:0]
PORT06_IN_GPIO_SEL[3:0]
GPIO_IN_R15:8
GPIO_IN_R7:0
GPIO_OUT_R[15:8]
GPIO_OUT_R[7:0]
GPIO1_OUT_SEL[3:0]
GPIO0_OUT_SEL[3:0]
GPIO3_OUT_SEL[3:0]
GPIO2_OUT_SEL[3:0]
GPIO5_OUT_SEL[3:0]
GPIO4_OUT_SEL[3:0]
GPIO7_OUT_SEL[3:0]
GPIO6_OUT_SEL[3:0]
GPIO9_OUT_SEL[3:0]
GPIO8_OUT_SEL[3:0]
GPIO11_OUT_SEL[3:0]
GPIO10_OUT_SEL[3:0]
GPIO13_OUT_SEL[3:0]
GPIO12_OUT_SEL[3:0]
GPIO15_OUT_SEL[3:0]
GPIO14_OUT_SEL[3:0]
LED_ON
LED_OUT_SEL
PWM_RATE_SEL
PWM_INTERVAL_SEL[3:0]
0xCD ~ 0xCF, inaccessible to users
AC
F0
RS[1:0]
OV
F1
Bit0 IPL0.0
P
Rev 0.6 | 12/102
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Addr TYP
Bit7
0xDD RW GPIO_IN_R_D1
0xDE RW GPIO_OUT_R_D1
0xDF RW
0xE0 RW
ACC
0xE6 RW
IEN1
EX7
0xF0 RW
B
0xF1 RW
IRCON1
IE7
0xF6 RW
IPL1
IPL1.7
0xFF RW
SYS_CTL
SFR_CLK_GATE_EN
Bit6
EX6 IE6 IPL1.6
Bit5
Bit4
Bit3
0xD1 ~ 0xDC, inaccessible to users
inaccessible to users
ACC[7:0]
0xE1 ~ 0xE5, inaccessible to users
EX5
EX4
0xE7 ~ 0xEF, inaccessible to users
B[7:0]
IE5
IE4
0xF2 ~ 0xF5, inaccessible to users
IPL1.5
IPL1.4
0xF7 ~ 0xFE, inaccessible to users
EX3 IE3 IPL1.3
Notes: This color indicates inaccessible areas. This color indicate the original 8051 core register, supporting bit range and direct access (with no need for register bank switching)
Bit2
EX2 IE2 IPL1.2
AN286
Bit1
Bit0
GPIO_IN_R[16] GPIO_OUT_R[16]
Rev 0.6 | 13/102
2.2.2 Bank 1 Sub-area Register List
Addr TYP
Name
Bit7
Bit6
0x8E RW 0x8F RW 0x90 RW 0x91 RW 0x92 RW 0x93 RW 0x94 RW 0x95 RW 0x96 RW 0x97 RW
PA_POWER_TH_9 PA_POWER_TH_8 PA_POWER_TH_7 PA_POWER_TH_6 PA_POWER_TH_5 PA_POWER_TH_4 PA_POWER_TH_3 PA_POWER_TH_2 PA_POWER_TH_1 PA_POWER_TH_0
0xA9 RW
TX_SYM_GROUP
0xAA RW
TX_SYM_CTL
0xAB RW
TX_PKT_CTL
0xAC RW
SYMBOL_TIME_H
0xAD RW
SYMBOL_TIME_L
0xAE RW
FREQ_DEV_H
0xAF RW
FREQ_DEV_L
0xB0 RW RAMP_STEP_TIME_H
0xB1 RW RAMP_STEP_TIME_L
0xB2 RW
0xB3 RW
PA_IDAC_CODE
0xB4 RW
PA_CTL0
0xB5 RW
TX_DIRECT_EN
AN286
Bit5
Bit4
Bit3
Bit2
0x80 ~ 0x8D, inaccessible
PA_POWER_TH_9[6:0]
PA_POWER_TH_8[6:0]
PA_POWER_TH_7[6:0]
PA_POWER_TH_6[6:0]
PA_POWER_TH_5[6:0]
PA_POWER_TH_4[6:0]
PA_POWER_TH_3[6:0]
PA_POWER_TH_2[6:0]
PA_POWER_TH_1[6:0]
PA_POWER_TH_0[6:0]
0x98 ~ 0xA8, inaccessible
TX_SYM_GROUP[7:0] / TX_DIRECT_DATA[0]
TX_GROUP_WIDTH[2:0]
TX_SYM_ENDIAN
RAMP_EN
TX_MODU
SYMBOL_TIME[15:8]
SYMBOL_TIME[7:0]
FREQ_DEV[15:8]
FREQ_DEV[7:0]
RAMP_STEP_TIME[14:8]
RAMP_STEP_TIME[7:0]
inaccessible
PA_IDAC_CODE[5:0]
PA_DIFF_SEL
PA_RCRAMP_SELB
inaccessible
Bit1
Bit0
TX_SYM_CTRL[1:0]
FREQ_DEV_INV
GUASS_ON
PA_RAMP_RSEL[2:0]
Rev 0.6 | 14/102
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Addr TYP 0xB6 RW 0xB7 RW 0xB8 RW 0xB9 RW 0xBA RW 0xBB RW 0xBC RW 0xBD RW 0xBE RW 0xBF RW 0xC0 RW 0xC1 RW 0xC2 RW 0xC3 RW
Name VCO_CTL0 VCO_CTL1
PLLN PLLK_H PLLK_L
RNG_CTL RNG_SUM LBD_CTL LFRX_IF_TH_H
LFRX_IF_TH_L
0xD7 RW 0xD8 RW 0xD9 RW 0xDA RW 0xDB RW 0xDC RW 0xDD RW 0xDE RW 0xDF RW 0xE0 RW 0xE1 RW 0xE2 RW
TBCLK_DIV_H TBCLK_DIV_L
TBCH TBCL TBCCR0H TBCCR0L TBCCTL0H TBCCTL0L TBCCR1H
TBCCR1L TBCCTL1H
AN286
Bit7 VCO_HBAND
TBCCR0_SCS
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
VCO_GAIN_CODE[2:0]
PLL_BW_SEL[1:0]
PDCPLF_CPBIAS_CODE
DIVX_CODE[1:0]
DIVX_SEL[3:0]
inaccessible
PLLN_CFG[7:0]
PLLK_CFG[15:8]
PLLK_CFG[7:0]
inaccessible
inaccessible
RNG_SUM_VLD
RNG_START
RNG_SUM(IN)
LBD_FLAG
LBD_VTH_SEL
LBD_POR_EN
LBD_ON
LFRX_TBCCI0_SEL LFRX_TACCI1_SEL
LFRX_TACCI0_SEL
inaccessible
LFRX_ANT_REF[7:0]
0xC4 ~ 0xD6, inaccessible
TBCLK_DIV[15:8]
TBCLK_DIV[7:0]
TB_START
TBCCI3
TBCCI2
TB_CNT_MODE[1:0]
TB_CLR
TMRB_IE
TMRB_IFG
TBCCR0[15:8]
TBCCR0[7:0]
TBCCR0_CCI
TBCCR0_SCCI
TBCCR0_CM[1:0]
TBCCR0_CCIS[1:0]
TBCCR0_CAP
TBCCR0_OUTMODE[2:0]
TBCCR0_IE
TBCCR0_OUT
TBCCR0_COV
TBCCR0_IFG
TBTACCR1[15:8]
inaccessible
TBTACCR1[7:0]
TBCCR1_CCI
TBCCR1_SCCI
TBCCR1_CM[1:0]
TBCCR1_CCIS[1:0]
TBCCR1_CAP
Rev 0.6 | 15/102
Addr TYP
0xE3 RW
0xE4 RW
0xE5 RW
0xE6 RW
0xE7 RW
0xE8 RW
0xE9 RW
0xEA
R
0xEB
R
Name TBCCTL1L TBCCR2H TBCCR2L
TBCCTL2H TBCCTL2L TBCCI_SEL TBCNT_H TBCNT_L
Bit7 TBCCR1_SCS
TBCCR2_SCS
Notes
This color indicates inaccessible areas.
Bit6
Bit5
Bit4
Bit3
TBCCR1_OUTMODE[2:0]
TBCCR1_IE
TBTACCR2[15:8]
TBTACCR2[7:0]
inaccessible
TBCCR2_CCI
TBCCR2_SCCI
TBCCR2_CM[1:0]
TBCCR2_OUTMODE[2:0]
TBCCR2_IE
TBCCI1_GPIO_SEL[3:0]
TIMERB_CNT[15:8]
TIMERB_CNT[7:0]
0xEC ~ 0xFF, inaccessible
Bit2 TBCCR1_OUT
Bit1 TBCCR1_COV
TBCCR2_CCIS[1:0]
TBCCR2_OUT
TBCCR2_COV
TBCCI0_GPIO_SEL[3:0]
AN286
Bit0 TBCCR1_IFG
TBCCR2_CAP TBCCR2_IFG
Rev 0.6 | 16/102
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AN286
3 Register Details
3.1 T8051 XC3 Core Register Set
Name
P0 SP DPL DPH PCON TCON
TMOD
TL1
TH1
SCON0
SBUF0 IEN0 IPL0 PSW ACC IEN1
B IRCON1
IPL1
Storage Area Block1 Block1 Block1 Block1 Block1 Block1
Block1
Block1
Block1
Block1
Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1
Table 2. 8051 Core Register Set
Sub-area Address Reset
Function
Bank0 Bank0 Bank0 Bank0 Bank0 Bank0
Bank0
Bank0
Bank0
Bank0
Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0
0x80 0x81 0x82 0x83 0x87 0x88
0x89
0x8B
0x8D
0x98
0x99 0xA8 0xB8 0xD0 0xE0 0xE6 0xF0 0xF1 0xF6
0x00 0x00 0x00 0x00 0x00 0x00
0x00
0x00
0x00
0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Port0 register, support bit access, corresponding to the 8 core ports, P0.0P0.7 [1]. Stack pointer register Data pointer (DPTR) register lower 8 bits Data pointer (DPTR) register higher 8 bits Power control register Timer1 control register (see Section 3.2 Timer1 Register Set for details) Timer1 operating mode register (see Section 3.2 Timer1 Register Set for details) The lower 8 bits of the Timer1 register (see Section 3.2 Timer1 Register Set for details) The Timer1 register higher 8 bits (Section 3.2 Timer1 Register Set for details). Serial port 0 control register (see Section 3.8 UART Register Set for deails) Serial 0 data buffer register (see Section 3.8 UART Register Set for deails) Interrupt enabling register 0 Interrupt priority register 0 Program status/flag register Accumulator register Interrupt enabling register 1 B register Peripheral interrupt request flag register Interrupt priority register 1
Notes: Here, P0 is the core port0, the mapping between P0 and CMT216xA GPIOs is configurable.Other words, P0.0 does not nessessary refer to GPIO0. For the mapping between GPIO and P0, see CMT216xA User Guide for more details.
Rev 0.6 | 17/102
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AN286
PCON Register
PCON
7
6
5
SMOD1
SMOD0
—
Reset value0x00
4
3
2
1
0
—
GF1
GF0
STOP
IDLE
Name
7
SMOD1
6
SMOD0
5:4
—
3
GF1
2
GF0
1
STOP
0
IDLE
Decription Serial port 0 double baud rate control bit. Setting to 1 valid when serial port 0 operates in mode 1/2/3 . Serial port 0 frame error (FE) selection bit: When set to 1, read/write SCON0.7 as the FE flag bit. When set to 0, read/write SCON0.7 as the SM0 flag bit. Unused, read as 0 General flag 1 General flag 0 STOP mode control bit [1] IDLE mode control bit [1]
Type R/W
R/W
R R/W R/W R/W R/W
Note: The STOP or IDLE mode only makes the 8051 core enter the power saving mode, but does not mean the whole CMT216xA SoC system enters the power saving mode. If it is required the entire system to enter power saving, the API function sys_shutdown should be called.
PSW Register
PSW
7
6
CY
AC
5
4
3
2
F0
RS1
RS0
OV
Reset value0x00
1
0
F1
P
Name
7
CY
6
AC
5
F0
4:3
RS[1:0]
2
OV
1
F1
0
P
Carrying flag Assisting carrying flag
General flag 0, user operable Operating register set selection: 2’b00:
0x00-0x07 2’b01:0x08-0x0F 2’b10:0x10-0x17 2’b11: 0x18-0x1F Signed calculation
overflow bit
General flag 1, user operable ACC parity indication bit
Description
IRCON1 register
IRCON1
7
6
5
4
3
2
IE7
IE6
IE5
IE4
IE3
IE2
Type R/W R/W R/W
R/W
R/W R/W
R
Reset value0x00
1
0
–
—
Name
7
IE7
6
IE6
5
IE5
External interrupt 7 request flag External interrupt 6 request flag External interrupt 5 request flag
Decription
Rev 0.6 | 18/102
Type R/W R/W R/W
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AN286
Name
4
IE4
3
IE3
2
IE2
1:0
—
External interrupt 4 request flag External interrupt 3 request flag External interrupt 2 request flag Unused, read as 0
Decription
Type R/W R/W R/W
R
IEN0 register
IEN0
7
6
EA
—
5
4
3
2
—
ES0
ET1
EX1
Name
7
EA
6:5
–
4
ES0
3
ET1
2
EX1
1
–
0
EX0
Decription General interrupt enabling bit. It is valid when setting to 1. Unused, read as 0. Serial port 0 interrupt enabling bit. It is valid when setting to 1. Timer 1 interrupt enabling bit. It is valid when setting to 1. External interrupt 1 enabling bit. It is valid when setting to 1. Unused, read as 0. External interrupt 0 enabling bit. It is valid when setting to 1.
Reset value0x00
1
0
—
EX0
Type R/W
R R/W R/W R/W R/W
R
IEN1 register
IEN1
7
6
5
4
3
2
EX7
EX6
EX5
EX4
EX3
EX2
Reset value0x00
1
0
—
—
Name
7:2
Exn
1:0
–
Decription External interrupt n enabling bit. It is valid when setting to 1. Unused, read as 0.
Type R/W
R
Notes: The interrupt is different from the ShutDown (SDN) mode wakeup. Please refer to CMT216xA User Guide for more details.
IPL0 Register
IPL0
7
6
—
—
Reset value0x00
5
4
3
2
1
0
—
IPL0.4
IPL0.3
IPL0.2
—
IPL0.0
Name
7:5
–
4
IPL0.4
3
IPL0.3
2
IPL0.2
1
–
0
IPL0.0
Decription Unused, read as 0. Series port 0 priority. Setting to 1 represents the highest priority. Timer 1 priority. Setting to 1 represents the highest priority. External interrupt 1 priority. Setting to 1 represents the highest priority. Unused, read as 0. External interrupt 0 priority. Setting to 1 represents the highest priority.
Type R
R/W R/W R/W R/W
R
Rev 0.6 | 19/102
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AN286
IPL1 register
IPL1
7
6
IPL1.7
IPL1.6
5 IPL1.5
4 IPL1.4
3 IPL1.3
2 IPL1.2
Reset value0x00
1
0
—
—
Name
7:2
IPL1[7:2]
1:0
–
Decription External interrupt 7~2 priority. Setting to 1 represents the highest priority. Unused, read as 0.
Type R/W
R
Rev 0.6 | 20/102
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AN286
3.2 Timer1 Register Set
Name TCON TMOD
TL1 TH1 TIMER_IN_SEL
Area Block1 Block1 Block1 Block1 Block1
Table 3. Timer1 Module Register Set List
Sub-area Bank0 Bank0 Bank0 Bank0 Bank0
Address 0x88 0x89 0x8B 0x8D 0xB7
Reset 0x00 0x00 0x00 0x00 0x00
Function Timer1 control register Timer1 operating mode register Timer1 register lower 8 bits Timer1 register higher 8 bits Timer1 input selection register
TCON Register
TCON
7
6
5
TF1
TR1
—
Reset value0x00
4
3
2
1
0
—
IE1
IT1
IE0
IT0
Name
7
TF1
6
TR1
5:4
–
3
IE1
2
IT1[1]
1
IE0
0
IT0[1]
Decription Timer 1 overflow bit. Set to 1 by the hardware when Timer1 timer/counter overflows. Timer 1 timer/counter enabling and operating bit Unused, read as 0. External interrupt 1 enabling bit. External interrupt 1 triggering mode. Set to 0, level triggering Set to 1, edge triggering External interrupt 0 enabling bit. External interrupt 0 triggering mode. Set to 0, level triggering Set to 1, edge triggering
Type R/W R/W
R R/W
R/W
R/W
R/W
Notes: The triggering mode of external interrupt 0 and external interrupt 1 is other than the one of traditional 51 core, namely, the level and edge modes are supported. See the IRQn_SEL register description in Section 3.16 IRQn_SEL for details.
TMOD register TMOD
Reset value0x00
7
6
5
4
3
2
1
0
GATE1
C/T1
M1[1]
M1[0]
—
—
—
—
Name
7
GATE1
6
C/T1
5:4
M1[1:0]
Decription Timer 1 gate bit. When set to 1, the T1 input source is valid only when Timer1 operates in the counting mode. Timer 1 count / timing selection bit. Set to 0, select the up-count mode of the internal clock source. Set to 1, select the up-count mode triggered by T1 falling edge input Timer1 operating mode selection 2’b00: Mode 0, 8-bit timing/counting mode with 5-bit prescaler. 2’b01: Mode 1, 16-bit timing/counting mode.
Type R/W R/W
R/W
Rev 0.6 | 21/102
AN286
Name
3:0
–
Decription 2’b10: Mode 2, 8-bit timing/counting mode with reloading. 2’b11: Mode 3, unused, Timer 1 stops. Unused, read as 0.
Type R
TL1/TH1, timer1 counter register
TL1 & TH1
7
6
5
H
L
4
3
2
TH1[7:0]
TL1[7:0]
Name TH1 TL1
Timer1 higher 8-bit count value Timer1 lower 8-bit count value
Decription
Reset value0x00, 0x00
1
0
Type R/W R/W
TIMER_IN_SEL register TIMER_IN_SEL
Reset value0x00
7
6
5
4
3
2
1
0
T1_GPIO_SEL[3:0]
RXD0_IN_GPIO_SEL[3:0]
Name
Decription Timer1 external input signal selection. Can map to GPIO[15:0].
4’b0000, corresponding to GPIO0, namely A0 pin.
4’b0001, corresponding to GPIO1, namely A1 pin.
……
7:4
T1_GPIO_SEL 4’b01114’b0001, corresponding to GPIO7, namely A7 pin.
4’b1000, corresponding to GPIO8, namely A8 pin.
4’b1001, , corresponding to GPIO9, namely A9 pin.
……
4’b1111, , corresponding to GPIO15, namely B7 pin.
Type R/W
Rev 0.6 | 22/102
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AN286
3.3 GPIO Register Set
Name CUS_PADCTL1 CUS_PADCTL2 CUS_PADCTL3
CUS_PADCTL4
CUS_PADCTL5
CUS_PADCTL6
CUS_PADCTL7 CUS_PADCTL8 CUS_PADCTL9 CUS_PADCTL10 CUS_PADCTL11
CUS_PADCTL12
CUS_SYSCTL11 CUS_SYSCTL12 CUS_SYSCTL20
CUS_LFRX3 CUS_LFRX4 CUS_SNOOZE6
P0
TIMER_IN_SEL
TACCI_SEL
SPI_IN_SEL0
SPI_IN_SEL1
P0_IN_SEL0 P0_IN_SEL1 P0_IN_SEL2 P0_IN_SEL3 GPIO_IN_R_H GPIO_IN_R_L
GPIO_OUT_R_H GPIO_OUT_R_L GPIO_OUT_SEL0
Area Block0 Block0 Block0
Block0
Block0
Block0
Block0 Block0 Block0 Block0 Block0
Block0
Block0 Block0 Block0 Block0 Block0 Block0 Block1
Block1
Block1
Block1
Block1
Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1
Table 4. GPIO Register Set List
Sub-area Address Reset
Function
—
0x24 0xFF GPIO0 ~ GPIO15 port mode has the following 3 methods:
—
0x25 0xFF 1. Push-pull output mode or open-drain output mode.
—
0x26 0x7F 2. Digital input mode (configurable pull-up/ pull-down) or
3. Analog input and output mode.
—
0x27 0xFF
4. Floating (default).
—
0x28 0x00 GPIO0 ~ GPIO15 port mode configuration register 1,
responsible for input pull-up/pull-down selection or output
—
0x29 0x00
push-pull/open-drain configuration
—
0x2A 0x00 GPIO0 ~ GPIO15 port IO change interrupt/wake-up enabling
—
0x2B 0x00 register
—
0x2C 0x00 GPIO0 ~ GPIO15 input status saving register, used for IOC
—
0x2D 0x00 function port status transition comparison
—
0x2E 0x00 GPIO0 ~ GPIO15 port mode configuration register 2,
responsible for input pull-up/pull-down enabling and output
—
0x2F 0x00
status saving (output mode)
—
0x68 0x80 System control register 11.
—
0x69 0x00 System control register 12.
—
0x71 0x13 System control register 20
—
0x12 0x2A Low frequency wake-up receiving register 3
—
0x13 0x55 Low frequency wake-up receiving register 3
—
0x23 0x00 SNOOZE configuration register 6
Bank0
0x80 0x00 8051 core Port 0 register
Bank0
0xB7
Timer1 input and GPIO mapping registers, see Section 3.2 0x00
for details.
Bank0
0xB9
Timer A capture module CCI and GPIO mapping, see 0x00
Section 3.9 for details.
Bank0
0xBA
SPI input signal and GPIO mapping configuration register 0, 0x00
see Section 3.7 for details.
Bank0
0xBB
The SPI input signal and GPIO mapping configuration 0x00
register 1, see Section 3.7 for details.
Bank0
0xBC 0x00
Bank0
0xBD 0x00 GPIO[15:0] mapping selection configuration register, when
Bank0
0xBE 0x00 Port0[7:0] is used as the input mode.
Bank0
0xBF 0x00
Bank0
0xC0 0x00 GPIO0 ~ GPIO15 input read register
Bank0
0xC1 0x00 (Note: this register does not support bit access mode)
Bank0
0xC2 0x00 GPIO0 ~ GPIO15 output control register
Bank0
0xC3 0x00 (Note: this register does not support bit access mode)
Bank0
0xC4 0x00 Function selection register when GPIO0 ~ GPIO15 is used
Rev 0.6 | 23/102
AN286
Name GPIO_OUT_SEL1 GPIO_OUT_SEL2 GPIO_OUT_SEL3 GPIO_OUT_SEL4 GPIO_OUT_SEL5
GPIO_OUT_SEL6 GPIO_OUT_SEL7
LED_CTL GPIO_IN_R_D1 GPIO_OUT_R_D1
TBCCI_SEL
Area Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1
Block1
Sub-area Address Reset
Function
Bank0
0xC5 0x00 as output function
Bank0
0xC6 0x00
Bank0
0xC7 0x00
Bank0
0xC8 0x00
Bank0
0xC9 0x00
Bank0
0xCA 0x00
Bank0
0xCB 0x00
Bank0
0xCC 0x00 LED module control register, see section 3.4 for details.
Bank0
0xDD 0x00 GPIO16 (namely D1) input access register
Bank0
0xDE 0x00 PIO16 (namely D1) output access register
Bank1
0xE9
TimerB capture module CCI and GPIO mapping, see section 0x00
3.9 for details.
Notes: This document focuses on the function description of each register. As the CMT216xA SoC on-chip GPIO configuration quite is flexible and rich, it is recommended that users read GPIO realted sections in CMT216xA User Guide and to better understand the function of the above registers.
CUS_PADCTL1 ~ CUSPADCTL4 register set
CUS_PADCTL1 ~ 4
7
6
5
4
1
GPIO3_MODE[1:0]
GPIO2_MODE[1:0]
2
GPIO7_MODE[1:0]
GPIO6_MODE[1:0]
3
GPIO11_MODE[1:0]
GPIO10_MODE[1:0]
4
GPIO15_MODE[1:0]
GPIO14_MODE[1:0]
Reset value0xFF, 0xFF, 0xF7, 0xFF
3
2
1
0
GPIO1_MODE[1:0]
GPIO0_MODE[1:0]
GPIO5_MODE[1:0]
GPIO4_MODE[1:0]
GPIO9_MODE[1:0]
GPIO8_MODE[1:0]
GPIO13_MODE[1:0]
GPIO12_MODE[1:0]
Name GPIOn_MODE
Decription GPIOn operating mode selection. 2’b00: analog input/output 2’b01: digital input 2’b10: digital output 2’b11: floating internally, high impedance (default value except GPIO9)
Type R/W
Notes: When the power supply voltage of the chip is lower than the lower limit of the operating voltage (less than 2.0 V), the GPIO configuration is restored to the default state, namely the floating internally, and the high impedance state externally . However, for B0 ~ B4 specially as simulation and programming pins, the status is different. In this case, B0, B1, B2, and B4 show a pull-up high state and B3 shows a pull-down low state.
Rev 0.6 | 24/102
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AN286
CUS_PADCTL5 ~ CUSPADCTL6 register set CUS_PADCTL5 ~ 6
7
5
GPIO7_CNF
6
GPIO6_CNF
5
GPIO5_CNF
4
GPIO4_CNF
6
GPIO15_CNF
GPIO14_CNF
GPIO13_CNF
GPIO12_CNF
3
GPIO3_CNF GPIO11_CNF
2
GPIO2_CNF GPIO10_CNF
Reset value0x00, 0x00
1
GPIO1_CNF GPIO9_CNF
0
GPIO0_CNF GPIO8_CNF
Name GPIOn_CNF
Decription When GPIOn_MODE[1:0] = 2’b01 and GPIO is in digital input mode, – GPIOn_CNF = 0, it provides a pull-up resistor. – GPIOn_CNF = 1, it provides a pull-down resistor. When GPIOn_MODE[1:0] = 2’b10 and GPIO is in digital output mode, – GPIOn_CNF= 0, it provides push-pull output. – GPIOn_CNF= 1, it provides open-drain output
Type R/W
CUS_PADCTL7 ~ CUSPADCTL8 register set
CUS_PADCTL7 ~ 8
7
6
5
4
7
GPIO7_IOC
GPIO6_ IOC
GPIO5_ IOC
GPIO4_IOC
8
GPIO15_ IOC
GPIO14_ IOC
GPIO13_ IOC
GPIO12_ IOC
3
GPIO3 IOC GPIO11 IOC
2
GPIO2_ IOC GPIO10_IOC
Reset value0x00, 0x00
1
0
GPIO1_ IOC
GPIO0_ IOC
GPIO9_ IOC
GPIO8_ IOC
Name GPIOn_IOC
Decription Set to 0 to disable the IOC interrupt/wake-up function of the GPIOn port. Set to 1 to enable the IOC interrupt/wake-up function of the GPIOn port.
Type R/W
CUS_PADCTL9 ~ CUSPADCTL10 register set
CUS_PADCTL9 ~ 10
7
6
5
4
9
GPIO7_IDR
GPIO6_ IDR
GPIO5_ IDR
GPIO4_ IDR
10 GPIO15_ IDR
GPIO14_ IDR
GPIO13_ IDR
GPIO12_ IDR
3
GPIO3 IDR GPIO11 IDR
2
GPIO2_ IDR GPIO10_IDR
Reset value0x00, 0x00
1
0
GPIO1_ IDR
GPIO0_ IDR
GPIO9_ IDR
GPIO8_ IDR
Name GPIOn_IDR
Decription GPIOn input status saving register Set to 0, input is 0, generate interrupt or wake up the chip when input is detected changing to 1. Set to 1, input is 1, generate interrupt or wake up the chip when input is detected changing to 0.
Type R/W
Rev 0.6 | 25/102
AN286
CUS_PADCTL11 ~ CUSPADCTL12 register set
CUS_PADCTL11 ~ 12
7
6
5
4
9
GPIO7_ODR
GPIO6_ ODR
GPIO5_ ODR
GPIO4_ ODR
10 GPIO15 ODR GPIO14 ODR GPIO13 ODR GPIO12 ODR
3
GPIO3 ODR GPIO11 ODR
2
GPIO2 ODR GPIO10 ODR
Reset value0x00, 0x00
1
0
GPIO1_ ODR
GPIO0_ ODR
GPIO9_ ODR
GPIO8_ ODR
Name GPIOn_ODR
Decription GPIOn mode configuration 2. When GPIOnMODE[1:0] = 2’b01 and GPIO is in digital input mode: – GPIOn ODR = 0, it provides a pull-up resistor. – GPIOn_ ODR = 1, it provides a pull-down resistor. When GPIOnMODE[1:0] = 2’b10 and GPIO is in digital output mode: – GPIOn ODR = 0, both push-pull output and open-drain output output 0[1]. – GPIOn_ ODR = 1, push-pull output outputs 1, open-drain output has no output[1].
Type R/W
Notes [1]. When the CMT216xA enters the Shut Down mode, part of the Block1 register will be reset, so the GPIO status can only be saved through the GPIO associated register in Block0, such as the output high/low state, the input with pull-up/pull-down. GPIOn_ODR is responsible for the function that, in Shut Down mode, it retains the status of whether the input port is with pull- up or pull-down, or whether the port outputs high or low. See CMT216xA User Guide for more details.
CUS_SYSCTL11 Register
CUS_SYSCTL11
7
6
5
SLPT_MAN U_RSTN
Reserved
Reserved
4 SNOOZE_M ANU_CLR
3 LBD_MANU
_CLR
2 LFRX_MAN
U_CLR
Reset value: 0x80
1
0
SLPT_MAN BUT_MANU
U_CLR
_CLR
Name
Decription
In SDN mode, the IOC interrupt manual clearing bit. When it is set to 1, it is
automatially 0 BUT_MANU_CLR
cleared.
Type R/W
CUS_SYSCTL12 Register
CUS_SYSCTL12
7
6
5
Reserved
SNOOZE_W AKEUP
4 WKID_PASS
3 SYNC_PAS
S
2 LFRX_SIGN
AL_OK
Reset value0x00
1
0
SLEEP_TIM KEY_LAUNC
ESUP
H
Name
Decription
0
KEY_LAUNCH
IOC triggering being active flag. It is active when being read as 1.
Type R
Rev 0.6 | 26/102
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AN286
CUS_SYSCTL20 Register
CUS_SYSCTL20
7
6
5
Reserved OTP_CP_VCC_SELN[1:0]
4 OTP_CP_V
TH_SEL
3 GPIO16_O
DR
2 GPIO16_C
NF
Reset value0x13
1
0
GPIO16_MODE[1:0]
Name
Decription
3
GPIO16_ODR For GPIO16 ODR configuration, please refer to GPIO[15:0] ODR configuration.
2
GPIO16_CNF For GPIO16 CNF configuration, please refer to GPIO[15:0] CNF configuration.
For GPIO16 mode configuration, please refer to GPIO[15:0] mode
1:0
GPIO16_MODE
configuration.
Type R/W R/W
R/W
CUS_LFRX3 Register
CUS_LFRX3
7
6
5
4
3
PD_P25
PD_P50
LFRX_AGC_IN[1:0]
Reset value0x2A
2
1
0
LFRX_AGC_VHREF[3:0]
Name
7
PD_P25
6
PD_P50
Decription Configure the output port load capacity. It is a common configuration of GPIO[16:0]: 2’b00, high speed (default). 2’b01, meduim speed. 2’b10, low speed. 2’b11, super-low speed.
Type R/W
R/W
CUS_LFRX4 Register
CUS_LFRX4
7
6
5
4
3
Reserved PD_PULLUP2 LFRX_AGC_CNT[1:0]
Reset value0x55
2
1
0
LFRX_AGC_VLREF[3:0]
Name
Decription
Valid for all GPIO[16:0].
6
PD_PULLUP2 Set to 0 to enable the 500 k pull-up resistor[1]
Set to 1 to disable 500 k pull-up resistor
Type R/W
Notes [1] 1. The 500 k is a weak pull-up, which is disabled by default. The
pull-up mentioned above is a standard pull-up, which is
about 47 k; 2. The difference is that the standard pull-up supports
independent enabling/disabling per each GPIOn, however the weak
pull-up is enabled or disabled as a whole. 3. If both the 2 types of pull-ups
are enabled at the same time, they are in parallel.
Rev 0.6 | 27/102
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AN286
CUS_SNOOZE6 Register
CUS_SNOOZE6
7
6
GPIO_HOLD
Reserved
5
Reserved
4
Reserved
3
DWTH_WK_INT
2
UPTH_WK_INT
Reset value0x00
1
0
WOUT_WK_INT WIN_WK_INT
Name
Decription
GPIO[16:0] output mapping value selection[1]:
7
GPIO_HOLD – Se to 0, output the digital output mapping value.
– Se to 1, output the value of GPIOn_ODR register.
Type R/W
Notes[1]. It is recommended to configure the output port status that is required to be retained in GPIOn_ODR before entering Shut Down mode, then set GPIO to 1 and enter the Shut Down mode. Upon waking-up (to Active mode), clear this bit for operation convenience. See the CMT216xA User Guide for details.
P0_IN_SEL0 ~ P0_IN_SEL3 register set
P0_IN_SEL0/1/2/3
7
6
5
4
0
PORT01_IN_GPIO_SEL[3:0]
1
PORT03_IN_GPIO_SEL[3:0]
2
PORT05_IN_GPIO_SEL[3:0]
3
PORT07_IN_GPIO_SEL[3:0]
Reset value0x00/0x00/0x00/0x00
3
2
1
0
PORT00_IN_GPIO_SEL[3:0]
PORT02_IN_GPIO_SEL[3:0]
PORT04_IN_GPIO_SEL[3:0]
PORT06_IN_GPIO_SEL[3:0]
Name PORT0n_IN_GPIO_SEL
Decription When 8051core Port0 is input port, the mapping with GPIOn is:
4’b0000, map to GPIO0 input, corresponding to the A0 pin.
4’b0001, map to GPIO1 input, corresponding to the A11pin. 4’b0010, map to
GPIO2 input, corresponding to the A2 pin. …… 4’b0111, map to GPIO7 input,
corresponding to the A7 pin. 4’b1000, map to GPIO8 input, corresponding to the
B0 pin. …… 4’b1110, map to GPIO14 input, corresponding to the B6 pin. 4’b1111,
map to GPIO15 input, corresponding to the B7 pin.
Type R/W
GPIO_IN_R_H/GPIO_IN_R_L register set
GPIO_IN_R_H/L
7
6
5
4
3
2
H
GPIO_IN_R15:8
L
GPIO_IN_R7:0
Name GPIO_IN_R[15:0]
Decription GPIOn input mode mapping register. The range of n is 0 ~ 15.
Reset value0x00/0x00
1
0
Type R/W
Rev 0.6 | 28/102
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AN286
GPIO_OUT_R_H/GPIO_OUT_R_L register set
GPIO_OUT_R_H/L
7
6
5
4
3
2
H
GPIO_OUT_R15:8
L
GPIO_OUT_R7:0
Name GPIO_OUT_R[15:0]
Decription GPIOn output mode mapping register. The range of n is 0 ~ 15.
Reset value0x00/0x00
1
0
Type R/W
GPIO_IN_R_D1
GPIO_IN_R_D1
7
6
Name GPIO_IN_R[16]
5
4
3
2
Reserved
Decription GPIO16 (namely D1) input mode mapping register
Reset value0x00
1
0
GPIO_IN_R[16]
Type R
GPIO_OUT_R_D1
GPIO_OUT_R_D1
7
6
Name GPIO_OUT_R[16]
5
4
3
2
Reserved
Decription GPIO16 (namely D1) output mode mapping register.
Reset value0x00
1
0
GPIO_OUT_R[16]
Type R/W
Rev 0.6 | 29/102
AN286
GPIO_OUT_SEL0 ~ GPIO_OUT_SEL7 register set GPIO_OUT_SEL0GPIO_OUT_SEL7
7
6
5
4
3
0
GPIO1_OUT_SEL[3:0]
1
GPIO3_OUT_SEL[3:0]
2
GPIO5_OUT_SEL[3:0]
3
GPIO7_OUT_SEL[3:0]
4
GPIO9_OUT_SEL[3:0]
5
GPIO11_OUT_SEL[3:0]
6
GPIO13_OUT_SEL[3:0]
7
GPIO15_OUT_SEL[3:0]
Reset value: all 0x00
2
1
0
GPIO0_OUT_SEL[3:0]
GPIO2_OUT_SEL[3:0]
GPIO4_OUT_SEL[3:0]
GPIO6_OUT_SEL[3:0]
GPIO8_OUT_SEL[3:0]
GPIO10_OUT_SEL[3:0]
GPIO12_OUT_SEL[3:0]
GPIO14_OUT_SEL[3:0]
Name
Decription
GPIOn_OUT_SEL
The mapping configuration of GPIOn when it operates as output:
Value Binary
Function Description
Map to GPIO_OUT_R[15:0], namely control input status through
the 2 registers, GPIO_OUT_R_H/L with one-to-one 0 4’b0000
correspondence. For example, GPIO1 is corresponding to
GPIO_OUT_R_L Bit1. This is the default value of GPIOn output.
Map to Port0 output. Both GPIO[7:0] and GPIO[15:8] can be
configured to the corresponding Port0[7:0] with one-to-one
correspondence. For example, GPIO7 or GPIO15 can be mapped 1 4’b0001
to Port0.7, and GPIO10 or GPIO2 can be mapped to Port0.2. When
this value is selected, GPIOn can be controlled through Port0.n
output control.s
2 4’b0010 Map to TB_OUT0, TimerB captures/compares module 0 output.
3 4’b0011 Map to TB_OUT1, TimerB capture/compare module 1 output.
4 4’b0100 Map to TB_OUT2, TimerB capture/compare module 2 output.
5 4’b0101 Map to NSS_OUT, SPI module master mode chip selection output.
6 4’b0110 Map to SCK_OUT, SPI module master mode clock output.
7 4’b0111 Map to MISO_OUT, SPI module Slave mode data output.
8 4’b1000 Map to MOSI_OUT, SPI module Master mode data output.
9 4’b1001 Map to RxD0_OUT, UART module output enabling signal.
10 4’b1010 Map to TxD_OUT, UART module clock or data output.
11 4’b1011 Map to TA_OUT0, TimerA captures/compares module 0 output.
12 4’b1100 Map to TA_OUT1, TimerA capture/compare module 1 output.
13 4’b1101 Map to TA_OUT2, TimerA capture/compare module 2 output.
14 4’b1110 Map to LED_OUT_LV, the PWM output generated by LED module.
15 4’b1111 Map to T1_OV, overflow flag of Timer1 module.
Type R/W
Rev 0.6 | 30/102
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AN286
3.4 LED Module
Name CUS_SYSCTL3
LED_CTL
Area Block0 Block1
Table 5. LED Module Register Set List
Sub-area Address Reset
Function
—
0x50 0x00 System control register 3
Bank0
0xCC 0x00 LED control register
CUS_SYSCTL3 Register CUS_SYSCTL3
7 LED_INV
6 AFE_IR_EN
5 SNOOZE_E
N
4 SNOOZE_D EBUG_EN
3 LFRX_DEBU
G_EN
2 LFRX_EN
Reset value0x00
1 SLPT_WAK EUP_MODE
0 SLEEP_TIM
ER_EN
Name
7
LED_INV
Decription LED module output direction enabling Set to 0, high level is normal state and low level drives LED. Set to 1, low level is normal state and high level drives LED.
Type R/W
LED_CTL Register LED_CTL
7 SAR_DATA_UPDATE
6 LED_ON
5 LED_OUT_SEL
4 PWM_RATE_SEL
Reset value0x00
3
2
1
0
PWM_INTERVAL_SEL[3:0]
Name
Decription
Type
6
LED_ON
LED module enabling. 0: disable. 1, enable.
R/W
LED module output mode selection:
5
LED_OUT_SEL
Set to 0, output TX baseband data.
R/W
Set to 1, output PWM signal.
PWM frequency selection (if LED_OUT_SEL selects the PWM signal as valid
signal):
4
PWM_RATE_SEL
R/W
Set to 0, PWM is 3.34 kHz.
Set to 1, PWM is 6.68 kHz.
PWM duty cycle selection, ranging from 0 to 15 with 16 levels of duty cycle, each
3:0 PWM_INTERVAL_SEL
R/W
level increasing by 1 / 16.
Rev 0.6 | 31/102
AN286
3.5 S3S Programming Interface
Name INT_SYSCTL3
Area Block0
Table 6. SPI Module Register Set List
Sub-area Address Reset
Function
—
0x44
INT system control register 3
INT_SYSCTL3 register
INT_SYSCTL3
7
6
5
4
Reserved Reserved S3S_DISABLE
3
2
Reserved
Reset value: 0xC4
1
0
Name
Decription
Type
S3S debug port function enabling control (control PB1 ~ PB4, namely GPIO9 ~ GPIO12).
5
S3S_DISABLE Set to 0, the S3S debug port is used as a programming port.
R/W
Set to 1, S3S is used as GPIO.
3.6 LBD Module
Name CUS_SYSCTL11 CUS_SYSCTL13 CUS_SYSCTL16 CUS_SYSCTL17
LBD_CTL
Area Block0 Block0 Block0 Block0 Block1
Table 7. LBD Module Register Set List
Sub-area —–
Bank1
Address 0x68 0x6A 0x6D 0x6E 0xC0
Reset 0x80 0x00 0x00 0x00 0x24
Function System control register 11 System control register 13 System control register 16 System control register 17 LBD control register
CUS_SYSCTL11 register
CUS_SYSCTL11
7
6
5
SLPT_MAN U_RSTN
Reserved
Reserved
4 SNOOZE_M ANU_CLR
3 LBD_MANU
_CLR
2 LFRX_MAN
U_CLR
Reset value0x80
1
0
SLPT_MAN BUT_MANU
U_CLR
_CLR
Name
Decription
When the low voltage detection is completed, it needs clear the end flag manually.
3
LBD_MANU_CLR
When set to 1, the system clears it automatically.
Type R/W
Rev 0.6 | 32/102
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AN286
CUS_SYSCTL13 register
CUS_SYSCTL13
7
6
5
LBD_STATUS LBD_FINISH LBD_AVG_SEL
4 LBD_ENABLE
Reserved
2 SAR_MSTART
Reset value0x00
1
0
SAR_TRIGGER SAR_CLK_EN
Name
Decription
Low voltage detection results.
7
LBD_STATUS
Read as 0, the power supply voltage is higher than the set threshold.
Read as 1, the power supply voltage is lower than the set threshold.
6
LBD_FINISH
Low voltage detection end flag.
Low voltage detection result (LBD_RESULT) sampling times selection.
5
LBD_AVG_SEL
Set to 0, average the the results of 8 successive samplings
Set to 1, sample once for measurement.
Set to 0, LBD module is disabled.
4
LBD_ENABLE
Set to 1, LBD module is enabled.
Type R R
R/W R/W
CUS_SYSCTL16 register
CUS_SYSCTL16
7
6
5
4
3
2
LBD_TH[7:0]
Name LBD_TH
Decription Low voltage detection comparison threshold
Reset value0x00
1
0
Type R/W
CUS_SYSCTL17 register
CUS_SYSCTL17
7
6
5
Name LBD_RESULT
4
3
2
LBD_RESULT[7:0]
Decription Low voltage detection result
Reset value0x00
1
0
Type R
Note: The low-voltage detection module uses VBG (1.2V) as the reference
voltage and measures VBAT / 4 (VDD / 4), so setting LBD_TH or reading
LBD_RESULT is calculated according to the following formulas.
LBD_TH = LBD × 255 4.8
=
_ 255
×
4.8
Rev 0.6 | 33/102
AN286
LBD_CTL register
LBD_CTL
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 LBD_FLAG
2 LBD_VTH_SEL
Reset value0x24
1
0
LBD_POR_EN LBD_ON
Name
Voltage monitoring flag.
Decription
Type
3
LBD_FLAG
Read as 0, in normal.
R
Read as 1, voltage is lower than the monitoring threshold.
Voltage monitoring threshold selection.
2
LBD_VTH_SEL Set to 0, the monitoring threshold is 1.8 V.
R/W
Set to 1, the monitoring threshold is 2.0 V.
Whether the power supply resets the chip when the power supply voltage is
lower than the monitoring threshold (LBD_VTH_SEL selection).
1
LBD_POR_EN
R/W
Set to 0, not reset.
Set to 1, reset (this reset is equivalent to re-poweron).
Set to 0, the power supply voltage monitoring is disabled.
0
LBD_ON
R/W
Set to 1, the power supply voltage monitoring is enabled.
Notes: 1. Suggest users call the API sys_start_stop_supply_voltage_supervision
to configure of LBD monitoring rather than
configure this register directly since the LBD voltage monitoring function
still requires other related configurations.
2. Users can either read LBD_FLAG or call the API call the API function
sys_read_result_from_supply_voltage_supervision to
query the voltage monitoring status.
Rev 0.6 | 34/102
AN286
3.7 SPI Register Set
Name SPI_CTL1_H SPI_CTL1_L SPI_CTL2_H SPI_DATA_H SPI_DATA_L SPI_IN_SEL0 SPI_IN_SEL1
Area Block1 Block1 Block1 Block1 Block1 Block1 Block1
Table 8. SPI Module Register Set List
Sub-area Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0
Address 0x91 0x92 0x93 0x95 0x96 0xBA 0xBB
Reset 0x00 0x00 0x02 0x00 0x00 0x00 0x00
Function SPI module control register1 higher byte SPI module control register1 lower byte SPI module control register2 higher byte SPI module data higher byte SPI module data lower byte SPI input signal and GPIO mapping register0 SPI input signal and GPIO mapping register1
SPI_CTL1_H register
SPI_CTL1_H
7
6
5
4
3
2
BIDI_MODE
BIDI_OE RX_ONLY
DFF
TXDMAEN
SSOE
Reset value0x00
1
0
SSM
SSI
Name
Decription
Type
SPI module bidirectional data mode selection:
7
BIDI_MODE
Set to 0, select 2-wire bidirectional mode, namely, 4-wire SPI mode.
R/W
Set to 1, select single line bidirectional mode, namely, 3-wire SPI mode.
Data line output direction in the single line bidirectional mode (BIDI_MODE = 1):
Set to 0, the output is disabled (receiving-only mode).
Set to 1, the output is enabled (sending-only mode).
6
BIDI_OE
R/W
Note: in the single line bidirectional mode, on the host side, if the host is the sender,
the data line is mosi. Otherwise, the data line is miso. On the slave side, if the slave is
the sender, the data line is miso. Otherwise, the data line is mosi
In the 2-line bidirectional mode (BIDI_MODE = 0), for multiple slave configuration, set
this bit to 1 to let only the accessed slave devices output, so that no data conflicts will
5
RX_ONLY
occur in the data line.
R/W
Set to 0, full duplex (transmiting and receiving);
Set to 1, disable output (receiving-only);
Data frame format selection.
4
DFF
Set to 0, transmit or receive using a 8-bit data frame format.
R/W
Set to 1, transmit or receive using a 16-bit data frame format.
SPI DMA function enabling bit:
3
TXDMAEN
Set to 0, disable the DMA function.
R/W
Set to 1, enable the DMA function.
SS output enabling:
Set to 0 to disable SS output in the master mode. The device can operate in the
2
SSOE
multi-master mode.
R/W
Set to 1,enable SS output in the master mode, the device can not operate in the
multi-master mode.
Rev 0.6 | 35/102
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AN286
Name
1
SSM
0
SSI
Decription Software slave device management. When set to 1, the level on the NSS pin is determined by the value of the SSI bit. Set to 0, disable software slave device management. Set to 1, enable software slave device management. Internal slave device selection. Valid when SSM = 1. It determines the level on the NSS. The IO operation on the NSS pin is invalid in this case.
Type R/W R/W
SPI_CTL1_L register
SPI_CTL1_L
7
6
LSB_FIRST
SPE
5
4
3
BR[2:0]
2 MSTR
1 CPOL
Reset value0x00 0
CPHA
Name
Decription
Frame format selection.
7
LSB_FIRST
Set to 0, transmit MSB first. Data shifts to the left.
Set to 1, transmit LSB first. Data shifts to the right.
SPI module enabling bit:
6
SPE
Set to 0, disable SPI module.
Set to 1, enable SPI module.
SPI baud rate selection (FPCLK system clock, detault as 24 MHz).
3’b000, baud rate is FPCLK/2.
3’b001, baud rate is FPCLK /8.
3’b010, baud rate is FPCLK /16.
5:3
BR[2:0]
3’b011, baud rate is FPCLK /24.
3’b100, baud rate is FPCLK /32.
3’b101, baud rate is FPCLK /64.
3’b110, baud rate is FPCLK /128.
3’b111, baud rate is FPCLK /256.
Master and slave mode selection.
2
MSTR
Set to 0, configure as slave mode.
Set to 1, configure as master mode.
SPI clock polarity.
1
CPOL
Set to 0, in the idle state, SCK remains low.
Set to 1, in the idle state, SCK remains high.
SPI clock phase.
0
SSOE
Set to 0, data sampling begins on the first clock edge.
Set to 1, data sampling begins on the second clock edge.
Type R/W R/W
R/W
R/W R/W R/W
Notes: When data communication is ongoing, cannot modify this register’s value.
Rev 0.6 | 36/102
AN286
SPI_CTL2_H register
SPI_CTL2_H
7
6
5
4
Reserved
Reset value0x02
3
2
1
0
SPI_BUSY SPI_TXE
SPI_RXNE
Name
Decription
Type
SPI busy flag.
Read as 0, SPI not busy.
2
SPI_BUSY
Read as 1, SPI busy in communication, or tranmission buffer not empty.
R/W
Notes: This bit is set or reset by the hardware. In the master mode with
receiving-only (single line bidirectional), it is forbidden to check the flag.
SPI transmitting buffer not empty.
1
SPI_TXE
Read as 0, transmitting buffer not empty.
R/W
Read as 1, transmitting buffer empty.
SPI receiving buffer not empty.
0
SPI_RXNE
Read as 0, receiving buffer not empty.
R/W
Read as 1, receiving buffer empty.
SPI_DATA_H/SPI_DATA_L register set
SPI_CTL2_H/L
7
6
5
4
3
2
H
SPI_DATA[15:8]
L
SPI_DATA[7:0]
Reset value0x00/0x00
1
0
Name SPI_TXDATA
Decription SPI data register, buffering data to be sent or received. The data register has two buffers, one for writing (sending buffer), the other for reading (receiving buffer). A write operation writes data to the sending buffer; a read operation returns the data in the receiving buffer.
Type R/W
SPI_IN_SEL0/SPI_IN_SEL1 register set SPI_IN_SEL0/1
Reset value0x00/0x00
7
6
5
4
3
2
1
0
0
SCK_IN_SEL[3:0]
NSS_IN_SEL[3:0]
1
MOSI_IN_SEL[3:0]
MISO_IN_SEL[3:0]
Name NSS_IN_SEL SCK_IN_SEL MISO_IN_SEL MOSI_IN_SEL
Decription In SPI bus slave mode, chip selection input signal maps to GPIO[15:0] In SPI bus Slave mode, clock input signal maps to GPIO[15:0] In SPI bus Master mode, data input signal maps GPIO[15:0] In SPI bus Slave mode, data input signal maps to GPIO[15:0]
Type R/W R/W R/W R/W
Rev 0.6 | 37/102
www.hoperf.com
Notes:
1. The selection mapping is as follows. 4’b0000, mapping to GPIO0 input,
corresponding to A0 pin. 4’b0001, mapping to GPIO1 input, corresponding to A1
pin. -4’b0010, mapping to GPIO2 input, corresponding to A2 pin. … 4’b0111,
mapping to GPIO7 input, corresponding to A7 pin. 4’b1000, mapping to GPIO8
input, corresponding to B0 pin. … 4’b1110, mapping to GPIO14 input,
corresponding to B6 pin. 4’b1111, mapping to GPIO15 input, corresponding to B7
pin.
AN286
Rev 0.6 | 38/102
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AN286
3.8 UART Register Set
Name SCON0
PCON
SBUF0 USART_CTL TIMER_IN_SEL
Area Block1
Block1
Block1 Block1 Block1
Table 9. UART Register Set List
Sub-area Bank0
Bank0
Bank0 Bank0 Bank0
Address 0x98
0x87
0x99 0x97 0xB7
Reset 0x00
0x00
0x00 0x00 0x00
Function Series port 0 control register. Power consumption control register, refer to Section 3.1 for details. Port 0 data buffer register. UART control register. Timer1 input selection register.
SCON0 Register
SCON0
7
6
FE0/SM00
SM10
5 SM20
4 REN0
3 TB80
2 RB80
Reset value0x00
1
0
TI0
RI0
Name
7
FE0
7
SM00
Decription Series port 0 frame error flag. When PON.6 = 1, access is valid. When an incorrect STOP bit is received, it is set to 1 by the hardware automatically. Series port 0 mode configuration Bit0. When PCON.6 = 0, access is valid. Cooperate with SM10 and SM20 series port 0 operating mode configuration.
Type R/W R/W
Series port 0 mode configuration bit1:
SM00 SM10 Mode
Description
0
0
0 Synchronous shift register. Fix to FPCLK/12 baud rate.
6
SM10
0
1
1 8-bit UART, configurable baud rate and clock generated by Timer1.
R/W
1
0
2 9-bit UART, FPCLK/64 or FPCLK/32 baud rate.
9-bit UART, baud rate is configurable and clock is generated by
1
1
3
Timer1.
5
SM20 Series port 0 mode configuration bit2, namely multimachine control bit.
R/W
Serial receiving enabling bit. In the UART mode, set to 1 to enable receiving.
4
REN0 In mode 0, set to start data input transfer. Must clear it to 0 to enable data output transfer (write to R/W
SBUF0)
3
TB80 The 9th bit of 9-bit transmitting mode.
R/W
2
RB80 The 9th bit of 9-bit receiving mode.
R/W
1
TI0 Series port 0 transmitting interrupt flag.
R/W
0
RI0 Series port 0 receiving interrupt flag.
R/W
Rev 0.6 | 39/102
AN286
SBUF0 register SBUF0
Reset value0x00
7
6
5
4
3
2
1
0
SBUF0[7:0]
Name SBUF0
Decription Series port 0 data buffer
Type R/W
USART_CTL register
USART_CTL
7
6
Reserved
Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
Reset value0x00
1
0
Reserved UART_SEL
Name
Decription
UART baud rate ehancement control bit.
0 UART_SEL Set to 0, disable.
Set to 1, enable.
Type R/W
Notes: When this bit is set, the preset frequency division by 12 of timer1 is closed. In this case, for UART1 and UART3 modes, it can fulfill multiple more accurate baud rates. Refer to CMT216xA User Guide for more details.
TIMER_IN_SEL register TIMER_IN_SEL
Reset value0x00
7
6
5
4
3
2
1
0
T1_GPIO_SEL[3:0]
RXD0_IN_GPIO_SEL[3:0]
Name
Decription
UART0 external input signal selection, with configurably mapping to GPIO[15:0]. 4’b0000, corresponding to GPIO0, namely A0 pin. 4’b0001, corresponding to GPIO1, namely A1 pin. … 3:0 RXD0_IN_GPIO_SEL 4’b0111, corresponding to GPIO7, namely A7 pin. 4’b1000, corresponding to GPIO8, namely B0 pin. 4’b1001, corresponding to GPIO9, namely B1 pin. … 4’b1111, corresponding to GPIO15, namely B7 pin.
Type R/W
Rev 0.6 | 40/102
AN286
3.9 16-Bit TimeA and TimerB Register Set
Name TACLK_DIV_H TACLK_DIV_L
TACH TACL TACNT_H TACNT_L TACCR0H TACCR0L TACCTL0H TACCTL0L TACCR1H TACCR1L
TACCTL1H TACCTL1L TACCR2H TACCR2L TACCTL2H TACCTL2L TACCI_SEL TBCLK_DIV_H
TBCLK_DIV_L TBCH TBCL TBCCR0H TBCCR0L TBCCTL0H TBCCTL0L TBCCR1H TBCCR1L
TBCCTL1H TBCCTL1L TBCCR2H TBCCR2L TBCCTL2H TBCCTL2L
TBCCI_SEL
TBCNT_H
Area Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1
Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1
Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1
Block1 Block1 Block1
Block1
Block1
Table 10. 16-Bit TimerA and TimerB Register Set
Sub-area Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0
Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank1 Bank1 Bank1 Bank1 Bank1
Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1
Bank1
Bank1
Address 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA9 0xAA
0xAB 0xAC 0xAD 0xAE 0xB9 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE1
0xE2 0xE3 0xE4 0xE5 0xE7 0xE8
0xE9
0xEA
Reset 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x40 0x00
0x00 0x00 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00
0x40 0x00 0x00 0x00 0x40 0x00
0x00
0x00
Function TimerA clock source frequency division register TimerA control register TimerA 16-bit real-time count register TimerA capture/compare module 0 register TimerA capture/compare module 0 control register TimerA capture/compare module 1 register TimerA capture/compare module 1 control register TimerA capture/compare module 2 register TimerA capture/compare module 2 control register TimerA capture module CCI and GPIO mapping TimerB clock source frequency division register TimerB control register TimerB capture/compare module 0 register TimerB capture/compare module 0 control register TimerB capture/compare module 1 register TimerB capture/compare module 1 control register TimerB capture/compare module 2 register TimerB capture/compare module 2 control register TimerB capture module CCI and GPIO mappin, see Section 3.7 for details. TimerB 16-bit real-time count register
Rev 0.6 | 41/102
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AN286
Name TBCNT_L
Area Sub-area Address Reset
Block1 Bank1
0xEB 0x00
Function
TACLK_DIV, TimerA clock source division register
TACLK_DIV_H & TACLK_DIV_L
7
6
5
4
3
2
H
TACLK_DIV[15:8]
L
TACLK_DIV[7:0]
Reset value0x00, 0x00
1
0
Name TACLK_DIV
Decription TimerA clock source division factor. TACLK = FPCLK/TACLK_DIV, FPCLK is system clock, defualt as 24MHz. The TACLK_DIV range is 165535.
Type R/W
TACH, TimerA control register higher byte
TACH
7
6
5
4
Reserved
Reserved
Reserved
Reserved
3 Reserved
2 TA_START
Reset value0x00
1
0
TACCI3
TACCI2
Name
TimerA enabling bit.
Decription
2
TA_START Set to 1, enable the TimerA module.
Set to 0, disable the TimerA module.
1
TACCI3
Software configurable capture source input 3.
0
TACCI2
Software configurable capture source input 2.
Type R/W
R/W R/W
TACL and TimerA control register lower byte
TACL
7
6
5
4
3
Reserved
Reserved
Reserved
TA_CNT_MODE[1:0]
2 TA_CLR
1 TMRA_IE
Reset value0x00 0
TMRA_IFG
Name
TimerA count mode selection.
Decription
Type
2’b00, Stop mode, TimerA stopping count mode.
4:3 TA_CNT_MODE 2’b01, Up mode, TimerA up count mode.
R/W
2’b10, Continuous mode, TimerA continuous count mode.
2’b11, Up / Down mode, Timer up and down count mode.
TimerA clearing control bit.
2
TA_CLR
When set, it will reset TACNT, count direction, TACLK_DIV_H, TACLK_DIV_L, and TimerA R/W
related registers except register TACH/TACL.
1
TMRA_IE
TimerA interrupt enabling bit. When set to 1, run TimerA count interrupt request.
R/W
0
TMRA_IFG TimerA counts the interrupt flag, which is set when the TACNT count returns to 0 again.
R/W
Rev 0.6 | 42/102
AN286
TACNT_H/TACNT_L, TimerA real-time count register
TACNT_H & TACNT_L
7
6
5
4
3
2
H
TACNT[15:8]
L
TACNT[7:0]
Reset value0x00, 0x00
1
0
Name TACNT
Decription TimerA’s real-time count value, read-only register, can be cleared by TA_CLR
Type R
TACCR0H/TACCR0L, TimerA capture/compare module 0 register
TACCR0H & TACCR0L
7
6
5
4
3
2
H
TACCR0[15:8]
L
TACCR0[7:0]
Reset value0x00, 0x00
1
0
Name TACCR0
Decription TimerA capture/compare module 0 register. In compare mode, it saves the data that TACNT needs to compare with. In capture mode, it saves the count value of Timer A upon successful capture.
Type R/W
TACCTL0H, TimerA capture/compare module 0 control register higher byte
TACCTL0H
7
6
5
4
3
2
1
Reserved TACCR0_CCI TACCR0_SCCI
TACCR0_CM[1:0]
TACCR0_CCIS[1:0]
Reset value0x40 0
TACCR0_CAP
Name
Decription
6
TACCR0_CCI The value of the selected capture source, which can be read by the software.
When EQUx is valid, the selected captured value is stored and can be read by
5
TACCR0_SCCI
software.
Capture mode selection.
2’b00, not captured.
4:3
TACCR0_CM 2’b01, capture the rising edg.
2’b10, capture the falling edge.
2’b11, capture double edges.
Capture source selection.
2’b00, TACCI0.
2’b01, TACCI1.
2:1
TACCR0_CCIS 2’b10, TACCI2.
2’b11, TACCI3.
Among them, TACCI0 and TACCI1 are from GPIO mapping (see
TACCI_SELregister), TACCCI2 and TACCI3 are from register (see TACHregister);
Set to 0 to select the comparison mode.
0
TACCR0_CAP
Set to 1, select the capture mode.
Type R R
R/W
R/W
R/W
Rev 0.6 | 43/102
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AN286
TACCTL0L, TimerA capture/compare module 0 control register lower byte
TACCTL0L
7
6
5
4
3
2
TACCR0_SCS
TACCR0_OUTMODE[2:0]
TACCR0_IE TACCR0_OUT
Reset value0x00
1
0
TACCR0_COV TACCR0_IFG
Name
Decription
Set to 0, the selected capture source is not synchronized with the system clock.
7
TACCR0_SCS
Set to 1, the selected capture source is synchronized with the system clock.
Output mode selection:
3’b000, direct output mode.
3’b001, set output mode.
3’b010, reverse/reset output mode.
3’b011, set/reset output mode;
3’b100, reverse output mode. 6:4 TACCR0_OUTMODE
3’b101, reset output mode.
3’b110, reverse /set output mode.
3’b111, reset /set output mode.
Type R/W
R/W
Note: The function is explained in detail in the Section TimerA / B in CMT16xA User
Guide.
3
TACCR0_IE
TimerA capture/compare module 0 interrupt enabling bit
R/W
Can only be used in output mode 0 (TACCR0_OUTMODE=0), get throught directly
2
TACCR0_OUT
R/W
to the corresponding output signal
Capture overflow flag. Reading as 1 means that the previous capture source
1
TACCR0_COV
triggering result is not read yet, the current trigger source is captured currently, and R/W
software clearing is required.
0
TACCR0_IFG
TimerA capture/compare 0 interrupt flag
R/W
TACCR1H/TACCR1L, TimerA capture/compare module1 register
TACCR1H & TACCR1L
7
6
5
4
3
H
TACCR1[15:8]
L
TACCR1[7:0]
Reset value0x00, 0x00
2
1
0
Name TACCR1
Decription TimerA capture/compare module1 register. In compare mode, it saves the data required to be compared with TACNT. In capture mode, it saves the current count value of Timer A.
Type R/W
Rev 0.6 | 44/102
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AN286
TACCTL1H, TimerA capture/compare module1control register higher byte TACCTL1H
Reset value0x40
7
6
5
4
3
2
1
0
Reserved TACCR1_CCI TACCR1_SCCI
TACCR1_CM[1:0]
TACCR1_CCIS[1:0]
TACCR1_CAP
Name
Decription
Type
6
TACCR1_CCI The selected capture source value. Can be read by the software.
R
5
TACCR1_SCCI When EQUx is valid, it saves the selected capture value. Can be read by the software.
R
Capture mode selection.
2’b00, not capture.
4:3
TACCR1_CM 2’b01, capture on the rising edge.
R/W
2’b10, capture on the falling edge.
2’b11, capture on both edges.
Capture source selection.
2’b00, TACCI0.
2’b01, TACCI1.
2’b10, TACCI2.
2:1
TACCR1_CCIS
R/W
2’b11, TACCI3.
Among them, TACCI0 and TACCI1 come from GPIO mapping ( see TACCI_SEL
register for details). TACCCI2 and TACCI3 come from register ( see TACH register for
details).
Set to 0, select compare mode.
0
TACCR1_CAP
R/W
Se to 1, select capture mode.
TACCTL1L, Timer A capture/compare module1 control register lower byte TACCTL1L
Reset value0x00
7
6
5
4
3
2
1
0
TACCR1_SCS
TACCR1_OUTMODE[2:0]
TACCR1_IE TACCR1_OUT TACCR1_COV TACCR1_IFG
Name
Decription
Set to 0, the selected capture source is not be synchronized with the system clock.
7
TACCR1_SCS
Set to 1, the selected capture source is synchronized with the system clock.
Output mode selection:
3’b000, direct output mode.
3’b001, set output mode.
3’b010, reverse/reset output mode.
3’b011, set/reset output mode;
6:4 TACCR1_OUTMODE 3’b100, reverse output mode.
3’b101, reset output mode.
3’b110, reverse /set output mode.
3’b111, reset /set output mode.
Note: The function is explained in detail in the Section TimerA / B in CMT16xA User
Guide.
Type R/W
R/W
Rev 0.6 | 45/102
AN286
Name
Decription
Type
3
TACCR1_IE
TimerA capture/compare module 1 interrupt enabling bit.
R/W
Can only be used in output mode 0 (TACCR1_OUTMODE=0), get through directly to
2
TACCR1_OUT
R/W
the corresponding output signal.
Capture overflow flag. Reading as 1 means that the previous capture source
1
TACCR1_COV
triggering result is not read yet, the current trigger source is captured currently, and
R/W
software clearing is required.
0
TACCR1_IFG
TimerA capture/compare 1 interrupt flag
R/W
TACCR2H/TACCR2L, TimerA capture/compare module 2 register
TACCR2H & TACCR2L
7
6
5
4
3
2
H
TACCR2[15:8]
L
TACCR2[7:0]
Reset value0x00, 0x00
1
0
Name TACCR2
Decription TimerA capture/compare module 2 register, in compare mode, saves the data that TACNT needs to compare with. In capture mode, saves the count value of Timer A upon successful capture.
Type R/W
TACCTL2H, Timer A capture/compare module 2 control register higher byte
TACCTL2H
7
6
5
4
3
2
1
Reserved TACCR2_CCI TACCR2_SCCI
TACCR2_CM[1:0]
TACCR2_CCIS[1:0]
Reset value0x40 0
TACCR2_CAP
Name
Decription
6
TACCR2_CCI The value of the selected capture source, which can be read by the software.
When EQUx is valid, the selected captured value is stored and can be read by the
5
TACCR2_SCCI
software.
Capture mode selection.
2’b00, not captured.
4:3
TACCR2_CM 2’b01, capture the rising edge.
2’b10, capture the falling edge.
2’b11, capture double edges.
Capture source selection.
2’b00, TACCI0.
2’b01, TACCI1. 2:1 TACCR2_CCIS
2’b10, TACCI2.
2’b11, TACCI3. Among them, TACCI0 and TACCI1 are from GPIO mapping (see
TACCI_SEL register), TACCCI2 and TACCI3 are from register (see TACHregister).
Set to 0, select the comparison mode.
0
TACCR2_CAP
Set to 1, select the capture mode.
Type R R
R/W
R/W
R/W
Rev 0.6 | 46/102
AN286
TACCTL2L, Timer A capture/compare module 2 control register lower byte
TACCTL2L
7
6
5
4
3
2
TACCR2_SCS
TACCR2_OUTMODE[2:0]
TACCR2_IE TACCR2_OUT
Reset value0x00
1
0
TACCR2_COV TACCR2_IFG
Name
Decription
Set to 0, the selected capture source is not be synchronized with the system clock.
7
TACCR2_SCS
Set to 1, the selected capture source is synchronized with the system clock.
Output mode selection:
3’b000, direct output mode.
3’b001, set output mode.
3’b010, reverse/reset output mode.
3’b011, set/reset output mode;
6:4 TACCR2_OUTMODE 3’b100, reverse output mode.
3’b101, reset output mode.
3’b110, reverse /set output mode.
3’b111, reset /set output mode.
Note: The function is explained in detail in the Section TimerA / B in CMT16xA User
Guide.
3
TACCR2_IE
TimerA capture/compare module 2 interrupt enabling bit.
Can only be used in output mode 0 (TACCR1_OUTMODE=0), get through directly to
2
TACCR2_OUT
the corresponding output signal.
Capture overflow flag. Reading as 1 means that the previous capture source triggering
1
TACCR2_COV
result is not read yet, the current trigger source is captured currently, and software
clearing is required.
0
TACCR2_IFG
TimerA capture/compare 2 interrupt flag
Type R/W
R/W
R/W R/W R/W R/W
TACCI_SEL, TimerA input signal Selection
TACCI_SEL
7
6
5
4
TACCI1_GPIO_SEL [3:0]
Reset value0x00
3
2
1
0
TACCI0_GPIO_SEL[3:0]
Name TACCI0_GPIO_SEL[3:0] TACCI1_GPIO_SEL[3:0]
Decription TACCI0 input signal mapping to GPIO[15:0] TACCI1 input signal mapping to GPIO[15:0]
Type R/W R/W
Notes: TACCI0 and TACCI1 input signals are mapped as follows. 4’b0000,
corresponding to GPIO0, namely A0 pin. 4’b0001, corresponding to GPIO1,
namely, A1 pin. … 4’b0111, corresponding to GPIO7, namely A7 pin. 4’b1000,
corresponding to GPIO8, namely B0 pin. 4’b1001, corresponding to GPIO9, namely
B1 pin. …
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AN286
4’b1111, corresponding to GPIO15, namely B7 pin.
TBCLK_DIV, TimerB clock source frequency division register
TBCLK_DIV_H & TBCLK_DIV_L
7
6
5
4
3
2
H
TBCLK_DIV[15:8]
L
TBCLK_DIV[7:0]
Reset value0x00, 0x00
1
0
Name TBCLK_DIV
Decription TimerB clock source division factor. TBCLK = FPCLK / TBCLK_DIV, FPCLK is the system clock, the default is 24 MHz. The TBCLK_DIV range is 1 ~ 65535.
Type R/W
TBCH, TimerB control register higher byte
TBCH
7
6
5
4
Reserved
Reserved
Reserved
Reserved
3 Reserved
2 TB_START
1 TBCCI3
Reset value0x00 0
TBCCI2
Name
Decription
TimerB enabling bit.
2
TB_START Set to 1 to enable the TimerB module.
Set to 0 to disable the TimerB module;
1
TBCCI3 Software configurable capture source input 3
0
TBCCI2 Software configurable capture source input 2
Type
R/W
R/W R/W
TBCL, TimerB control register lower byte
TBCL
7
6
5
4
3
Reserved
Reserved
Reserved
TB_CNT_MODE[1:0]
2 TB_CLR
1 TMRB_IE
Reset value0x00 0
TMRB_IFG
Name
Decription
Type
TimerB counting mode selection.
2’b00, stop mode, namely TimerB stoping count mode.
4:3 TB_CNT_MODE 2’b01, count up mode, namely TimerB up counting mode.
R/W
2’b10, continuous mode, namely TimerB continuous counting mode.
2’b11, up/down mode, namely TimerB up and down counting mode.
TimerB clearing control bit.
2
TB_CLR
When set to 1, resets TBCNT, count direction,TBCLK_DIV_H, TBCLK_DIV_L, and R/W
other TimerB related registers except registerTBCH/TBCL.
1
TMRB_IE
TimerB interrupt enabling bit. When set to 1, run TimerB count interrupt request
R/W
TimerB count interrupt flag, which is set to 1 when the TBCNT count returns to 0
0
TMRB_IFG
R/W
again.
Rev 0.6 | 48/102
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AN286
TBCNT_H/TBCNT_L, TimerB realtime count register
TBCNT_H & TBCNT_L
7
6
5
4
3
2
H
TBCNT[15:8]
L
TBCNT[7:0]
Reset value0x00, 0x00
1
0
Name TBCNT
Decription TimerB real-time count value, read-only register, can be cleared by TB_CLR
Type R
TBCCR0H/TBCCR0L, TimerB capture/compare module 0 register
TBCCR0H & TBCCR0L
7
6
5
4
3
2
H
TBCCR0[15:8]
L
TBCCR0[7:0]
Reset value0x00, 0x00
1
0
Name TBCCR0
Decription TimerB capture/compare module 0 register. In compare mode, it saves the data that TBCNT needs to compare with. In capture mode, it saves the count value of Timer B opun successful capture.
Type R/W
TBCCTL0H, TimerB capture/compare module 0 control register higher byte
TBCCTL0H
Reset value0x40
7
6
5
4
3
2
1
0
Reserved
TBCCR0_CCI TBCCR0_SCCI
TBCCR0_CM[1:0]
TBCCR0_CCIS[1:0]
TBCCR0_CAP
Name
Decription
Type
6
TBCCR0_CCI The value of the selected capture source, which can be read by the software.
R
When EQUx is valid, the selected captured value is stored and can be read by the
5
TBCCR0_SCCI
R
software;
Capture mode selection.
2’b00, not captured.
4:3
TBCCR0_CM 2’b01, capture the rising edge.
R/W
2’b10, capture the falling edge.
2’b11, capture both edges.
Capture source selection.
2’b00, TBCCI0.
2’b01, TBCCI1.
2:1 TBCCR0_CCIS 2’b10, TBCCI2.
R/W
2’b11, TBCCI3.
Among them, TBCCI0 and TBCCI1 are from GPIO mapping (see TBCCI_SEL register),
TBCCCI2 and TBCCI3 are from register (see TBCH register).
Set to 0 to select the compare mode.
0
TBCCR0_CAP
R/W
Set to 1, select the capture mode.
Rev 0.6 | 49/102
AN286
TBCCTL0L, TimerB capture/compare module 0 control register lower byte
TBCCTL0L
7
6
5
4
3
2
TBCCR0_SCS
TBCCR0_OUTMODE[2:0]
TBCCR0_IE TBCCR0_OUT
Reset value0x00
1
0
TBCCR0_COV TBCCR0_IFG
Name
Decription
Type
Set to 0, the selected capture source is not synchronized with the system clock.
7
TBCCR0_SCS
R/W
Set to 1, the selected capture source is synchronized with the system clock.
Output mode selection:
3’b000, direct output mode.
3’b001, set output mode.
3’b010, reverse/reset output mode.
3’b011, set/reset output mode;
6:4 TBCCR0_OUTMODE 3’b100, reverse output mode.
R/W
3’b101, reset output mode.
3’b110, reverse /set output mode.
3’b111, reset /set output mode.
Note: The function is explained in detail in the Section TimerA / B in CMT16xA User
Guide.
3
TBCCR0_IE
TimerB capture/compare module 0 interrupt enabling bit
R/W
Can only be used in output mode 0 (TBCCR0_OUTMODE=0), get through directly
2
TBCCR0_OUT
R/W
to the corresponding output signal
Capture overflow flag. Reading as 1 means that the previous capture source
1
TBCCR0_COV
triggering result is not read yet, the current trigger source is captured currently, and R/W
software clearing is required.
0
TBCCR0_IFG
TimerB capture/compare 0 interrupt flag.
R/W
TBCCR1H/TBCCR1L, TimerB capture/compare module 1 register
TBCCR1H & TBCCR1L
7
6
5
4
3
2
H
TBCCR1[15:8]
L
TBCCR1[7:0]
Reset value0x00, 0x00
1
0
Name TBCCR1
Decription TimerB capture/compare module 1 register. In compare mode, it saves the data that TACNT needs to compare with. In capture mode, it saves the count value of Timer B upon successful capture.
Type R/W
Rev 0.6 | 50/102
AN286
TBCCTL1H, TimerB capture/compare module 0 control register higher byte TBCCTL1H
Reset value0x40
7
6
5
4
3
2
1
0
Reserved TBCCR1_CCI TBCCR1_SCCI
TBCCR1_CM[1:0]
TBCCR1_CCIS[1:0]
TBCCR1_CAP
Name
Decription
Type
6
TBCCR1_CCI The value of the selected capture source, which can be read by the software.
R
When EQUx is valid, the selected captured value is stored and can be read by
5
TBCCR1_SCCI
R
software.
Capture mode selection.
2’b00, not captured.
4:3
TBCCR1_CM 2’b01, capture the rising edge.
R/W
2’b10, capture the falling edge.
2’b11, capture both edges.
Capture source selection.
2’b00, TACCI0.
2’b01, TACCI1.
2:1
TBCCR1_CCIS 2’b10, TACCI2.
R/W
2’b11, TACCI3.
Among them, TACCI0 and TACCI1 are from GPIO mapping (see
TACCI_SELregister), TACCCI2 and TACCI3 are from register (see TACHregister);
Set to 0 to select the comparison mode.
0
TBCCR1_CAP
R/W
Set to 1, select the capture mode.
TBCCTL1L, TimerB capture/compare module 1 control register lower byte
TBCCTL1L
7
6
5
4
3
2
TBCCR1_SCS
TBCCR1_OUTMODE[2:0]
TBCCR1_IE TBCCR1_OUT
Reset value0x00
1
0
TBCCR1_COV TBCCR1_IFG
Name
Decription
Type
Set to 0, the selected capture source is not synchronized with the system clock.
7 TBCCR1_SCS
R/W
Set to 1, the selected capture source is synchronized with the system clock.
Output mode selection:
3’b000, direct output mode.
3’b001, set output mode.
3’b010, reverse/reset output mode.
TBCCR1_OUT 3’b011, set/reset output mode;
6:4
R/W
MODE
3’b100, reverse output mode.
3’b101, reset output mode.
3’b110, reverse /set output mode.
3’b111, reset /set output mode.
Note: The function is explained in detail in the Section TimerA / B in CMT16xA User Guide.
3
TBCCR1_IE TimerB capture/compare module 1 interrupt enabling bit
R/W
Can only be used in output mode 0 (TACCR1_OUTMODE=0), get through directly to the
2 TBCCR1_OUT
R/W
corresponding output signal
Capture overflow flag. Reading as 1 means that the previous capture source triggering
1 TBCCR1_COV
R/W
result is not read yet, the current trigger source is captured currently, and software clearing
Rev 0.6 | 51/102
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AN286
Name
is required.
Decription
0
TBCCR1_IFG TimerB capture/compare 1 interrupt flag.
Type R
TBCCR2H/TBCCR2L, TimerB capture/compare module 2 register
TBCCR2H & TBCCR2L
7
6
5
4
3
2
H
TBCCR2[15:8]
L
TBCCR2[7:0]
Reset value0x00, 0x00
1
0
Name TBCCR2
Decription TimerB capture/compare module 2 register. In compare mode, saves the data that TACNT needs to compare with. In capture mode, saves the count value of Timer B upon successful capture.
Type R/W
TBCCTL2H, TimerB capture/compare module 2 control register higher byte
TBCCTL2H
7
6
5
4
3
2
1
Reserved TBCCR2_CCI TBCCR2_SCCI
TBCCR2_CM[1:0]
TBCCR2_CCIS[1:0]
Reset value0x40 0
TBCCR2_CAP
Name
Decription
Type
6
TBCCR2_CCI The selected capture source value. Can be read by the software.
R
5
TBCCR2_SCCI When EQUx is valid, it saves the selected capture value. Can be read by the software.
R
Capture mode selection.
2’b00, not capture
4:3
TBCCR2_CM 2’b01, capture on the rising edge.
R/W
2’b10, capture on the falling edge.
2’b11, capture on both edges.
Capture source selection.
2’b00, TBCCI0.
2’b01, TBCCI1.
2’b10, TBCCI2.
2:1
TBCCR2_CCIS
R/W
2’b11, TBCCI3.
Among them, TBCCI0 and TBCCI1 come from GPIO mapping ( see
TACCI_SELregister for details). TBCCCI2 and TBCCI3 come from register See
TBCHregister for details.
Set to 0 to select the comparison mode.
0
TBCCR2_CAP
R/W
Set to 1, select the capture mode.
Rev 0.6 | 52/102
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AN286
TBCCTL2L, Timer B capture/compare module2 control register lower byte
TBCCTL2L
7
6
5
4
3
2
TBCCR2_SCS TBCCR2_OUTMODE[2:0]
TBCCR2_IE
TBCCR2_OUT
Reset value0x00
1
0
TBCCR2_COV TBCCR2_IFG
Name
Decription
Set to 0, the selected capture source is not be synchronized with the system
clock. 7 TBCCR2_SCS
Set to 1,the selected capture source is synchronized with the system clock
Output mode selection:
Type R/W
3’b000, direct output mode.
3’b001, set output mode.
3’b010, reverse/reset output mode.
TBCCR2_OUT 3’b011, set/reset output mode;
6:4
R/W
MODE
3’b100, reverse output mode.
3’b101, reset output mode.
3’b110, reverse /set output mode.
3’b111, reset /set output mode.
Note: The function is explained in detail in the Section TimerA / B in CMT16xA User Guide.
3
TBCCR2_IE TimerB capture/compare module 2 interrupt enabling bit
R/W
Can only be used in output mode 0TBCCR2_OUTMODE=0,pass directly to the
2 TBCCR2_OUT
R/W
corresponding output signal
Capture overflow flag. Reading as 1 means that the previous capture source triggering
1 TBCCR2_COV result is not read yet, the current trigger source is captured currently, and software clearing R/W
is required.
0 TBCCR2_IFG TimerB capture/compare 2 interrupt flag
R/W
TBCCI_SEL, TimerB input signal selection
TBCCI_SEL
7
6
5
4
TBCCI1_GPIO_SEL [3:0]
Reset value0x00
3
2
1
0
TBCCI0_GPIO_SEL[3:0]
Name TBCCI0_GPIO_SEL[3:0] TBCCI1_GPIO_SEL[3:0]
Decription TBCCI0 input signal mapping to GPIO[15:0] TBCCI1 input signal mapping to GPIO[15:0]
Type R/W R/W
Notes: Timer1 external input signal selection. Can map to GPIO[15:0]. 4’b0000,
corresponding to GPIO0, namely A0 pin. 4’b0001, corresponding to GPIO1, namely
A1 pin. …… 4’b01114’b0001, corresponding to GPIO7, namely A7 pin. 4’b1000,
corresponding to GPIO8, namely A8 pin. 4’b1001, , corresponding to GPIO9,
namely A9 pin. …… 4’b1111, , corresponding to GPIO15, namely B7 pin.
Rev 0.6 | 53/102
AN286
3.10 3D Low-frequency Wakeup Register Set
Table 11. 3D Low-frequency Wakeup Register Set
Name CUS_LFRX3 CUS_LFRX4 CUS_LFRX5 CUS_LFRX6 CUS_LFRX7 CUS_LFRX8 CUS_LFRX9
CUS_LFRX10 CUS_LFRX11 CUS_LFRX12 CAL_LFRX_TCAP2
CAL_LFRX_TCAP1
CAL_LFRX_TCAP0 CAL_LFRX_OSC_CODE
CUS_SYSCTL3 CUS_SYSCTL4 CUS_SYSCTL5
CUS_SYSCTL6
CUS_SYSCTL7
CUS_SYSCTL8 CUS_SYSCTL9 CUS_SYSCTL10 CUS_LFRX15 CUS_LFRX16 CUS_LFRX17
CUS_LFRX18
CUS_LFRX19
CUS_LFRX20
CUS_LFRX21
CUS_LFRX22
CUS_LFRX23
Storage Area Block0 Block0 Block0 Block0 Block0 Block0 Block0 Block0 Block0
Block0 Block0
Block0
Block0 Block0 Block0 Block0 Block0
Block0
Block0
Block0 Block0 Block0 Block0 Block0 Block0
Block0
Block0
Block0
Block0
Block0
Block0
Sub-area ————
—
——
—
—
——-
—
—
—
—
—
—
Address Reset
Function
0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x34
0x35
0x36 0x37 0x50 0x51 0x52
0x53
0x54
0x55 0x56 0x57 0x58 0x59 0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x2A 0x55 0x8F 0xFE 0x61 0xB3 0xE4 0xEF 0x15 0x13 0x10
0x10
0x10 0x00 0x00 0x01 0x00
0x00
0x00
0x10 0x29 0x00 0x72 0xAD 0x59
0x5A
0xA5
0x00
0x23
0x00
0x00
Low-frequency wakeup configuration register3 Low-frequency wakeup configuration register4 Low-frequency wakeup configuration register5 Low- frequency wakeup configuration register6 Low-frequency wakeup configuration register7 Low-frequency wakeup configuration register8 Low-frequency wakeup configuration register9 Low-frequency wakeup configuration register10 Low- frequency wakeup configuration register11 Low-frequency wakeup configuration register12 Low-frequency wakeup Internal matching capacitor register2 (Z-axis antenna) Low-frequency wakeup Internal matching capacitor register1 (Y-axis antenna) Low-frequency wakeup Internal matching capacitor register0 (X-axis antenna) NA System control register3 System control register4 System control register5, low-frequency receiving duty-cycle receiving T1 setting System control register6, low- frequency receiving duty-cycle receiving T2 setting System control register7, low-frequency receiving duty-cycle sleepint time setting 1 Low- frequency receiving duty-cycle sleepint time setting 2 System control register9 System control register10, Low- frequency receiving manual control state register Low-frequency wakeup configuration register15 Low- frequency wakeup configuration register16 Low-frequency wakeup configuration register17, SyncValue[7:0] Low-frequency wakeup configuration register18, SyncValue[15:8] Low-frequency wakeup configuration register19, SyncValue[23:16] Low-frequency wakeup configuration register20, SyncValue[31:24] Low-frequency wakeup configuration register21, WakeupID[7:0] Low-frequency wakeup configuration register22, WakeupID[15:8] Low-frequency wakeup configuration register23, WakeupID[23:16]
Rev 0.6 | 54/102
AN286
Name
CUS_LFRX24
CUS_LFRX25 CUS_LFRX26
CUS_LFRX27
CUS_LFRX28 CUS_LFRX29 CUS_LFRX30 CUS_SYSCTL11 CUS_SYSCTL12 CUS_SYSCTL18
CUS_LFRX31 CUS_LFRX32 CUS_LFRX33 CLK_SYS_DIV
LFRX_IF_TH_H
LFRX_IF_TH_L
Storage Area
Block0
Block0 Block0
Block0
Block0 Block0 Block0 Block0 Block0 Block0 Block0 Block0 Block0 Block1
Block1
Block1
Sub-area
—
—
—
———Bank0
Bank1
Bank1
Address Reset
Function
0x61
0x62 0x63
0x64
0x65 0x66 0x67 0x68 0x69 0x6F 0x72 0x73 0x74 0x8F
0xC1
0xC3
0x00
0x1C 0x50
0x31
0x7C 0x65 0x1E 0x80 0x00 0x00 0x00 0x00 0x00 0x00
0x00
0x7D
Low-frequency wakeup configuration register24, WakeupID[31:24] Low-frequency wakeup configuration register25 Low-frequency wakeup configuration register26 Low-frequency wakeup configuration register27, low-frequency rate section Low- frequency wakeup configuration register28 Low-frequency wakeup configuration register29 Low-frequency wakeup configuration register30 System control register11 System control register12 System control register18 Low-frequency wakeup configuration register31 Low-frequency wakeup configuration register32 Low-frequency wakeup configuration register33 System clock division register Calibration frequency output capturing channel selection Target frequency of Calibration
CUS_LFRX3 register
CUS_LFRX3
7
6
5
4
3
PD_P25
PD_P50
LFRX_AGC_IN[1:0]
Reset value0x3F
2
1
0
LFRX_AGC_VHREF[3:0]
Name
Decription
5:4
LFRX_AGC_IN
AGC input source select, generated by CMT216xA RFPDK
3:0 LFRX_AGC_VHREF AGC reference upper threshold, generated by CMT216xA RFPDK
Type R/W R/W
CUS_LFRX4 register
CUS_LFRX4
7
6
5
4
3
Reserved PD_PULLUP2 LFRX_AGC_CNT[1:0]
Reset value0x68
2
1
0
LFRX_AGC_VLREF[3:0]
Name
Decription
Type
AGC detection count related to threshold, automatically generated by CMT216xA
5:4 LFRX_AGC_CNT
R/W
RFPDK.
3:0 LFRX_AGC_VLREF AGC reference upper threshold, automatically generated by CMT216xA RFPDK
R/W
Rev 0.6 | 55/102
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AN286
CUS_LFRX5 register
CUS_LFRX5
7
6
LFRX_CADET_WIN[1:0]
5
4
LFRX_CADET_OK_CNT[1:0]
3
2
LFRX_PEAKDET_CLK[1:0]
Reset value0x8F
1
0
LFRX_DATA_CLK[1:0]
Name
Decription
Type
Related to carrier frequency detection time window, automatically generated by
7:6
LFRX_CADET_WIN
R/W
CMT216xA RFPDK
Related to carrier frequency detection time window, automatically generated by
5:4 LFRX_CADET_OK_CNT
R/W
CMT216xA RFPDK.
Related to carrier frequency detection time window, automatically generated by
3:2
LFRX_PEAKDET_CLK
R/W
CMT216xA RFPDK.
Demodulation data filter related configuration, automatically generated by
1:0
LFRX_DATA_CLK
R/W
CMT216xA RFPDK.
CUS_LFRX6 register
CUS_LFRX6
7
6
LFRX_DATA_R0[1:0]
5
4
LFRX_DATA_R1[1:0]
3
2
LFRX_PEAKDET_C[1:0]
Reset value0xFE
1
0
Reserved
Name
Decription
Type
Demodulation data filter related configuration, automatically generated
7:6
LFRX_DATA_R0
R/W
by CMT216xA RFPDK.
Demodulation data filter related configuration, automatically generated
5:4
LFRX_DATA_R1
R/W
by CMT216xA RFPDK.
Peak detection related configuration, automatically generated by
3:2
LFRX_PEAKDET_C
R/W
CMT216xA RFPDK.
CUS_LFRX7 register
CUS_LFRX7
Reset value0x61
7
6
5
4
3
2
1
0
LFRX_DATA_C1[3:0]
LFRX_DATA_C0[3:0]
Name
Decription
Type
Demodulation data filter related configuration, automatically generated
7:4
LFRX_DATA_C1
R/W
by CMT216xA RFPDK.
Demodulation data filter related configuration, automatically generated
3:0
LFRX_DATA_C0
R/W
by CMT216xA RFPDK.
CUS_LFRX8 register
CUS_LFRX8
Reset value0xB3
7
6
5
4
3
2
1
0
LFRX_DATA_C3[3:0]
LFRX_DATA_C2[3:0]
Name
Decription
Type
Demodulation data filter related configuration, automatically generated by
7:4
LFRX_DATA_C3
R/W
CMT216xA RFPDK.
Rev 0.6 | 56/102
AN286
Name
Decription
Type
Demodulation data filter related configuration, automatically generated by
3:0
LFRX_DATA_C2
R/W
CMT216xA RFPDK.
CUS_LFRX9 register
CUS_LFRX9
7
6
LFRX_CMP_NOISE_MASK LFRX_CMP_SW
5
4
3
LFRX_RSSIAMP_IBIAS[2:0]
Reset value0xE4
2
1
0
LFRX_PGA_IBIAS[2:0]
Name
Decription
Related to carrier frequency detection threshold configuration, automatically
7
LFRX_AGC_CNT
generated by CMT216xA RFPDK.
Related to carrier frequency detection threshold configuration, automatically
6
LFRX_AGC_VLREF
generated by CMT216xA RFPDK.
Related to signal link power configuration configuration, automatically 5:3
LFRX_RSSIAMP_IBIAS
generated by CMT216xA RFPDK.
Signal link power configuration related configuration, automatically
2:0
LFRX_PGA_IBIAS
generated by CMT216xA RFPDK.
Type R/W R/W R/W R/W
CUS_LFRX10 register
CUS_LFRX10
7
6
5
LFRX_CMP_REF[3:0]
Reset value0xEF
4
3
2
1
0
LFRX_DEMOD_TH_HOLD
LFRX_RSSIREC_IBIAS[2:0]
Name
Decription
Type
Related to carrier frequency detection threshold, automatically generated
7:4
LFRX_CMP_REF
R/W
by CMT216xA RFPDK.
3
LFRX_DEMOD_TH_HOLD NA, fixed to 1.
R/W
Related to signal link power configuration, automatically generated by
2:0
LFRX_RSSIREC_IBIAS
R/W
CMT216xA RFPDK.
CUS_LFRX11 register
CUS_LFRX11
7
6
5
4
3
LFRX_SNRDET_INVALID_WIN[1:0] LFRX_SNRDET_VALID_WIN[1:0]
Reset value0x15
2
1
0
LFRX_SNRDET_SNR[3:0]
Name
Decription
SNR detection, invalid-window setting, automatically generated 7:6
LFRX_SNRDET_INVALID_WIN
by CMT216xA RFPDK.
SNR detection, effective-window setting, automatically generated
5:4
LFRX_SNRDET_VALID_WIN
by CMT216xA RFPDK.
SNR detection, signal-to-noise ratio setting, automatically
3:0
LFRX_SNRDET_SNR
generated by CMT216xA RFPDK.
Type R/W R/W R/W
Rev 0.6 | 57/102
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CUS_LFRX12 register
CUS_LFRX12
7
6
5
LFRX_MEAS_SOURCE LFRX_OSC_VREF[1:0]
4 LFRX_CH_Z
3 LFRX_CH_Y
2 LFRX_CH_X
Reset value0x03
1
0
LFRX_STARTUP_MANUAL[1:0]
Name
Decription
Type
Related to RSSI measurement, automatically generated by CMT216xA
7
LFRX_MEAS_SOURCE
R/W
RFPDK
6:5
LFRX_OSC_VREF
Internal parameter, automatically generated by CMT216xA RFPDK
R/W
4
LFRX_CH_Z
In normal mode, channel Z enabling control. Set to 1 to enable.
R/W
3
LFRX_CH_Y
In normal mode, channel Y enabling control. Set to 1 to enable.
R/W
2
LFRX_CH_X
In normal mode, channel X enabling control. Set to 1 to enable.
R/W
1:0 LFRX_STARTUP_MANUAL Internal parameter, users can ignore it. The default value is 3.
R/W
CUS_LFRX_TCAP2 register
CUS_LFRX_TCAP2
7
6
5
4
Reserved Reserved Reserved
3
2
1
LFRX_TCAP_Z[4:0]
Reset value0x10 0
Name
Decription
Low-frequency wakeup tuning load capacitance in Z-axls antenna, ranging
4:0
LFRX_TCAP_Z
from 0 to 31 with 1.2 pF/Step.
Type R/W
CUS_LFRX_TCAP1 register
CUS_LFRX_TCAP1
7
6
5
4
Reserved Reserved Reserved
3
2
1
LFRX_TCAP_Y[4:0]
Reset value0x10 0
Name
Decription
Type
Low-frequency wakeup tuning load capacitance in Y-axls antenna, ranging
4:0
LFRX_TCAP_Y
R/W
from 0 to 31 with 1.2 pF/Step.
CUS_LFRX_TCAP0 register
CUS_LFRX_TCAP0
7
6
5
4
Reserved Reserved Reserved
3
2
1
LFRX_TCAP_X[4:0]
Reset value0x10 0
Name
Decription
Type
Low-frequency wakeup tuning load capacitance in X-axls antenna, ranging from
4:0
LFRX_TCAP_X
R/W
0 to 31 with 1.2 pF/Step.
Rev 0.6 | 58/102
AN286
CUS_LFRX_OSC_CODE register
CUS_LFRX_TCAP0
7
6
5
Reserved
4
3
2
LFRX_OSC_IBIAS[6:0]
Reset value0x00
1
0
Name
Decription
Internal parameter. The configuration value is generated by CMT216xA
6:0
LFRX_OSC_IBIAS
RFPDK.
Type R/W
CUS_SYSCTL3 register
CUS_SYSCTL3
7 LED_I
NV
6 AFEIR
EN
5 SNOOZE_
EN
4 SNOOZE_DEBU
G_EN
3 LFRX_DEBUG
_EN
2 LFRX_
EN
Reset value0x00
1 SLPT_WAKEUP_M
ODE
0 SLEEP_TIMER
_EN
Name
Decription
Type
Low-frequency wakeup module simulating mode enabling.
Set to 0 to disable the low frequency module simulating mode.
3
LFRX_DEBUG _EN
R/W
Set to 1 to enable the low frequency mode simulating mode (used when
performing online debugging).
Low frequency wake-up module enabling control.
2
LFRX_EN
Set to 0 to disable the low-frequency wakeup module.
R/W
Set to 1 to enable the low-frequency wakeup module.
Rev 0.6 | 59/102
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AN286
CUS_SYSCTL4 register
CUS_SYSCTL4
7
6
LFRX_MODE
[1:0]
5 LFRX_SIGNAL_OK
_TYPE
4
3
LFRX_TIMER_EXTEND_M
ODE[1:0]
2 DUTY_CYCLE_M
ETHOD
Reset value0x01
1 LFRX_DUTY_CYC
LE_EN
0 ALWAYS_L
FRX
Name
Decription
Type
Low-frequency wakeup mode selection.
2’b00, LFRX_WAKEUP is only used to wake up the core.
2’b01, LFRX_WAKEUP is only used to wake up the external MCU, and
7:6
LFRX_MODE
the internal MCU can be uses asother functions.
R/W
2’b10, LFRX_WAKEUP is only used to wake up the external MCU, the
internal MCU is not used.
2’b11, invalid configuration, unavailable.
Low-frequency signal detection method.
5
LFRX_SIGNAL_OK_TYPE Set to 0, use carrier (carrier duration) detection mode.
R/W
Set to 1, use signal to noise ratio (SNR) detection mode.
In low-frequency duty cycle delay mode, the condition selection for T1
time being extended to T2 (pre-condition is DUTY_CYCLE_METHOD=0).
2’b00, signal detection being satisfied (lfrx_signal_ok).
4:3 LFRX_TIMER_EXTEND_MODE
R/W
2’b01, sync word matching (sync_pass).
2’b10, wakeup ID matching (wkid_pass.;
2’b11, signal strength being satisfied (dbmdet_ok).
Low-frequency receiving duty cycle mode selection (pre-condition is
LFRX_DUTY_CYCLE_EN=1)
Set to 0, adopt automatic delay mode (need to set T1 and T2 for low-
2
DUTY_CYCLE_METHOD
R/W
frequency receiving).
Set to 1, adopt fixed duty cycle mode (only need to set T1 for
low-frequency receiving)
Set to 0, disable the duty cycle mode of low frequency receiving.
1
LFRX_DUTY_CYCLE_EN
R/W
Set to 1, enable the duty cycle mode of low frequency receiving.
Set to 0, adopt non-long-receiving mode for low-frequency receiving.
0
ALWAYS_LFRX
R/W
Set to 1, adopt long-receiving mode for low-frequency receiving.
CUS_SYSCTL5 register
CUS_SYSCTL5
7
6
5
4
3
LFRX_TIMER_M_RX_T1[4:0]
Reset value0x00
2
1
0
LFRX_TIMER_R_RX_T1[2:0]
7:3 2:0 Notes:
Name LFRX_TIMER_M_RX_T1 LFRX_TIMER_R_RX_T1
Decription In low-frequency receiving duty cycle mode, receive the M value of the T1 window with a configuration range of 0-31. In low-frequency receiving duty cycle mode, receive the R value of the T1 window with a configuration range of 0-7.
Type R/W R/W
1. The T1 window of low-frequency receiving duty cycle mode meets the below calculation formular.
Rev 0.6 | 60/102
AN286
1 = × 2(+1) × 500 In above, M is the value of LFRX_TIMER_M_RX_T1R is the value of LFRX_TIMER_R_RX_T1. 500 us corresponds to the internal 32 kHz clock. When external 32.768 kHz crystal oscillator is used, the time unit is 488 us.
CUS_SYSCTL6 register
CUS_SYSCTL6
7
6
5
4
3
LFRX_TIMER_M_RX_T2[4:0]
Reset value0x00
2
1
0
LFRX_TIMER_R_RX_T2[2:0]
Name
Decription
In low-frequency receiving duty cycle mode, receive the M value of the T2 7:3
LFRX_TIMER_M_RX_T2
window with a configuration range of 0-31.
In low-frequency receiving duty cycle mode, receive the R value of the T2 2:0
LFRX_TIMER_R_RX_T2
window with a configuration range of 0-7.
Notes:
Type R/W R/W
1. The T2 window of low-frequency receiving duty cycle mode meets the below calculation formular.
2 = × 2(+1) × 500 In above, M is the value of LFRX_TIMER_M_RX_T2R is the value
of LFRX_TIMER_R_RX_T2. 500 us corresponds to the
internal 32 kHz clock. When external 32.768 kHz crystal oscillator is used,
the time unit is 488 us.
CUS_SYSCTL7 register
CUS_SYSCTL7
7
6
5
4
3
2
LFRX_TIMER_M_SLEEP[7:0]
Reset value0x00
1
0
7:0 Notes:
Name LFRX_TIMER_M_SLEEP
Decription In low-frequency receiving duty cycle mode, the M value of the sleep window with a configuration range of 0-255.
Type R/W
1. The sleep window of low-frequency receiving duty cycle mode meet the below calculation formular. = × 2(+1) × 500
In above, M is the value of LFRX_TIMER_M_SLEEP, R is the value of LFRX_TIMER_R_SLEEP. 500 us corresponds to the internal 32 kHz clock. When external 32.768 kHz crystal oscillator is used, the time unit is 488 us.
Rev 0.6 | 61/102
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AN286
CUS_ SYSCTL8 register
CUS_SYSCTL8
Reserved
6
5
Reserved LFRX_WAKEUP_AUTOCLR_DIS
4
3
LFRX_WAKEUP_MODE[1:0]
Reset value0x10
2
1
0
LFRX_TIMER_R_SLEEP[2:0]
5
4:3 2:0 Notes:
Name LFRX_WAKEUP_AUTOCLR_DIS
LFRX_WAKEUP_MODE LFRX_TIMER_R_SLEEP
Decription After LFRX_WAKEUP is valid, namely, wakeup is valid, the signal_ok auto-clear function is automatically disabled. Set to 0, once the set time window of Signal_Ok Auto Clear Time is met, automatic clearing will be performed immediately, and it will return from Decode state to Listen state; Set to 1, that is, namely the MCU is wakened, the function of automatically clearing signal_ok is immediately disabled, and let the MCU set the clearing signal LFRX_MANU_CLR to 1 at an appropriate time. If the MCU is not woken up yet, the automatic clearing function is always effective. Mode selection for low-frequency wakeup. 2’b00, signal detection being satisfied (lfrx_signal_ok). 2’b01, sync word matching (sync_pass). 2’b10, wakeup ID matching (wkid_pass). 2’b11, invalid configuration. The R value of low- frequency receiving duty cycle mode with a configuration range of 0-7.
Type R/W
R/W R/W
The sleep window of low-frequency receiving duty cycle mode meet the below calculation formular.
= × 2(+1) × 500
M is the value of LFRX_TIMER_M_SLEEPR is the value of LFRX_TIMER_R_SLEEP. 500 us corresponds to the internal 32 kHz clock. When external 32.768 kHz crystal oscillator is used, the time unit is 488 us.
CUS_ SYSCTL9 register
CUS_SYSCTL9
7
6
LFRX_RSSI_MEAS_DIS LFRX_DBUF_DIS
5
4
3
LFRX_SNRDET_WIN[2:0]
Reset value0x29
2
1
0
LFRX_MEAS_WIN[2:0]
Name
Decription
Type
7 LFRX_RSSI_MEAS_DIS RSSI measurement related settings. The configurations are generated by RFPDK. R/W
Set to 0, enable data stream output delay fucntion after low-frequency wakeup [1]
6
LFRX_DBUF_DIS
(default);
R/W
Set to 1, disable data stream output delay fucntion after low-frequency wakeup.
5:3
LFRX_SNRDET_WIN SNR detection related settings. The configurations are generated by RFPDK.
R/W
2:0
LFRX_MEAS_WIN
RSSI measurement related settings. The configurations are generated by RFPDK. R/W
Notes: The data stream output delay fucntion after wakeup is required to match the OTP code loading time when waking up, to
Rev 0.6 | 62/102
AN286
make sure the code has been loaded and running upon data stream output (the software can receive from the first data bit correctly). When this feature is enabled, users can set the buffer depth of the delay, namely the delay time (time converted according to the low-frequency data rate).
CUS_ SYSCTL10 register
CUS_SYSCTL10
7
6
5
Reserved Reserved Reserved
4 Reserved
3 Reserved
2 GO_LFRX_DECODE
Reset value0x00
1 GO_LFRX_LISTEN
0 GO_LFSLEEP
Name
Decription
In decode-only mode (namely LFRX_ENABLE_MODE = 1), setting this bit to 1
2
GO_LFRX_DECODE
indicates a jump to (LFRX) DECODE mode.
1
GO_LFRX_LISTEN Setting this bit to 1 indicates a jump to the (LFRX) LISTEN state.
0
GO_LFSLEEP
Setting this bit to 1 indicates a jump to the (LFRX) SLEEP state.
Type R/W R/W R/W
Note: This register provides a manual control of the low-frequency state mode (ie user software control). This manual mode is not recommended for normal use of low frequency module. If users need to manually control the low-frequency module per specific requirements, please contact CMOSTEK engineers.
CUS_LFRX15 register
CUS_LFRX15
7
6
5
LFRX_DBUF_LEGNTH[2:0]
4 LFRX_WKID_EN
3
2
LFRX_WKID_LENGTH[1:0]
Reset value0x72
1
0
LFRX_SYNC_LENGTH[1:0]
Name
Decription
Type
The depth of output delay after wakeup ( precondition is LFRX_DBUF_DIS=0)
7:5 LFRX_DBUF_LENGTH with a range of 0-7. The unit is byte, namely, the conversion of the delay time
R/W
according to the set data rate.
Set to 0, disable ID matching function.
4
LFRX_WKID_EN
R/W
Set to 1, enable ID matching function.
The length selection of matching ID:
2’b00, 1-Byte
3:2 LFRX_WKID_LENGTH 2’b01, 2-Byte
R/W
2’b10, 3-Byte
2’b11, 4-Byte
The length selection of sync word.
2’b00, 1-Byte is valid. LF_SYNC_VALUE[7:0].
1:0 LFRX_SYNC_LENGTH 2’b01, 2-Byte is valid. LF_SYNC_VALUE[15:0].
R/W
2’b10, 3-Byte is valid. LF_SYNC_VALUE[23:0].
2’b11, 4-Byte is valid . LF_SYNC_VALUE[31:0].
Rev 0.6 | 63/102
AN286
CUS_LFRX16 register
CUS_LFRX16
7
6
LFRX_ANT_M
ODE[1:0]
5 LFRXHOLD
RST_SEL
4 LFRXSNRDET
REFIN_SEL
3 LFRX_MAN
_TYPE
2 LFRXWKID
MAN_EN
Reset value0xAD
1 LFRX_DIG_DAT
AOUT_SEL
0 LFRXDATA
MAN_EN
Name
Decription
The mode selection of low-frequency wake-up antenna:
2’b00 and 2’b01, non-scanning antenna modes (X, Y, and Z-axis
7:6
LFRX_ANT_MODE
antennas can be individually enabled and controlled).
2’b10, X and Y-axis scanning antenna pattern.
2’b11, X, Y and Z-axis scanning antenna patterns.
The configuration is generated by RFPDK. Not suggest users
5
LFRX_HOLD_RST_SEL
change them.
The SNR detection related settings. The configuration is generated
4
LFRX_SNRDET_REFIN_SEL
by RFPDK. Not suggest users change them.
The polarity selection when the low-frequency data Manchester
code is valid (LFRX_DATA_MAN_EN=1).
3
LFRX_MAN_TYPE
Set to 0, 01 represents logic 1, and 10 represents logic 0.
Set to 1, 10 represents logic 1, and 01 represents logic 0.
Set to 0, the low-frequency wakeup ID is not encoded (namely adopt
2
LFRX_WKID_MAN_EN
NRZ code by default).
Set to 1, the low-frequency wakeup ID is Manchester coded.
Low-frequency demodulation data stream output stage selection.
Set to 0, the low frequency demodulated data stream is output after
waking up.
1
LFRX_DIG_DATAOUT_SEL
Set to 1, the low frequency demodulated data code stream is output
upon invalid signal detection(carrier detection)
Note: this setting is valid when LFRX_DATAOUT_SEL=0.
Set to 0, the low-frequency payload data is not encoded (namely
0
LFRX_DATA_MAN_EN
adopt NRZ encoding by default).
Set to 1, the low frequency load data is Manchester coded.
Type R/W R/W R/W R/W R/W
R/W
R/W
CUS_LFRX17 – CUS_LFRX20 register set
CUS_LFRX17 – 20
7
6
5
4
3
2
17
LFRX_SYNC_VALUE[7:0]
18
LFRX_SYNC_VALUE[15:8]
19
LFRX_SYNC_VALUE[23:16]
20
LFRX_SYNC_VALUE[31:24]
Reset value0x59, 0x5A, 0xA5, 0x00
1
0
Name LFRX_SYNC_VALUE
Decription Low frequency data sync word configuration value, can configure as 8/16/24/32 Symbols. Note: only the NRZ encoding format is used.
Type R/W
Rev 0.6 | 64/102
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AN286
CUS_LFRX21 – CUS_LFRX24 register set
CUS_LFRX21 – 24
Reset value0x23, 0x00, 0x00, 0x00
7
6
5
4
3
2
1
0
21
LFRX_WKID_VALUE[7:0]
22
LFRX_ WKID _VALUE[15:8]
23
LFRX_ WKID _VALUE[23:16]
24
LFRX_ WKID _VALUE[31:24]
Name LFRX_WKID_VALUE
Decription The low-frequency data wakeup ID configuration value, can configure as 8/16/24/32 bits. Note: Manchester encoding can be used with LFRX_WKID_MAN_EN configuration. NRZ is used by default. If Manchester encoding is used, the above value is the value after Manchester encoding.
Type R/W
CUS_LFRX25 register
CUS_LFRX25
7 LFRX_DATAOUT
_SEL
6 LFRX_DECODE
_SEQ
5 LFRX_SIGNAL_OK_AUTO
CLR_DIS
4 LFRX_AGC
_EN
3 LFRX_AGC_S
TEP
Reset value0x1C
2
1
0
LFRX_AGC_CNT_T
H[2:0]
Name
Decription
Low-frequency demodulation data output mode selection.
7
LFRX_DATAOUT_SEL Set to 0, the output as data rate clock synchronization mode (default).
Set to 1, output as RAW DATA mode.
The matching sequence of wakeup IDs.
6
LFRX_DECODE_SEQ
Set to 0, higher bit data first in (data shift to the left) (default).
Set to 1, lower bit data first in (data shift to the right).
LFRX_SIGNAL_OK_AUTOC Set to 0, enable automatic LFRX_SIGNAL_OK clearing.
5
LR_DIS
Set to 1, disable automatic LFRX_SIGNAL_OK clearing.
Set to 0, disable low-frequency demodulation AGC.
4
LFRX_AGC_EN
Set to 1, enable low-frequency demodulation AGC.
AGC adjustment step selection (when LFRX_AGC_EN=1).
3
LFRX_AGC_STEP
Set to 0, the adjustment step is 3 dB / Step.
Set to 1, the adjustment step is 6 dBm / Step.
2:0
LFRX_AGC_CNT_TH
AGC restoring time. The configuration is generated by RFPDK.
Type R/W
R/W R/W R/W R/W R/W
CUS_LFRX26 register
CUS_LFRX26
Reset value0x50
7
6
5
4
3
2
1
0
LFRX_DQRES[3:0]
LFRX_AGC_MIN_INDEX[3:0]
Name
Decription
Type
Antenna’s Q-factor reducing resistor configuration. The
7:4
LFRX_DQRES
R/W
configuration is generated by RFPDK.
The minimum AGC gain configuration. The configuration is
3:0
LFRX_AGC_MIN_INDEX
R/W
generated by RFPDK.
Rev 0.6 | 65/102
AN286
CUS_LFRX27 register
CUS_LFRX27
7
6
5
LFRX_DR_SEL[3:0]
Reset value0x31
4
3
2
1
0
Reserved LFRX_ENABLE_MODE Reserved LFRX_AGC_START_SEL
Name
Decription
Low-frequency rate selection.
– 4’b1111: 1.00 kbps.
– 4’b1110: 1.07 kbps.
– 4’b1101: 1.14 kbps.
– 4’b1100: 1.23 kbps.
– 4’b1011: 1.33 kbps.
– 4’b1010: 1.45 kbps.
– 4’b1001: 1.60 kbps.
7:4
LFRX_DR_SEL
– 4’b1000: 1.78 kbps.
– 4’b0111: 2.00 kbps.
– 4’b0110: 2.29 kbps.
– 4’b0101: 2.67 kbps.
– 4’b0100: 3.20 kbps.
– 4’b0011: 4.00 kbps (default).
– 4’b0010: 5.33 kbps.
– 4’b0001: 8.00 kbps.
– 4’b0000: cannot be used.
Low-frequency module operating mode.
2
LFRX_ENABLE_MODE
Set to 0, Listen & Decode mode (default).
Set to 1, Decode-only mode.
Low-frequency module AGC startup selection.
0
LFRX_AGC_START_SEL Set to 0, start in Listen mode.
Set to 1, start in Decode mode.
Type
R/W
R/W R/W
CUS_LFRX28 register
CUS_LFRX28
7
6
5
4
3
2
LFRX_CADET_TH_H[7:0]
Reset value0x7C
1
0
Name LFRX_CADET_TH_H
Decription The upper limit value of carrier frequency detection tolerance window. The unit is the time of a carrier frequency cycle.
Type R/W
Rev 0.6 | 66/102
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AN286
CUS_LFRX29 register
CUS_LFRX29
7
6
5
4
3
2
LFRX_CADET_TH_L[7:0]
Reset value0x65
1
0
Name LFRX_CADET_TH_L
Decription The lower limit value of carrier frequency detection tolerance window. The unit is the time of a carrier frequency cycle.
Type R/W
Notes: LFRX_CADET_TH_H and LFRX_CADET_TH_L are a pair of carrier detection upper/lower window values. For instance, when the 125 kHz carrier detection window is configured as 906.25 us, the unit time is 8 us, reserving a margin of 10% for upper and lower window values .
=
906.25 8
×
110%
=
124
CUS_LFRX30 register
CUS_LFRX30
7
6
=
906.25 8
×
90%
=
101
5
4
3
2
LFRX_SIGNAL_OK_CLR_TH[7:0]
Reset value0x1E
1
0
Name LFRX_SIGNAL_OK_CLR_TH
Decription The perodic auto-reset window time value of the low-frequency module. The configuration is generated by RFPDK.
Type R/W
Notes: This item is valid when the low-frequency auto-reset function is enabled. It is used to automatically reset the low-frequency module at regular intervals. After resetting, the low-frequency module retrieves the preset detection mode (carrier or SNR), synchronization word matching, wake-up ID matching, and so on.
CUS_SYSCTL11 register
CUS_SYSCTL11
7 SLPT_MAN
U_RSTN
6 Reserved
5 Reserved
4 SNOOZE_M ANU_CLR
3 LBD_MANU
_CLR
2 LFRX_MAN
U_CLR
Reset value0x80
1 SLPT_MAN
U_CLR
0 BUT_MANU
_CLR
Name
Decription
Type
Low-frequency wakeup manual clearing flag. Set to 1, the system automatically
2 LFRX_MANU_CLR
R/W
clears.
Rev 0.6 | 67/102
AN286
CUS_SYSCTL12 register
CUS_SYSCTL12
Reset value0x00
7 Reserved
6 SNOOZE_W
AKEUP
5
4
3
2
1
0
LFRXSIGNAL SLEEP_TIME KEY_LAUNC
WKID_PASS SYNC_PASS
OK
SUP
H
Name
Decription
Type
4
WKID_PASS
Flag for matching ID detection valid In low-frequency data, valid when reading as 1.
R
3
SYNC_PASS
Flag for synch word detection valid In low-frequency data, valid when reading as 1.
R
2
LFRX_SIGNAL_OK Flag for low-frequency carrier detection valid, valid when reading as 1.
R
CUS_LFRX31 register
CUS_LFRX31
7
6
5
Reserved
Reserved
Reset value0x00
4
3
2
1
0
LFRX_AGC_INDEX[5:0]
Name
Decription
Type
Low-frequency signal strength indication value, which is used to calculte RSSI value.
5:0 LFRX_AGC_INDEX See Section 4.4 in AN280 CMT216xA Low-frequency Receiving Function User Guide R
for details.
CUS_LFRX32 register
CUS_LFRX32
7 MAN_DECODE
_ERR_FLAG
6 5 4 LFRXMEAS
OUT[2:0]
3 LFRX_IBIAS_CAL
_OVTS_FLAG
2 LFRX_TCAP2_CAL
_OVTS_FLAG
1 LFRX_TCAP1_CAL
_OVTS_FLAG
Reset value0x00 0
LFRX_TCAP0_CAL _OVTS_FLAG
Name
Decription
Type
Low-frequency demodulation data error indication, valid when reading as
7
MAN_DECODE_ERR_FLAG
R
1 (valid when Manchester is enabled).
6:4
LFRX_MEAS_OUT
NA, internal parameter. Users can ignore it.
R
3
LFRX_IBIAS_CAL_OVTS_FLAG NA, internal parameter. Users can ignore it.
R
2 LFRX_TCAP2_CAL_OVTS_FLAG Low-frequency Z-axis antenna tuning overflow flag
R
1 LFRX_TCAP1_CAL_OVTS_FLAG Low-frequency Y-axis antenna tuning overflow flag
R
0 LFRX_TCAP0_CAL_OVTS_FLAG Low-frequency X-axis antenna tuning overflow flag
R
CUS_LFRX33 register
CUS_LFRX33
7
6
Name LFRX_DATA_LENGTH
5
4
3
2
LFRX_DATA_LENGTH[7:0]
Decription Low-frequency data receiving length
Rev 0.6 | 68/102
Reset value0x01
1
0
Type R/W
www.hoperf.com
AN286
CLK_SYS_DIV register
CLK_SYS_DIV
7
6
5
4
3
Reserved LFRX_MCU_RCLK LFRX_MCU_RDATA Reserved
Reset value0x00
2
1
0
CLK_SYS_DIV[3:0]
Name
Decription
Type
6 LFRX_MCU_RCLK Low-frequency demodulation data synchronization clock flag, software accessible.
R
5 LFRX_MCU_RDATA Low-frequency demodulation data flag, software accessible.
R
Notes: 1. Both LFRX_MCU_RCLK and LFRX_MCU_RDATA can generate interrupts. Refer
to the interrupt related sections
CMT216xA User Guide for more details. 2. Suggest users use interrupt mode to
collect low-frequency data bit by bit, especially for LFRX_MCU_RCLK. Since the
synchronous clock is output at a preset rate, interrupt mode can respond in a
timely manner. If the software query method is used, users should pay
attention to the period of the software query interval to avoid asynchrony
causing data loss.
LFRX_IF_TH_H register
LFRX_IF_TH_H
7 Reserve
d
6 Reserve
d
5 Reserve
d
4 Reserve
d
3 LFRX_TBCCI1_S
EL
2 LFRX_TBCC0_S
EL
Reset value0x00
1 LFRX_TACCI1_S
EL
0 LFRX_TACCI0_S
EL
Name
Decription Select CCI1 for outputting low-frequency resonance frequency to TimerB.
3 LFRX_TBCCI1_SEL Set to 1, select output.
Set to 0, close.
Select CCI0 for low-frequency resonance frequency output to TimerB.
2 LFRX_TBCCI0_SEL Set to 1, select output. Set to 0, close.
Select CCI1 for outputting low-frequency resonance frequency to TimerA:
1 LFRX_TACCI1_SEL Set to 1, select output. Set to 0, close.
Select CCI0 for low-frequency resonance frequency output to TimerA.
0
LFRX_TACCI0_SE Set to 1, select output.
Set to 0, close.
Type R/W R/W R/W R/W
LFRX_IF_TH_L register
LFRX_IF_TH_L
7
6
5
4
3
2
LFRX_ANT_REF[7:0]
Reset value0x7D
1
0
Name LFRX_ANT_REF
Decription The target frequency of antenna calibration. The default value is 125, namely 125 kHz.
Type R/W
Rev 0.6 | 69/102
AN286
3.11 Sub-1G Transmiter Module Register Set
Name PA_POWER_TH_9 PA_POWER_TH_8 PA_POWER_TH_7 PA_POWER_TH_6 PA_POWER_TH_5
PA_POWER_TH_4 PA_POWER_TH_3 PA_POWER_TH_2 PA_POWER_TH_1 PA_POWER_TH_0
TX_SYM_GROUP
TX_SYM_CTL TX_PKT_CTL
SYMBOL_TIME_H
SYMBOL_TIME_L
FREQ_DEV_H FREQ_DEV_L RAMP_STEP_TIME_H RAMP_STEP_TIME_L PA_IDAC_CODE
PA_CTL0 VCO_CTL0 VCO_CTL1
PLLN
PLLK_H PLLK_L
Table 12. Sub-1G Transmiter Module Register List
Storage Area Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1
Block1 Block1 Block1 Block1
Block1
Block1
Block1 Block1 Block1 Block1 Block1 Block1 Block1 Block1
Block1
Block1 Block1
Sub-area Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1
Bank1 Bank1
Bank1
Bank1
Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1 Bank1
Bank1
Bank1 Bank1
Address 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0xA9 0xAA 0xAB
0xAC
0xAD
0xAE 0xAF 0xB0 0xB1 0xB3 0xB4 0xB6 0xB7
0xB9
0xBA 0xBB
Reset
Function
0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x00 0x00 0x40
0x00
0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x0F 0x20
0x42
0xC1 0xC5
Transmission power threshold register9 Transmission power threshold register8 Transmission power threshold register7 Transmission power threshold register6 Transmission power threshold register5 Transmission power threshold register4 Transmission power threshold register3 Transmission power threshold register2 Transmission power threshold register1 Transmission power threshold register0 Transmission symbol register Transmission symbol control register Transmission mode control register Transmission data rate configuration register higher 8 bits Transmission data rate configuration register lower 8 bits Frequency deviation register higher 8 bits Frequency deviation register lower 8 bits RAMP configuration register higher 8 bits RAMP configuration register lower 8 bits Transmission power configuration register PA configuration/control register0 VCO control register0 VCO control register1 Phase-locked loop N value configuration register Phase-locked loop K value register higher 8 bits Phase-locked loop K value register lower 8 bits
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AN286
PA_POWER_TH_0-9 register set
PA_POWER_TH_0-9
7
6
5
4
3
2
PA_POWER_TH_n[7:0]
Name PA_POWER_THn
Decription Transmission power configuration according to each voltage level. When n = 0, transmit power configuration value at a voltage of 1.8 V. When n = 1, transmit power configuration value at a voltage of 2.0 V. When n = 2, transmit power configuration value at a voltage of 2.2 V. When n = 3, transmit power configuration value at a voltage of 2.4 V. When n = 4, transmit power configuration value at a voltage of 2.6 V. When n = 5, transmit power configuration value at a voltage of 2.8 V. When n = 6, transmit power configuration value at a voltage of 3.0 V. When n = 7, transmit power configuration value at a voltage of 3.2 V. When n = 8, transmit power configuration value at a voltage of 3.4 V. When n = 9, transmit power configuration value at a voltage of 3.6 V.
Reset value0x7F for all
1
0
Type
R/W
Note: The transmission power configuration value is related to users’ target power value. It is recommended that users assign values according to the configuration values provided by the official configuration tool (software). Using improper values may affect transmission performance.
TX_SYM_GROUP register
TX_SYM_GROUP
7
6
5
4
3
2
TY_SYM_GROUP[7:0] / TX_DIRECT_DATA[0]
Reset value0x00
1
0
Name
Decription
Type
Register for buffer of data to be transmitted.
In the packet mode, transmit data according to bit width defined by
7:0 TX_SYM_GROUP
R/W
TX_GROUP_WIDTH.
In the direct mode, the direct transmission is performed through setting Bit0 to 0 or 1.
TX_SYM_CTL register
TX_SYM_CTL
7 Reserved
6 TX_DIRECT_EN
5
4
3
TX_GROUP_WIDTH[2:0]
2 TX_SYM_ENDIAN
Reset value0x00
1
0
TX_SYM_CTRL[1:0]
Name
Decription
Direct mode enabling control.
6
TX_DIRECT_EN Set to 0, adopt packet mode.
Set to 1, adopt direct mode.
5:3 TX_GROUP_WIDTH Determine the TX_SYM_GROUP transmission bit width with a range of 1 – 8 bits.
Transmission data little/large endian mode selection.
2
TX_SYM_ENDIAN Set to 0, little endian mode, that is, data move to right with low bit out first;
Set to 1, big endian mode, that is, data move to left with high bit out first;
Type R/W R/W R/W
Rev 0.6 | 71/102
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AN286
Name
Decription
Transmission end mode selection.
2’b00, close transmission after the last bit transmission completes.
1:0
TX_SYM_CTRL 2’b01, keep transmitting the last bit after the last bit transmission completes.
2’b10, keep transmitting 0.
2’b11, keep transmitting 1.
Type R/W
Notes: 1. The main difference between packet mode and direct mode is that the
former needs to define the transmission buffer array
in the code, transmission is done through relevant API functions, and
transmission rate follows the set rate; while the direct mode does not need to
define the transmission buffer data, and it is not limited to use the set
transmission rate (suggest users fill a rate greater than the actual
transmission rate in the configuration tool software), instead the
transmission time is adjusted by software. Please refer to the Datasheet
specifications and related AN documents for more details. 2. When using the
API function tx_sym_transmit to implement the transmission function, the
TX_SYM_CTRL setting is invalid, and it is processed according to the 2’b00
option, that is, the transmission function is closed after the transmission is
completed.
TX_PKT_CTL register
TX_PKT_CTL
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 RAMP_EN
2 TX_MODU
Reset value0x40
1 FREQ_DEV_INV
0 GUASS_ON
Name
Decription
Set to 0, disable the RAMP function.
3
RAMP_EN
Set to 1, enable the RAMP function.
Modulation mode selection.
2
TX_MODU
Set to 0, OOK modulation mode.
Set to 1, FSK modulation mode.
FSK mode data modulation polarity.
1
FREQ_DEV_INV Set to 0, +FDEV is 1, -FDEV is 0 (FDEV is the transmission frequency deviation).
Set to 1, +FDEV is 0, -FDEV is 1.
Set to 0, disable FSK data Gaussian filtering.
0
GUASS_ON
Set to 1, enable FSK data Gaussian filtering.
Type R/W R/W
R/W R/W
SYMBOL_TIME_H / L register set
SYMBOL_TIME_H/L
7 H L
6
5
4
3
2
SYMBOL_TIME[15:8]
SYMBOL_TIME[7:0]
Reset value0x00/0x00
1
0
Name SYMBOL_TIME[15:0]
Decription Transmission data rate configuration. FSK modulation, with a configurable range of 0.5 – 200 kbps. OOK modulation with a data rate range of 0.5 – 40 kbps.
Notes:
Rev 0.6 | 72/102
Type R/W
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AN286
The rate calcualtion formula is as follows.
_
=
× 221
In above, FXTAL is crystal frequency, namely 26 MHz. In addition, users do not need to do te calculatation. The official configuration tool software can be used to automatically generate the target parameter results just by setting the target rate..
FREQ_DEV_H / L register set
FREQ_DEV_H/L
7
6
5
H
L
4
3
2
FREQ_DEV[15:8]
FREQ_DEV[7:0]
Reset value0x00/0x00
1
0
Name FREQ_DEV[15:0]
Decription FSK transmission frequency deviation configuration.
Type R/W
RAMP_STEP_TIME_H / L register set
RAMP_STEP_TIME_H/L
7
6
5
H
L
4
3
2
RAMP_STEP_TIME[14:8]
RAMP_STEP_TIME[7:0]
Reset value0x00/0x00
1
0
Name RAMP_STEP_TIME[14:0]
Decription PA RAMP step time register. The minimum step size is 76.9 ns, and the maximum step size is 20 us.
Type R/W
PA_IDAC_CODE register
PA_IDAC_CODE
Reset value0x00
7
6
5
4
3
2
1
0
Reserved
Reserved
PA_IDAC_CODE[5:0]
Name
Decription
The transmit power IDAC configuration, co-working with the PA_POWER_TH_0-9 5:0
PA_IDAC_CODE
register set to determine the transmission power;
Type R/W
Note: The above register configuration values need to be set by the configuration tool (XLS file or GUI software) through set target parameters (such as operating frequency, rate, frequency diviation) by users then the tools will automatically convert them into register configurations.
Rev 0.6 | 73/102
AN286
PA _CTL0 register
PA _CTL0
7 Reserved
6 Reserved
5
4
3
Reserved PA_DIFF_SEL PA_RCRAMP_SELB
Name
Decription
PA operating mode selection.
4
PA_DIFF_SEL
Set to 0, select the single-ended PA output.
Set to 1, select the differential PA output.
PA RAMP RC filter enabling selection. 3 PA_RCRAMP_SELB Set to 0, enable the RC
filter.
Set to 1, disable the RC filter.
2:0 PA_RAMP_RSEL PA RAMP RC filter parameter selection.
Reset value0x00
2
1
0
PA_RAMP_RSEL[2:0]
Type R/W
R/W R/W
VCO _CTL0 register
VCO _CTL0
7 Reserved
6 Reserved
5 Reserved
4
3
2
VCO_GAIN_CODE[2:0]
Name
Decription
4:2 VCO_GAIN_CODE The VCO gain configuration value.
PLL bandwidth selection.
1:0
PLL_BW_SEL
Set to 0, select 210 kHz.
Set to 1, select 150 kHz.
Reset value0x0F
1
0
PLL_BW_SEL[1:0]
Type R/W
R/W
VCO _CTL1 register
VCO _CTL1
7
6
5
4
3
VCO_HBAND PDCPLF_CPBIAS_CODE DIVX_CODE[1:0]
Reset value0x20
2
1
0
DIVX_SEL[3:0]
Name
Decription
VCO frequency band selection.
7
VCO_HBAND
Set to 0, select low frequency band.
Set to 1, select high frequency band.
Type R/W
6
PDCPLF_CPBIAS_CODE PDCPLF current control
R/W
5:4
DIVX_CODE
The two parameters determine the PLL frequency division ratio R/W
DIV_VALUE, and the VCO frequency is divided by the DIV_VALUE to the
3:0
DIVX_SEL
PA output frequency.
R/W
PLLN / PLLK_H / PLLK_L register set
PLLN / PLLK_ H/ PLLK_L
7
6
5
N
K_H
K_L
4
3
PLLN [7:0]
PLLK_H [15:8]
PLLK_L [7:0]
Rev 0.6 | 74/102
Reset value0x42 / 0xC1 / 0xC5
2
1
0
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AN286
Name PLLN[7:0] PLLK[15:0]
Decription N value and K value of PLL configuration. This parameter is related to transmission power.
Type R/W R/W
Notes:
1. The above register configuration values need to be set by the
configuration tool (XLS file or GUI software) through set target parameters
(such as operating frequency, rate, frequency diviation) by users then the
tools will automatically convert them into register configurations..
2. The PLL_K and PLLN values in the phase-locked loop are calculated as
follows:
= × _
_
=
×
_
–
_
×
216
In above,
DIV_VALUE is the frequency division from VCO frequency to PA output. It is
determined by DIVX_CODE and DIVX_SEL in VCO_CTL1 register. Please refer to
CMT216xA User Guide for details.
FXO is the crystal oscillator frequency, which is 26 MHz; FRF is the target
operating frequency.
PLL_N is the integer part of the phase-locked loop, which is calculated and
rounded according to the target frequency, the VCO frequency division value
and the crystal frequency. Then calculate the PLL_K, the decimal part of the
phase-locked loop.
Rev 0.6 | 75/102
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AN286
3.12 Analog Front EndAFEregister Set
ULPOA & HSOA, SAR-ADC and SNOOZE are the 3 core analog front end parts.
Table 13. Analog Front End Register Set List
Name
CUS_AFE4 CUS_AFE6 CUS_AFE7 CUS_AFE9 CUS_AFE10 CUS_AFE11 CUS_AFE12 CUS_AFE13
CUS_AFE14 CUS_AFE15 CUS_AFE16 CUS_AFE17 CUS_AFE18 CUS_SNOOZE1 CUS_SNOOZE2
CUS_SNOOZE3
CUS_SNOOZE4
CUS_SNOOZE5 CUS_SNOOZE6 CUS_SYSCTL3 CUS_SYSCTL11 CUS_SYSCTL12 CUS_SYSCTL13
CUS_SYSCTL14 CUS_SYSCTL15
CUS_SYSCTL19
CUS_RESV5
Storage Area Block0 Block0 Block0 Block0 Block0 Block0 Block0 Block0 Block0
Block0 Block0 Block0 Block0 Block0 Block0
Block0
Block0
Block0 Block0 Block0 Block0 Block0 Block0 Block0 Block0
Block0
Block0
Address
0x03 0x05 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x1E 0x1F
0x20
0x21
0x22 0x23 0x50 0x68 0x69 0x6A 0x6B 0x6C
0x70
0x7A
Reset 0x00 0x80 0x80 0xC1 0x00 0x00 0x00 0x84 0xFF 0xB7 0x07
0x00 0x00
0x00
0x00
0x00 0x00 0x00 0x80 0x00 0x00 0x00 0x00
0x70
0x7A
Function
Gain Configuration Register-1 Gain Configuration Register-2 Bridge sensor
interface configuration register DC bias configuration register HSOA0
configuration register HSOA1 configuration register HSOA2 configuration
register Micro-power regulator output and ADC input configuration register AFE
control register-1 AFE control register-2 ADC conversion time configuration
and LPOAs control register Constant current source drive control register-1
Constant current source drive control register-2 SNOOZE configuration
register-1 (sleep cycle configuration 1) SNOOZE configuration register-2
(sleep cycle configuration 2) SNOOZE interrupt threshold register-1 (trigger
window upper limit configuration) SNOOZE Interrupt Threshold Register-2
(trigger Window Lower Limit Configuration) SNOOZE interrupt enabling and ADC
clock frequency select register SNOOZE interrupt flag register System control
register 3 (SNOOZE mode control register) System control register 11 (software
clearing flag control register) System control register 12 (SNOOZE interrupt
wake-up flag) ADC control register ADC data register-1 ADC data register-2
System control register 19 (constant current source drive pulse output port
control) LPOAs non-inverting input port configuration register
Rev 0.6 | 76/102
AN286
CUS_AFE4 register
CUS_AFE4
7
6
AFE_IA2_GX[1:0]
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
Reset value0x00 0
Reserved
Name
Decription
Type
Gain selection for internal HSOA0 used as a second amplifier or
non-inverting amplifier of general-purpose instrumentation.
00, the gain is x1.0.
7:6
AFE_IA2_GX
R/W
01, the gain is x1.5.
10, the gain is x2.0.
11, the gain is x3.0.
CUS_AFE6 register
CUS_AFE6
7 Reserved
6 Reserved
5
4
3
AFE_IA1_GX[2:0]
2 Reserved
1 Reserved
Reset value0x80 0
Reserved
Name
Decription
Type
Gain selection for internal HSOA1 and HSOA2 used as a first amplifier or
a non-inverting amplifier of general-purpose instrumentation.
3’b000, no gain setting, disabled when the amplifier is operating.
3’b001, the gain is x2.
3’b010, the gain is x4.
5:3
AFE_IA1_GX
R/W
3’b011, the gain is x8.
3’b100, the gain is x16.
3’b101, the gain is x24.
3’b110, the gain is x32.
3’b111, the gain is x48.
CUS_AFE7 register
CUS_AFE7
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
Reset value0x80
2
1
0
AFE_SEN_CHX[2:0]
Name
Decription
Type
Sensor channel selection:
3’b000, no channel selection.
3’b001, select external sensor channel 1, A1 and A2 pins as bridge
sensor input, ASN and ASP pins as sensor power source;
2:0
AFE_SEN_CHX
3’b010, select external sensor channel 2, A3 and A4 pins as bridge
R/W
sensor input, PSN and PSP pins as sensor power supply excitation
source.
3’b011, select the internal temperature sensor channel.
3’b1xx, cannot use.
References
Read User Manual Online (PDF format)
Read User Manual Online (PDF format) >>