Intel 23.2 Quartus Prime Pro Edition User Guide
- June 13, 2024
- Intel
Table of Contents
Intel 23.2 Quartus Prime Pro Edition
Product Information
Product Name: Intel Quartus Prime
The Intel Quartus Prime is a software suite used for FPGA (Field-Programmable Gate Array) design. It provides a comprehensive set of tools and features to facilitate the creation, optimization, and analysis of FPGA designs.
Key Features:
- Project management capabilities
- Logic design file management
- Timing constraint management
- Integration with other EDA (Electronic Design Automation) tools
- Exporting compilation results
- Design planning capabilities
System Requirements:
To use Intel Quartus Prime, you will need:
- A compatible operating system (refer to the user manual for supported OS versions)
- A computer with sufficient processing power and memory
- An Intel FPGA device
User Manual:
The user manual for Intel Quartus Prime can be found in the provided documentation. It contains detailed instructions on various aspects of the software, including FPGA design prerequisites, software edition selection, project setup, IP integration, project migration, and more.
Product Usage Instructions
1. FPGA Basic Design Prerequisites
To start using Intel Quartus Prime for FPGA design, make sure you meet the basic design prerequisites outlined on page 6 of the user manual.
2. Selecting an Intel Quartus Prime Software Edition
Refer to page 7 of the user manual to understand the different software editions available for Intel Quartus Prime and choose the one that suits your requirements.
3. Creating a New FPGA Design Project
To create a new FPGA design project using Intel Quartus Prime, follow the
instructions provided on page 10 of the user manual.
This section also covers the usage of the Board-Aware Flow for project
creation.
4. Managing Intel Quartus Prime Projects
Refer to the relevant sections in the user manual to learn about managing Intel Quartus Prime projects. This includes viewing basic project information, using the compilation dashboard, viewing project reports and messages, managing project settings, logic design files, timing constraints, and integrating other EDA tools.
5. Exporting Compilation Results
If you need to export the compilation results from Intel Quartus Prime, follow the instructions provided on page 36 of the user manual.
6. Design Planning
For design planning tasks in Intel Quartus Prime, refer to page 59 of the user manual for detailed instructions.
Intel® Quartus® Prime Pro Edition User Guide
Getting Started
Updated for Intel® Quartus® Prime Design Suite: 23.2
This document is part of a collection – Intel® Quartus® Prime Pro Edition User
Guides – Combined PDF link
Answers to Top FAQs:
Q What do I need for FPGA design? A FPGA Basic Design Prerequisites on page 6
Q What do I need to download to use Quartus? A Intel FPGA Design Software for
Download on page 6
Q Which Quartus version should I use? A Selecting a Software Edition on page 7
Q How do I setup a project? A Creating a New Project on page 10
Q Do you have an example design to start with? A Start a Project from a Design
Example on page 11
Q Does Quartus work with my other tools? A Integrating Other EDA Tools on page
36
Q How do I add my IP? A Adding Your IP to IP Catalog on page 83
Q How do I migrate an old project? A Migrate to Intel Quartus Prime Pro
Edition on page 118
Q Do you have basic tool training? A Intel FPGA Technical Training Curriculum
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Contents
Contents
1. Introduction to Intel® Quartus® Prime Pro Edition………………………………………………… 5
1.1. FPGA Basic Design Prerequisites…………………………………………………………………… 6 1.2.
Selecting an Intel Quartus Prime Software Edition……………………………………………… 7 1.3.
Introduction to Intel Quartus Prime Pro Edition Revision History……………………………..8
2. Managing Intel Quartus Prime Projects……………………………………………………………… 10
2.1. Creating a New FPGA Design Project……………………………………………………………..10 2.1.1.
Using the Board-Aware Flow……………………………………………………………. 10
2.2. Viewing Basic Project Information……………………………………………………………….. 20 2.2.1.
Using the Compilation Dashboard………………………………………………………22 2.2.2. Viewing Project
Reports…………………………………………………………………. 23 2.2.3. Viewing Project
Messages………………………………………………………………. 24
2.3. Intel Quartus Prime Project Contents……………………………………………………………. 28 2.3.1.
Project File Best Practices………………………………………………………………..28
2.4. Managing Project Settings………………………………………………………………………….29 2.4.1.
Optimizing Project Settings…………………………………………………………….. 30
2.5. Managing Logic Design Files………………………………………………………………………. 34 2.5.1.
Including Design Libraries………………………………………………………………. 34 2.5.2. Creating a
Project Copy…………………………………………………………………. 35
2.6. Managing Timing Constraints………………………………………………………………………35 2.7. Integrating
Other EDA Tools………………………………………………………………………. 36 2.8. Exporting Compilation
Results……………………………………………………………………. 36
2.8.1. Exporting a Version-Compatible Compilation Database …………………………… 37
2.8.2. Importing a Version-Compatible Compilation Database ……………………………39
2.8.3. Creating a Design Partition……………………………………………………………… 40 2.8.4. Exporting
a Design Partition……………………………………………………………. 42 2.8.5. Reusing a Design
Partition……………………………………………………………….44 2.8.6. Viewing Quartus Database File
Information…………………………………………. 45 2.8.7. Clearing Compilation
Results…………………………………………………………… 46 2.9. Migrating Projects Across Operating
Systems………………………………………………….. 47 2.9.1. Migrating Design Files and
Libraries…………………………………………………… 47 2.9.2. Design Library Migration
Guidelines…………………………………………………… 48 2.10. Archiving
Projects…………………………………………………………………………………. 49 2.10.1. Manually Adding Files To
Archives…………………………………………………….49 2.10.2. Archiving Projects for Service
Requests…………………………………………….. 50 2.10.3. Archiving Projects for External
Revision Control…………………………………… 50 2.10.4. Creating Database-Only
Archives……………………………………………………..52 2.11. Command-Line
Interface………………………………………………………………………….53 2.11.1. Project Revision
Commands……………………………………………………………53 2.11.2. Project Archive
Commands……………………………………………………………. 54 2.11.3. Project Database
Commands…………………………………………………………. 55 2.12. Managing Projects Revision
History……………………………………………………………..56
3. Design Planning……………………………………………………………………………………………… 59
3.1. Design Planning………………………………………………………………………………………59 3.2. Create a Design
Specification and Test Plan……………………………………………………. 59 3.3. Plan for the Target
Device or Board……………………………………………………………… 59
3.3.1. Device Migration Planning………………………………………………………………. 60
Intel Quartus Prime Pro Edition User Guide: Getting Started 2
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3.4. Plan for Intellectual Property Cores……………………………………………………………… 61 3.5. Plan
for Standard Interfaces………………………………………………………………………. 61 3.6. Plan for Device
Programming………………………………………………………………………62 3.7. Plan for Device Power
Consumption………………………………………………………………63 3.8. Plan for Interface I/O
Pins………………………………………………………………………….67 3.9. Plan for other EDA
Tools…………………………………………………………………………… 69
3.9.1. Third-Party Synthesis Tools…………………………………………………………….. 69 3.9.2. Third-
Party Simulation Tools……………………………………………………………. 69 3.10. Plan for On-Chip
Debugging Tools……………………………………………………………….70 3.11. Plan HDL Coding
Styles……………………………………………………………………………71 3.11.1. Design
Recommendations………………………………………………………………71 3.11.2. Recommended HDL Coding
Styles…………………………………………………… 71 3.11.3. Managing
Metastability………………………………………………………………… 71 3.12. Plan for Hierarchical and
Team-Based Designs………………………………………………..72 3.12.1. Flat Compilation without
Design Partitions…………………………………………. 72 3.13. Design Planning Revision
History……………………………………………………………….. 73
4. Introduction to Intel FPGA IP Cores……………………………………………………………………76
4.1. IP Catalog and Parameter Editor…………………………………………………………………. 77 4.1.1. The
Parameter Editor……………………………………………………………………..78
4.2. Installing and Licensing Intel FPGA IP Cores…………………………………………………… 78
4.2.1. Intel FPGA IP Evaluation Mode…………………………………………………………. 79
4.3. IP General Settings…………………………………………………………………………………. 82 4.4. Adding IP to
IP Catalog……………………………………………………………………………..83 4.5. Best Practices for Intel FPGA
IP……………………………………………………………………84 4.6. Specifying the IP Core Parameters and
Options (Intel Quartus Prime Pro Edition)……… 84
4.6.1. Applying Preset Parameters for Specific Applications………………………………. 86
4.6.2. Customizing IP Presets………………………………………………………………….. 88 4.7. IP Core
Generation Output (Intel Quartus Prime Pro Edition)………………………………..91 4.8.
Scripting IP Core Generation……………………………………………………………………… 93 4.9. Modifying an
IP Variation………………………………………………………………………….. 94 4.10. Upgrading IP
Cores……………………………………………………………………………….. 94 4.10.1. Upgrading IP Cores at
Command-Line………………………………………………. 97 4.10.2. Migrating IP Cores to a Different
Device……………………………………………. 98 4.10.3. Troubleshooting IP or Platform Designer
System Upgrade………………………. 99 4.11. Simulating Intel FPGA IP
Cores…………………………………………………………………100 4.11.1. Generating IP Simulation
Files……………………………………………………….100 4.11.2. Scripting IP
Simulation………………………………………………………………..102 4.12. Generating Simulation Files for
Platform Designer Systems and IP Variants………….. 111 4.13. Synthesizing IP
Cores in Other EDA Tools…………………………………………………… 113 4.14. Instantiating IP Cores
in HDL………………………………………………………………….. 113 4.14.1. Example Top-Level Verilog HDL
Module…………………………………………….114 4.14.2. Example Top-Level VHDL
Module…………………………………………………… 114 4.15. Support for the IEEE 1735 Encryption
Standard…………………………………………….114 4.16. Introduction to Intel FPGA IP Cores
Revision History……………………………………… 116
5. Migrating to Intel Quartus Prime Pro Edition…………………………………………………….. 118
5.1. Keep Pro Edition Project Files Separate……………………………………………………….. 118 5.2.
Upgrade Project Assignments and Constraints……………………………………………….. 118
5.2.1. Modify Entity Name Assignments……………………………………………………..119 5.2.2. Resolve
Timing Constraint Entity Names…………………………………………….119
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5.2.3. Verify Generated Node Name Assignments………………………………………….120 5.2.4.
Replace Logic Lock (Standard) Regions…………………………………………….. 120 5.2.5. Modify
Signal Tap Logic Analyzer Files………………………………………………. 122 5.2.6. Remove
References to .qip Files……………………………………………………… 123 5.2.7. Remove Unsupported
Feature Assignments…………………………………………123 5.3. Upgrade IP Cores and Platform
Designer Systems………………………………………….. 124 5.4. Upgrade Non-Compliant Design
RTL…………………………………………………………….125 5.4.1. Verify Verilog Compilation Unit
………………………………………………………. 125 5.4.2. Update Entity Auto-
Discovery………………………………………………………… 126 5.4.3. Ensure Distinct VHDL Namespace for
Each Library……………………………….. 127 5.4.4. Remove Unsupported Parameter
Passing…………………………………………… 127 5.4.5. Remove Unsized Constant from WYSIWYG
Instantiation………………………… 127 5.4.6. Remove Non-Standard
Pragmas……………………………………………………… 128 5.4.7. Declare Objects Before Initial
Values…………………………………………………128 5.4.8. Confine SystemVerilog Features to
SystemVerilog Files…………………………..128 5.4.9. Avoid Assignment Mixing in Always
Blocks…………………………………………. 129 5.4.10. Avoid Unconnected, Non-Existent
Ports…………………………………………… 129 5.4.11. Avoid Illegal Parameter
Ranges…………………………………………………….. 129 5.4.12. Update Verilog HDL and VHDL Type
Mapping…………………………………….. 130 5.5. Migrating to Intel Quartus Prime Pro Edition
Revision History…………………………….. 130
6. Document Archives……………………………………………………………………………………….. 131
A. Intel Quartus Prime Pro Edition User Guides…………………………………………………….. 132
Intel Quartus Prime Pro Edition User Guide: Getting Started 4
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1. Introduction to Intel® Quartus® Prime Pro Edition
Figure 1.
This user guide describes basic concepts and operation of the Intel® Quartus®
Prime Pro Edition software. This software provides a complete design
environment for FPGA designs targeting the Intel Agilex® 7, Intel Stratix® 10,
Intel Arria® 10, and Intel Cyclone® 10 GX devices.(1)
Intel Quartus Prime Pro Edition Software GUI
The Intel Quartus Prime software GUI supports easy design entry, fast design processing, straightforward device programming, and integration with other industrystandard EDA tools. The user interface makes it easy for you to focus on your design– not on the design tool. The modular Compiler streamlines the FPGA development process, and ensures the highest performance for the least effort.
(1) A field-programmable gate array (FPGA) is a specialized integrated circuit that you can customize and reconfigure multiple times. To learn about and select a target Intel FPGA device family, refer to https://www.intel.com/content/www/us/en/products/details/fpga.html.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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1.1. FPGA Basic Design Prerequisites
Using the Intel Quartus Prime software to create a basic FPGA design requires the following prerequisite knowledge and software installation and licensing:
Prerequisite Knowledge
· Basic knowledge of digital logic design.
· Basic knowledge of how to describe a hardware design using VHDL, Verilog
HDL, SystemVerilog, or EDA schematic tools.
Note:
You can accelerate design creation and success by starting your design project from a pre-verified design example that targets an Intel FPGA development board, as Creating a New Project from a Design Example on page 11 describes.
Prerequisite Software and Licensing
To use the Intel Quartus Prime software for FPGA design, your system must
first meet the minimum Windows or Linux system requirements for installation.
Next, you download and install the software components. You must purchase a
license for any applicable software prior to production use.
The Intel FPGA Software Download Center webpage allows you to download Intel
FPGA software and IP cores. To download software, select and visit the desired
software landing page from the FPGA Software Download Center.
Table 1.
Intel FPGA Design Software for Download and Installation
Software Intel Quartus Prime Software
Device support Files (.qdz)
Description
Required?
You must install an edition of the Intel Quartus Prime software to
Yes
compile your design and generate files to program the target FPGA.
The Intel Quartus Prime installation also includes the Intel FPGA IP
Library and Nios II EDS.
The Intel Quartus Prime Pro Edition software provides unique features that support the latest Intel FPGAs. Select the Intel Quartus Prime software edition that provides the device support and features you require, as Selecting an Intel Quartus Prime Software Edition on page 7 describes.
You must install support for one or more Intel FPGA device families Yes as part of the Intel Quartus Prime software installation when prompted. Only select the support files for the device families that you plan to target.
Intel Quartus Prime Help Files Questa* Intel FPGA Edition Simulator
DSP Builder for Intel® FPGAs
Optional HTML help system that provides descriptions of the Intel
No
Quartus Prime software GUI.
Intel provides this simulator which is a version of the Questa*
No
Advanced simulator targeted for simulating Intel Quartus Prime
designs. The Questa Intel FPGA Edition simulator supports the Intel
FPGA gate-level simulation libraries, and includes behavioral
simulation, HDL test benches, and Tcl scripting support.
Digital signal processing (DSP) design tool that enables Hardware
No
Description Language (HDL) generation of DSP algorithms directly
from the MathWorks Simulink* environment onto Intel FPGAs.
Note:
Refer to Intel FPGA Software Installation and Licensing for step-by-step installation and licensing instructions for all Intel FPGA software.
Intel Quartus Prime Pro Edition User Guide: Getting Started 6
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Related Information · Intel FPGA Software Installation and Licensing · FPGAs for Dummies eBook
1.2. Selecting an Intel Quartus Prime Software Edition
Depending on your target FPGA device and desired software features, you can
choose either the Intel Quartus Prime Pro Edition software or the Intel
Quartus Prime Standard Edition software for your Intel FPGA design.
· Select the Intel Quartus Prime Pro Edition software if you are beginning a
new Intel Arria 10, Intel Cyclone 10 GX, Intel Stratix 10 or Intel Agilex 7
design, or to take advantage of the unique features of Intel Quartus Prime Pro
Edition.
· Select the Intel Quartus Prime Standard Edition software if your design must
target Arria V, Arria, Intel Cyclone 10 LP, Cyclone IV, Cyclone V, or MAX®
series devices, and you do not want to migrate you design to a device that
Intel Quartus Prime Pro Edition supports.
Figure 2. Intel Quartus Prime Feature Support Matrix
Software Features
Intel Quartus® Prime Standard Edition
Intel Quartus Prime Pro Edition
New Hybrid Placer & Global Router New Timing Analyzer New Physical Synthesis Platform Designer (formerly Qsys) Intel Stratix® 10 Device Support Intel Agilex® 7 Device Support Partial Reconfiguration Block-Based (Hierarchical) Design Flows OpenCL support Incremental Fitter Optimization Interface Planner (formerly BluePrint)
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The following features are only available in the Intel Quartus Prime Pro
Edition software:
· Hyper-Aware Design Flow–use Hyper-Retiming to reach the highest performance
in Intel Agilex 7 and Intel Stratix 10 devices.
· Advanced synthesis–integrates new, stricter language parser supporting all
major IEEE RTL languages, with enhanced algorithms, and parallel synthesis
capabilities, and support for SystemVerilog 2009.
· Hierarchical project structure–preserve individual post-synthesis, post-
placement, and post-place and route results for design instances. Optimizes
without impacting other partition placement or routing.
· Incremental Fitter Optimizations–run and optimize Fitter stages
incrementally. Each Fitter stage generates detailed reports.
· Faster, more accurate I/O placement–plan interface I/O in Interface Planner.
· Platform Designer (Pro)–builds on the system design and custom IP
integration capabilities of Platform Designer (Standard). Platform Designer
(Pro) introduces hierarchical isolation between system interconnect and IP
components.
· Block-Based Design Flows–preserve and reuse design blocks at various stages
of compilation.
Intel Quartus Prime Pro Edition software does not support the following Intel
Quartus Prime Standard Edition features:
· I/O Timing Analysis
· NativeLink third party tool integration (other third-party tool integration
available)
· Video and Image Processing Suite IP Cores
· Talkback features
· Various register merging and duplication settings
· Saving a node-level netlist as .vqm or RTL to schematic conversion
Related Information
Migrating to Intel Quartus Prime Pro Edition on page 118
1.3. Introduction to Intel Quartus Prime Pro Edition Revision History
Document Version 2023.04.03 2022.06.20
2020.09.28 2019.09.30 2018.09.24
Intel Quartus Prime Version
Changes
23.1
· Updated product family name to “Intel Agilex 7.”
22.2
· Added new Top FAQs navigation to document cover. · Revised Introduction to
add FPGA definition and device selection
footnote. · Added new FPGA Basic Design Prerequisites topic. · Added new
Experiment with a Design Example topic.
20.3
· Updated GUI screenshot in Introduction.
19.3
· Added compilation support for Intel Agilex 7 devices.
18.1
· Added screenshot of Intel Quartus Prime Pro Edition GUI. continued…
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Document Version 2018.05.07 2017.11.06 2017.05.08 2016.10.31
2016.05.03
2015.11.02
Intel Quartus Prime Version
Changes
18.0
Initial release as separate chapter of Getting Started User Guide. Separated Migrating to Intel Quartus Prime Pro Edition as independent chapter in user guide.
17.1
· Described Intel Quartus Prime tool name updates for Platform Designer
(Qsys), Interface Planner (BluePrint), Timing Analyzer (TimeQuest), Eye Viewer
(EyeQ), and Intel Advanced Link Analyzer (Advanced Link Analyzer).
· Added Verilog HDL Macro example.
· Updated for latest Intel branding conventions.
17.0
· Removed statement about limitations for safe state machines. The Compiler
supports safe state machines. State machine inference is enabled by default.
· Added reference to Block-Based Design Flows.
· Removed procedure on manual dynamic synthesis report generation. The
Compiler automatically generates dynamic synthesis reports when enabled.
16.1
· Implemented Intel rebranding.
· Added reference to Partial Reconfiguration support.
· Added to list of Intel Quartus Prime Standard Edition features unsupported
by Intel Quartus Prime Pro Edition.
· Added topic on Safe State Machine encoding.
· Described unsupported Intel Quartus Prime Standard Edition physical
synthesis options.
· Removed deprecated Per-Stage Compilation (Beta) Compilation Flow.
· Changed title from “Remove Filling Vectors” to “Remove Unsized Constant”.
16.0
· Removed software beta status and revised feature set. · Added topic on Safe
State Machine encoding. · Added Generating Dynamic Synthesis Reports. ·
Corrected statement about Verilog Compilation Unit. · Corrected typo in Modify
Entity Name Assignments. · Added description of Fitter Plan, Place and Route
stages,
reporting, and optimization. · Added Per-Stage Compilation (Beta) Compilation
Flow. · Added Platform Designer information. · Added OpenCL and Signal Tap
with routing preservation as unique
Pro Edition features. · Clarified limitations for multiple Logic Lock
instances in the same
region.
15.1
· First version of document.
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Managing Intel Quartus Prime Projects
The Intel Quartus Prime software organizes and manages the elements of your
design within a project. The project encapsulates information about your
design files, hierarchy, libraries, constraints, and project settings. This
chapter describes the basics of working with Intel Quartus Prime software
projects, including initial project setup, viewing project information, adding
design files and constraints, and viewing and exporting the design compilation
results. After you create or open a project, the GUI displays integrated
information and controls for the open project.
2.1. Creating a New FPGA Design Project
The Intel Quartus Prime software makes it easy for you to quickly setup a new
FPGA design project. Click File > New Project Wizard to quickly setup and open
a new project tailored for your application. The wizard guides you through
specifying various options for new project setup. The wizard includes access
to helpful project templates and design examples that allow you to
preconfigure project settings for specific applications, FPGA devices, and
target boards. Alternatively, you can create a blank design project and
specify all design files and settings.
Figure 3. New Project Wizard – Introduction
2.1.1. Using the Board-Aware Flow
The Intel Quartus Prime Pro Edition software allows you to create a system
that targets a specific development board, rather than only targeting a
specific FPGA device. When you target a specific development board, the Intel
Quartus Prime software is aware of the target board (board-aware) which
accelerates the process of appropriately configuring, connecting, and
validating IP for the target board.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
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What is the Intel Quartus Prime Software Board-Aware Flow?
In the board-aware flow, you can optionally start your project from a pre-
verified design example (rather than an empty project) and target a specific
Intel FPGA development board. You can also create appropriate IP presets to
target the specific board. The Intel Quartus Prime Platform Designer system
integration tool is also board-aware, allowing you to automatically set pin
assignments and export appropriate system interfaces for the target board.
The board-aware flow simplifies the application of appropriate parameters and
pin assignments for the instantiated IP in your project, thereby reducing the
chance of configuration errors. You can also save and reuse your preferred and
verified board and IP configurations for use in other projects that target the
same IP or board.
The board-aware flow helps to ensure the proper hand-off, consistency, and
reuse of configuration options across multiple projects, developers, and
boards.
Note:
To define new boards and IP preset files in Platform Designer, refer to Intel Quartus Prime Pro Edition User Guide: Platform Designer and AN 988: Using the Board-Aware Flow in the Intel Quartus Prime Pro Edition Software.
Related Information · Creating a New Project from a Design Example on page 11
· Specifying a Target Board for the Project on page 19 · Applying Preset
Parameters for Specific Applications on page 86 · Intel Quartus Prime Pro
Edition User Guide: Platform Designer · AN 988: Using the Board-Aware Flow in
the Intel Quartus Prime Pro Edition
Software
2.1.1.1. Creating a New Project from a Design Example
The Intel Quartus Prime software provides access to installed and online
platform- and board-specific design examples that you can use as a starting
point for your own design. You can accelerate your design progress by starting
from a pre-validated design example that installs with the Intel Quartus Prime
software or is available online.
This technique can be especially helpful if you are new to FPGA design or EDA
design tools. The design example can help you to quickly analyze a validated
design on a board and appropriately configure it in various ways to match your
users’ needs. Alternatively, you can start with an Empty Project for which you
specify all settings and design files.
· Pre-installed design examples–you can immediately access the design examples
that install along with the Intel Quartus Prime software installation at:
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2. Managing Intel Quartus Prime Projects 683463 | 2023.06.26
Figure 4.
To create a new Intel Quartus Prime project that is based on a design example,
follow these steps:
1. the Intel Quartus Prime software, click File New Project Wizard. Click
Next to view the Family, Device & Board Settings wizard page.
2. Under the Select the type of project to create, select Design Example and
click Next. The Family, Device & Board Settings page appears, allowing you to
find and select the design example from which to base your project.
Family, Device & Board Settings Page of New Project Wizard
Figure 5.
3. Under What is the working directory for this project?, specify the
directory to store your project files and click Next.
4. Under Find Options, select the Family, Development Kit, and Vendor design
example you want to use. Refer to Family, Device & Board Settings on page 13.
Board Tab in New Project Wizard
Intel Quartus Prime Pro Edition User Guide: Getting Started 12
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The search results display the design examples that meet your search criteria.
5. Select the design example that you want in the search results and click
Next. If the design example is licensed by Intel FPGA, a Software License
Agreement page appears that prompts you to accept the license agreement before
you can proceed.
6. Click Next to proceed to the Summary page.
7. Click Finish to deploy the selected design example in the Intel Quartus
Prime software. When a design example downloads, the design’s .par downloads
to the download path that you define in More Settings, but the design itself
extracts to the project working directory that you specify.
Also refer to Accessing Online Design Examples on page 15 and Accessing
Downloaded Design Examples on page 18.
Related Information Intel FPGA Design Examples
2.1.1.1.1. Family, Device & Board Settings
The following options are available in the Family, Device & Board Settings
page of the New Project Wizard. Specify these options to locate and deploy a
validated design example targeting a specific board as a starting point for
your FPGA design project. Some options are only available from File Open
Example Project
Table 2.
Family, Device & Board Settings Page Options
Option Select the type of project to create
What is the working directory for this project?
Description
· Empty–create a new empty FPGA design project to which you add all design
files, settings, and constraints.
· Design example–create a new project from an existing design example. You can
access installed or online available design examples.
Specifies the directory where you want to extract and deploy the design
example.
Find Options
Allows you to filter design example search results by one of the following
facets:
· Load from >Pre-installed design examples–specifies that search includes
examples installed with the Intel Quartus Prime software.
· Load from > User downloaded design examples–search includes design examples
that you download or your own design examples that you store in a local
repository.
· Load from > Online design examples–search includes design examples hosted
online, including examples from the Intel FPGA Design Store.
· Family–search only includes design examples for the device families that you
specify. You can specify multiple values.
· Quartus Prime version–search only includes design examples that support the
Intel Quartus Prime software version that you specify. You can specify
multiple pipe separated values.
· Development kit–search only includes design examples that support the Intel
FPGA development kit that you specify. You can specify multiple pipe separated
values.
More settings button
Opens the Options panel that allows you to configure the Internet Connectivity and Design Examples connection and download settings, as Design Examples Options on page 17 describes.
Reset button
Resets the Find Options to default settings.
continued…
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Option Legend panel
Filter text box Search results list Details panel Design Store button
Description
Displays the meaning of design example status icons in the search results.
Design example status is validated (checkmark icon), unvalidated (question
mark icon), or unsupported for the current Intel Quartus Prime software
version (x icon).
Specifies a text string to further filter design example search results
according to any text string you specify.
Displays the design examples, status, and location that match your search
filters.
Displays a detailed description and diagram of the selected design example.
Opens the Design Store website in your default web browser from which you can
download available Intel FPGA validated design examples.
2.1.1.1.2. Accessing Pre-Installed Design Examples
The Intel Quartus Prime software installation includes design examples for
your immediate use.
You can access the pre-installed design examples while using the Intel Quartus
Prime software using the following methods: · Click File New Project Wizard
Family, Device & Board Settings page. · Click Open Example Project on the Home
tab (Help Home). · Click File Open Example Project.
To create a new project based on pre-installed design examples, follow these
steps Intel Quartus Prime Pro Edition software: 1. Click File Open Example
Project. The Design Example page of the New
Project Wizard opens. 2. For What is the working directory for this project?,
specify the directory
location to store your project files.
Figure 6. Find Options Locate Pre-Installed Design Example
3. Under Find Options, specify the following settings to filter the list of design examples for the target device and board. Also refer to Family, Device & Board Settings on page 13.
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a. In Load from, select the Pre-Installed design examples, repository. b. In
Family, select your target FPGA device family. c. In Intel Quartus Prime
version, select the software version. d. In Development kit, select the target
kit or board. 4. Under Design name, select the design example to base your
project on. 5. Click Next, and then click Finish. The design extracts to the
working directory and opens in the Intel Quartus Prime software.
2.1.1.1.3. Accessing Online Design Examples
You can create a new project based on a design example that you access from an
online repository. To use this method, you may need to specify a proxy server
for access and the download path.
To create a new project in the Intel Quartus Prime software based on online
design examples, follow these steps: 1. Click File Open Example Project. The
Design Example page of the New
Project Wizard opens. 2. For What is the working directory for this project?,
specify the directory
location to store your project files. 3. Click the More Settings button. The
Options dialog box opens with the Internet
Connectivity tab open by default.
Figure 7. Intel Quartus Prime Software Internet Connectivity Settings
4. If your internet connection requires a proxy server (using VPN), turn on
the Access online design examples using a proxy server option, and then
specify your proxy Address, Port, User name, and Password. If your internet
connection does not require a proxy server, skip this step.
5. On the Design Example Search Locations tab, specify the Download path for
download of the design example .par file.
6. Click OK.
7. Under Find Options, specify the following settings. Also refer to Family,
Device & Board Settings on page 13.
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Figure 8.
a. In Load from, select Downloaded design examples. b. In Family, Intel
Quartus Prime version, and Development kit fields
select the values to match your target design and board. 8. In the design
example list, select the design that you want to deploy.
Online Intel Agilex 7 – I/O PLL Reconfiguration Design
9. Click Next, and then click Finish. The design extracts to the working directory and opens in the Intel Quartus Prime software.
Internet Connectivity Options
You can specify the following internet connectivity options that determine how
the Intel Quartus Prime software connects to the internet for various
functions, such as accessing Help and design examples, with either of the
following:
· Click Tools Options Internet Connectivity
Or
· Click More Settings on the Design Example page of the New Project Wizard
(File New Project Wizard).
The following options are available on the Internet Connectivity options page.
Table 3.
Internet Connectivity Options
Option
Description
Web browser
Specifies the web browser that deploys when the Intel Quartus Prime software accesses the internet, including the Intel FPGA Design Store web page. Enable Use custom web browser to specify the path to your preferred supported web browser.
Proxy server
Specify options if connecting to the internet through a proxy server. To
access online design examples specify the appropriate option:
· Access online design examples using a proxy server–turn on this option if
you are connected to the internet through a VPN. Turn off this option if you
are not connected to the internet through a VPN (such as connection through a
private network).
Intel Quartus Prime Pro Edition User Guide: Getting Started 16
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Figure 9. Internet Connectivity Page
Related Information Design Example Options Page on page 17
Design Examples Options
You can click the following to specify options that determine how the Intel
Quartus Prime software accesses available design examples.
· Click File New Project Wizard and then click the More Settings button on the Design Example page of the New Project Wizard.
Table 4.
Design Examples Options
Option
Description
Design Example search directory
Specifies the local directories that the Intel Quartus Prime software searches for design examples. This setting determines which directories you include in search when using the New Project Wizard to start a project from an existing design example. Click Add, Remove, Up, or Down to change the search order and contents in the Directories list.
Directories
Lists the various directories that you include in the design example search path for the New Project Wizard.
Download path
Specifies the path for download of online design examples.
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Figure 10. Design Examples Page
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2.1.1.1.4. Accessing Downloaded Design Examples
You can create a new project from a design example that you have previously
downloaded. Download a design example .par file from an online repository
(such as the Intel FPGA Design Store) into your working directory. Designs
that you create yourself and store in a local drive also appear as downloaded
examples.
To create a new project based on downloaded design examples, follow these
steps: 1. Download a design example, as Accessing Online Design Examples on
page 15
describes.
Figure 11. Open Example Project Icon on Home Page
2. Click the Open Example Project icon on the Intel Quartus Prime Pro Edition
Home page. The Design Example page of the New Project Wizard opens.
3. For What is the working directory for this project?, specify the directory
location to store your project files.
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4. Under Find Options, specify the following settings. Refer to Family,
Device & Board Settings on page 13. a. In Load from, select Downloaded design
examples. b. In Family, Intel Quartus Prime version, and Development kit
fields select the values to match your target design and board.
5. In the design example list, select the design that you want to deploy.
Figure 12. Downloaded Intel Agilex 7 I/O PLL Reconfiguration Design
6. Click Next, and then click Finish. The design extracts to the working
directory and opens in the Intel Quartus Prime software.
2.1.1.2. Specifying a Target Board for the Project You can specify the target
for a new project in the New Project Wizard, or you can specify a target board
for an existing project by clicking Assignments Device. To specify a target
board for an existing project, follow these steps: 1. Click Assignments
Device. The Device dialog box appears. 2. Click the Board tab. The Board tab
allows you to target a specific FPGA device board, rather than just a specific
FPGA device.
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Figure 13. Board Tab Settings
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3. In the Family, Intel Quartus Prime version, and Development kit fields,
select the values to match your target design and board.
4. Click the desired board in the list. The board details appear in the right
pane. 5. Click OK. Your project now targets the specified board and device.
2.2. Viewing Basic Project Information
View basic information about your project in the Project Navigator, the Tasks
pane, Compilation Dashboard, Report panel, and Messages window.
Figure 14. Project Navigator Hierarchy, Files, Design Units, and IP Components
Tabs
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The Project Navigator
The Project Navigator (View Project Navigator) displays the elements of your project, such as the design files, IP components, and your project hierarchy (after elaboration). Right-click in the Project Navigator to locate the elements of your project. Project information appears on the Files, Hierarchy, Design Units, and IP Components tabs.
Table 5.
Project Navigator Tabs
Project Navigator Tab
Description
Files
Lists all design files in the current project. Right-click design files in this tab to run these commands: · Open the file · Remove the file from project · View file Properties
Hierarchy
Provides a visual representation of the project hierarchy, specific resource usage information, and device and device family information. Right-click items in the hierarchy to Locate, Set as Top-Level Entity, or define Logic Lock regions or design partitions.
Design Units
Displays the design units in the project. Right-click a design unit to Locate in Design File.
IP Components
Displays the design files that make up the IP instantiated in the project, including Intel FPGA IP, Platform Designer components, and third-party IP. Click Launch IP Upgrade Tool from this tab to upgrade outdated IP components.
Project Tasks Pane
The Tasks pane (View Tasks) launches common project tasks, such as creating
design files, adding IP, running compilation, and device programming.
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Figure 15. Tasks Pane
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Create, open, or add design files
Assign device, global settings, I/Os, entity settings
Debug and Timing Closure
Add IP or Systems
Run Compiler and View Reports
Device Programming and Project Archive
2.2.1. Using the Compilation Dashboard
The Compilation Dashboard provides immediate access to settings, controls, and
reporting for each stage of the compilation flow.
The Compilation Dashboard appears by default when you open a project, or you
can click Compilation Dashboard in the Tasks window to re-open it.
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Figure 16. Compilation Dashboard
Snapshot Reports/Analysis Runs Module(s)
Opens Settings
Full Compilation Modules
Enables Optional Module
· Click the Pencil icon to edit settings for that stage of the compilation
flow. · Click any Compiler stage to run one or more Compiler stage.
You can click a Compiler stage to resume an interrupted compilation flow
provided no compilation settings have changed from the initial start of the
compilation flow. · Click the Report, RTL Viewer, Technology Map Viewer,
Timing Analyzer, or Snapshot Viewer icons for analysis of stage results. As
the Compiler progresses through the flow, the dashboard updates the status of
each module, and enables icons that you can click for reports and analysis.
The dashboard is also updated if you run your compilation flow from a command
line with the quartus_sh –flow command.
2.2.2. Viewing Project Reports
The Compilation Report panel updates dynamically to display detailed reports
during project processing. To access Compilation Reports, click (Processing
Compilation Report). Review the detailed information in these the compilation
reports to determine correct implementation. Right-click report data to locate
and edit the source in project files.
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Intel Quartus Prime Pro Edition User Guide: Getting Started 23
Figure 17. Compilation Report
Selected Report
Synthesis Reports
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2.2.3. Viewing Project Messages
The Messages window (View Messages) displays information, warning, and error
messages about Intel Quartus Prime processes. Right-click messages to locate
the source or get message help. · Processing tab–displays messages from the
most recent process · System tab–displays messages unrelated to design
processing · Find–locates specific messages
Figure 18. Messages Window
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2.2.3.1. Viewing Synthesis Warning Messages
Warning messages may contain hierarchies. In Compilation Report Synthesis
Messages window, you can view hierarchical warning messages up to any level
including the parent and child messages. For each message, you can view its
source, file location, line number, and message ID by selecting appropriate
column under Message Column (right-click on a message in the Message panel as
shown in the following image and click Message Column).
Figure 19. Synthesis Warning Messages (Two levels)
Figure 20. Example of Synthesis Warning Messages With Three Levels
Note:
In Compilation Report Synthesis Warning Messages, you can view a comprehensive
list of synthesis warning messages for each source file included in your
design. You can view all child warning messages hidden within a parent warning
message by expanding the collapsible rows. To view the location of each
warning, perform these steps:
1. Right-click on the message.
2. Select the Locate Node option.
3. Select the desired tool to view the node.
In the source file-specific warning messages window, messages are hierarchical
in nature and display up to three levels. If the warning messages go deeper
than three levels, use the Message (View Messages) window to view them.
In the source file-specific warning messages window, hierarchical messages are
displayed with message IDs and sample warning messages that are a combination
of the parent and child messages.
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Figure 21. Synthesis Warning Messages for Each Source File
2.2.3.2. Suppressing Message Display
You can suppress display of unimportant messages from the Messages window, so
that you can focus on the messages that are important to you. To suppress one
or more messages from displaying in the Messages window, right-click the
message, and then click any of the following commands:
· Suppress Message–suppresses all messages that match the exact text you
specify.
· Suppress Messages with Matching ID–suppresses all messages that match the
message ID number you specify, ignoring variables.
· Suppress Messages with Matching Keyword–suppresses all messages that match
the keyword or hierarchy you specify.
· Message Suppression Manager–allows you to create and edit message
suppression rules. You can define message suppression rules by message text,
message ID number, or keyword.
Note:
· You cannot suppress error or Intel legal agreement messages.
· Suppressing a message also suppresses any submessages.
· A root message does not display if you suppress all of the root message’s
submessages.
· Message suppression is project revision-specific. Derivative project
revisions inherit any suppression.
· You cannot edit messages or suppression rules during compilation.
· Messages are written to stdout when you use command-line executables.
Intel Quartus Prime Pro Edition User Guide: Getting Started 26
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Figure 22. Message Suppression Manager
Suppressing Messages by Design Entity
You can optionally suppress messages by design entity without modifying HDL.
Entitybased message suppression can be helpful to eliminate insignificant
warnings for specific IP components or design entities that may be obscuring
other more important warnings.
To suppress messages by design entity, add the following line to the project
.qsf, or to the .qip file for stand-alone IP components:
set_global_assignment -name MESSAGE_DISABLE -entity
2.2.3.3. Promoting Critical Warnings to Errors
You can promote critical warnings to errors so that the compilation flow halts
on receiving the critical warnings as it does with an errors. All critical
warnings are supported.
You can only promote the message IDs on open projects. 1. In the Message
dialog box, right-click on the critical warning you want to promote
to an error. 2. Click Message Promotion Promote Critical Message ID to Error
The software now treats the critical warning as an error. 3. To clear all
promotions, click Message Promotion Clear All Message
Promotions 4. Alternatively, manually promote or demote a critical warning in
the .qsf. For
example:
set_global_assignment -name PROMOTE_WARNING_TO_ERROR 12677
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2.3. Intel Quartus Prime Project Contents
The Intel Quartus Prime software organizes your design work within a project.
You can create and compare multiple revisions of your project, to experiment
with settings that achieve your design goals. When you create a new project in
the GUI, the Intel Quartus Prime software automatically creates an Intel
Quartus Prime Project File (.qpf) for that project. The .qpf references the
Intel Quartus Prime Settings File
(.qsf). The .qsf lists the project’s design, constraint, and IP files, and
stores project-wide and entity-specific settings that you specify in the GUI.
You do not need to edit the text-based .qpf or .qsf files directly. The Intel
Quartus Prime software creates and updates these files automatically as you
make changes in the GUI.
Table 6.
Intel Quartus Prime Project Files
File Type
Contains
To Edit
Format
Project file Settings file
Project and revision name
Lists design files, entity settings, target device, synthesis directives,
placement constraints
File New Project Wizard
Assignments Settings
Intel Quartus Prime Project File (.qpf) Intel Quartus Prime Settings File (.qsf)
Quartus database
Partition database
Project compilation results
Project Export Design Quartus Database File (.qdb)
Partition compilation results
Project Export Design Partition
Partition Database File (.qdb)
Timing constraints
Logic design files
Clock properties, exceptions, Tools Timing Analyzer setup/hold
RTL and other design source File New files
Synopsys Design Constraints File (.sdc) All supported HDL files
Programming files
Device programming image and information
Tools Programmer
SRAM Object File (.sof) Programmer Object File (.pof)
IP core files
IP core variation parameterization
Tools IP Catalog
Intel Quartus Prime IP File (.ip)
Platform Designer system files
System definition
EDA tool files
Scripts for third-party EDA tools
Tools Platform Designer
Platform Designer System File (.qsys)
Assignments Settings EDA Tool Settings
Verilog Output File (.vo) VHDL Output File (.vho) Verilog Quartus Mapping File (.vqm)
Archive files
Complete project as single compressed file
Project Archive Project Intel Quartus Prime Archive File (.qar)
2.3.1. Project File Best Practices
The Intel Quartus Prime software provides various options for specifying
project settings and constraints. The following best practices help ensure
automated management and portability of your project files.
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· Avoid manually editing Intel Quartus Prime data files, such as the Intel
Quartus Prime Project File (.qpf), Intel Quartus Prime Settings File (.qsf),
Quartus IP File (.ip), or Platform Designer System File (.qsys). Syntax errors
in these files cause errors during compilation. For example, the software may
ignore improperly formatted settings and assignments.
· Do not compile multiple projects into the same directory. Instead, use a
separate directory for each project.
· By default, the Intel Quartus Prime software saves all project output files,
such as Text-Format Report Files (.rpt), in the project directory. If you want
to change the location of output files, instead of manually moving project
output files, click Assignments Settings Compilation Process Settings, and
specify the Save project output files in specified directory option.
2.4. Managing Project Settings
The New Project Wizard guides you to make initial project settings when you
setup a new project. You can modify these and other global project settings in
the Settings and Device dialog boxes, respectively. The .qsf stores the
settings for each project revision. The optimization of these project settings
helps the Compiler to generate programming files that meet or exceed your
specifications.
Global Project Settings
To access global project settings, click Assignments Settings, or click
Settings on the Tasks pane.
Figure 23. Settings Dialog Box for Global Project Settings
The Settings dialog box provides access to settings that control project
design files, synthesis, Fitter, and timing constraints, operating conditions,
EDA tool file generation, programming file generation, and other project-level
settings.
Additionally, the Assignment Editor (Assignments Assignment Editor) provides a
spreadsheet-like interface for specifying instance-specific settings and
constraints.
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Figure 24. Assignment Editor
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2.4.1. Optimizing Project Settings
Optimize project settings to meet your design goals.
The Intel Quartus Prime Design Space Explorer II iteratively compiles your
project with various setting combinations to find the optimal settings for
your goals. Alternatively, you can create a project revision or project copy
to manually compare various project settings and design combinations.
2.4.1.1. Optimize Settings with Design Space Explorer II
Use Design Space Explorer II (Tools > Launch Design Space Explorer II) to find
optimal project settings for resource, performance, or power optimization
goals. Design Space Explorer II (DSE II) processes your design using various
setting and constraint combinations, and reports the best settings for your
design.
DSE II attempts multiple seeds to identify one meeting your requirements. DSE
II can run different compilations on multiple computers in parallel to
streamline timing closure.
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Figure 25. Design Space Explorer II
2.4.1.2. Optimize Settings with Project Revisions
You can save multiple, named project revisions within your Intel Quartus Prime
project (Project > Revisions). Each project revision captures a unique set of
project settings and constraints, while using the same set of logic design
files.
Use revisions to experiment with different settings while preserving the
original. Optimize different revisions for separate applications:
· Create a unique revision to optimize a design for different criteria, such
as by area in one revision and by fMAX in another revision.
· When you create a new revision the default Intel Quartus Prime settings
initially apply.
· Create a revision of a revision to experiment with settings and constraints.
The child revision includes all the assignments and settings of the parent
revision.
You create, delete, and edit revisions in the Revisions dialog box. Each time
you create a new project revision, the Intel Quartus Prime software creates a
new .qsf using the revision name.
To compare each revision’s synthesis, fitting, and timing analysis results
side-by-side, click Project > Revisions and then click Compare. In addition to
viewing the compilation Results of each revision, you can also compare the
Assignments for each revision. This comparison reveals how different
optimization options affect your design.
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Intel Quartus Prime Pro Edition User Guide: Getting Started 31
Figure 26. Comparing Project Revisions
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Related Information
Project Revision Commands on page 53
2.4.1.3. Back-Annotate Optimized Assignments
The Compiler maps the elements of your design to specific device resources
during fitting. After compilation, you can back-annotate (copy) the Compiler’s
resource assignments to preserve that same implementation in subsequent
compilations. Backannotation can simplify timing closure by allowing you to
lock down placement of your optimized results.
Locking down placement of large blocks related to Clocks, RAMs, and DSPs can
produce higher fMAX with less noise. Large blocks like RAMs and DSPs have
heavier connectivity than regular LABs, complicating movement during
placement. When a seed produces good results from suitable RAM and DSP
placement, you can capture that placement with back-annotation. Subsequent
compiles can then benefit from the high quality RAM and DSP placement from the
good seed.
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Figure 27. Back-Annotate Assignments Dialog Box
Assignment Type to Back-Annotate
Back-Annotate Only Nodes Matching Name Filter Assignment Storage Location
Note:
To back-annotate (copy) the device resource assignments from the last
compilation to the project .qsf (or to a Tcl file) for use in the next
compilation:
1. Run a full compilation, or run the Fitter through at least the Place
stage. 2. Click Assignments Back-Annotate Assignments.
3. Under Assignments to back-annotate, specify whether you want to preserve
Pin assignments, RAM assignments, DSP assignments, Clock assignments, and
Clock Spine assignments in the back-annotation.
4. In Filter, specify a text string (including wildcards) if you want to
filter backannotated assignments by entity name.
5. Under Output, specify whether to save the back-annotated assignments to
the .qsf or to a Tcl file. A default Tcl file name displays.
Alternatively, you can run back-annotation with the following quartus_cdb
executable. The Shell command field displays the shell command constructed by
the options that you specify in the GUI.
quartus_cdb chiptrip_nf –back_annotate –pin –ram –dsp –clocks –spines –file
“
Check available arguments by running quartus_cdb
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2.5. Managing Logic Design Files
The Intel Quartus Prime software helps you create and manage the logic design
files in your project. Logic design files contain the logic that implements
your design. When you add a logic design file to the project, the Compiler
automatically includes that file in the next compilation. The Compiler
synthesizes your logic design files to generate programming files for your
target device.
The Intel Quartus Prime software includes full-featured schematic and text
editors, as well as HDL templates to accelerate your design work. The Intel
Quartus Prime software supports VHDL Design Files (.vhd), Verilog HDL Design
Files (.v), SystemVerilog (.sv) and schematic Block Design Files (.bdf). In
addition, you can combine your logic design files with Intel and third-party
IP core design files, including combining components into a Platform Designer
system (.qsys).
The New Project Wizard prompts you to identify logic design files. Add or
remove project files by clicking Project > Add/Remove Files in Project. View
the project’s logic design files in the Project Navigator.
Figure 28. Design and IP Files in Project Navigator
Right-click files in the Project Navigator to: · Open and edit the file ·
Remove File from Project · Set as Top-Level Entity for the project revision ·
Create a Symbol File for Current File for display in schematic editors · Edit
file Properties
2.5.1. Including Design Libraries
Include design files libraries in your project. Specify libraries for a single
project, or for all Intel Quartus Prime projects. The .qsf stores project
library information.
The quartus2.ini file stores global library information.
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1. Click Assignment > Settings. 2. Click Libraries and specify the Project
Library name or Global Library name.
Alternatively, you can specify project libraries with SEARCH_PATH in the .qsf,
and global libraries in the quartus2.ini file.
Related Information Design Library Migration Guidelines on page 48
2.5.2. Creating a Project Copy
Click Project > Copy Project to create a separate copy of your project, rather
than just a revision within the same project.
The project copy includes separate copies of all design files, any .qsf files,
and project revisions. You can use this technique to optimize project copies
for different applications that require design file differences. For example,
you can optimize one project to interface with a 32-bit data bus, and optimize
a project copy to interface with a 64-bit data bus.
2.6. Managing Timing Constraints
Apply appropriate timing constraints to correctly optimize fitting and analyze
timing for your design. The Fitter optimizes the placement of logic in the
device to meet your specified timing and routing constraints.
Figure 29. Timing Analyzer
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Specify timing constraints in the Timing Analyzer (Tools > Timing Analyzer),
or in an .sdc file. Specify constraints for clock characteristics, timing
exceptions, and external signal setup and hold times before running analysis.
The Timing Analyzer reports detailed information about the performance of your
design compared with constraints in the Compilation Report panel.
Save the constraints you specify in the GUI in an industry-standard Synopsys
Design Constraints File (.sdc). You can subsequently edit the text-based .sdc
file directly. If you refer to multiple .sdc files in a parent .sdc file, the
Timing Analyzer reads the .sdc files in the order you list.
2.7. Integrating Other EDA Tools
You can optionally integrate supported EDA synthesis, netlist partitioning, simulation, and signal integrity verification tools into the Intel Quartus Prime design flow.
The Intel Quartus Prime software supports input netlist files from supported
EDA
synthesis tools. The Compiler’s EDA Netlist Writer module (quartus_eda) can
automatically generate output files for processing in other EDA tools. The EDA
Netlist Writer runs optionally as part of a full compilation, or you can run
EDA Netlist Writer separately from the GUI or at the command line. The
following functions are available to simplify EDA tool integration:
Table 7.
EDA Tool Integration Functions
EDA Integration Task
EDA Integration Function
Specify settings for generation of output files for processing in other EDA
tools.
Generate output files for processing in other EDA tools.
Click Assignments Settings EDA Tool Settings to specify options for supported
tools.
Click Processing Start Start EDA Netlist Writer (or run quartus_eda) to
generate files.
Compile RTL and gate-level simulation model libraries Click Tools Launch Simulation Library Compiler to compile for your device, supported EDA simulators, and design simulation libraries easily. language.
Generate EDA tool-specific setup scripts to compile, elaborate, and simulate Intel FPGA IP models and simulation model library files.
Specify options for Simulation file output when generating Intel FPGA IP with IP parameter editor.
Generate files that allow supported EDA tools to perform netlist modifications, such as adding new modules, partitioning the netlist, and changing module connectivity.
Use the quartus_eda resynthesis command to generate a
Verilog Quartus Mapping File (.vqm) that contains a node-level (or atom)
representation of the netlist in standard structural Verilog RTL.
Include files generated by other EDA design entry or synthesis tools in your project as synthesized design files.
Click Project Add/Remove Files In Project to add supported Design File files from other EDA tools.
2.8. Exporting Compilation Results
The Intel Quartus Prime Compiler writes the results to a set of database
files. You can run a command to export the compilation results database as a
single Quartus Database File (.qdb).
After running design compilation, the exported .qdb file contains the data to
reproduce similar compilation results in another project, or in a later
software version. You can export your project’s compilation results database
for import to another project or migration to a later Intel Quartus Prime
software version.
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You can export the .qdb for your entire project or for a design partition that
you define in your project. When migrating the database for an entire project,
you can export the compilation database in a version-compatible format to
ensure compatibility for import to a later software version. Although you
cannot directly read
the contents of the .qdb file after export, you can view attributes of the
database file in the Quartus Database File Viewer.
Table 8.
Exporting Compilation Results
To Export Compilation Results
For
Method
Complete Design
Click Project Export Design
Design Partition
Click Project Export Design Partition
Description
Saves compilation results for the current project revision in a version-
compatible Quartus database file (.qdb) that you can import to another project
or migrate to a later version of the Intel Quartus Prime software. You can
export the results for the synthesized or final compilation snapshot. Note:
Not supported for Intel Agilex 7 devices.
Saves compilation results for a design partition as a Partition Database File
(.qdb) that you can import to another project using the same version of the
Intel Quartus Prime software. You can export the results for the synthesized
or final compilation snapshot.
Related Information Creating Database-Only Archives on page 52
2.8.1. Exporting a Version-Compatible Compilation Database
You can export a project compilation database to a format that ensures versioncompatibility with a later version of the Intel Quartus Prime software. The Intel Quartus Prime Pro Edition software version supports export of version-compatible databases for the following software versions and devices:
Table 9.
Version-Compatible Compilation Database Support
The first table column indicates the first version to support version-
compatible compilation database export for the specified devices.
Note:
· Database import supports two major versions back. For example, a database
that you export from version 19.3, you can then import using version 19.3,
20.1, and 20.3. However, you cannot import version 19.3 to 21.1.
· You can export from any version that follows a supported version, if the
version still supports the devices.
First Version with ‘Export Design’ Support
Intel Stratix 10 and Intel Agilex 7 Devices
18.0
No Support.
18.1
· 1SG250L · 1SG280H_S2 · 1SG280L · 1SG280L_S3 · 1SX250L · 1SX280L · 1SX280L_S3
Intel Arria 10 and Intel Cyclone 10 GX Devices
Supports all devices. Supports all devices.
continued…
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First Version with ‘Export Design’ Support
Intel Stratix 10 and Intel Agilex 7 Devices
19.1
· 1SM16BH · 1SM21BH · 1SM16CH · 1SM21CH · 1SM21KH · 1SM16KH · 1SM21LH · 1SM16LH
19.3
· 1SG10MH_U1 · 1SG10MH_U2 · 1ST250E · 1ST280E · 1SM16E · 1SM21E · 1ST165E · 1ST210E · 1SG166H · 1SG211H
20.1
· 1SD280P · 1ST040E · 1ST085E · 1ST110E
20.3
· 1SD21BP · 1SG040H · 1SX040H
20.4
· 1SN21BH · 1SN21CE
Intel Arria 10 and Intel Cyclone 10 GX Devices
Supports all devices.
Supports all devices.
Supports all devices. Supports all devices. Supports all devices.
1. In the Intel Quartus Prime software, open the project that you want to
export.
2. Generate synthesis or final compilation results by running one of the
following commands:
· Click Processing Start Start Analysis & Synthesis to generate synthesized
compilation results.
· Click Processing Start Compilation to generate final compilation results.
3. Click Project Export Design. Select the synthesized or final Snapshot.
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Figure 30. Export Design Dialog Box
4. Specify a name for the Quartus Database File to contain the exported
results, and click OK.
5. To include the exported design’s settings and constraint files, copy the
.qsf and .sdc files to the import project directory.
2.8.2. Importing a Version-Compatible Compilation Database
Follow these steps to import a project compilation database into a newer
version of the Intel Quartus Prime software: 1. Export a version-compatible
compilation database for a complete design, as
Exporting a Version-Compatible Compilation Database on page 37 describes. 2.
In a newer version of the Intel Quartus Prime software, open the original
project.
Click Yes if prompted to open a project created with a different software
version. 3. Click Project Import Design and specify the Quartus Database File.
To
remove previous results, turn on Overwrite existing project’s databases
Figure 31. Import Design Dialog Box
4. Click OK. When you compile the imported design, run only Compiler stages
that
occur after the stage the .qdb preserves, rather than running a full
compilation. For example, if you import a version-compatible database that
contains the synthesized snapshot, start compilation with the Fitter
(Processing Start Start Fitter). If you import a version-compatible database
that contains the final snapshot, start compilation with Timing Analysis
(Signoff) (Processing Start Start Timing Analysis (Signoff)).
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2.8.3. Creating a Design Partition
A design partition is a logical, named, hierarchical boundary that you can
assign to an instance in your design. Defining a design partition allows you
to optimize and lock down the compilation results for individual blocks. You
can then optionally export the compilation results of a design partition for
reuse in another context, such as reuse in another project.
Figure 32. Design Partitions in Design Hierarchy
Root Partition
A
B
C
D
E
F
Partition B
Partition F
Follow these steps to create and modify design partitions:
1. In the Intel Quartus Prime software, open the project that you want to partition.
2. Generate synthesis or final compilation results by running one of the following commands:
· Click Processing Start Start Analysis & Synthesis to generate synthesized compilation results.
· Click Processing Start Compilation to generate final compilation results.
3. In the Project Navigator, right-click an instance in the Hierarchy tab, click Design Partition Set as Design Partition.
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Figure 33. Creating a Design Partition from the Project Hierarchy
4. To view and edit all design partitions in the project, click Assignments
Design Partitions Window.
Figure 34. Design Partitions Window
5. Specify the properties of the design partition in the Design Partitions Window. The following settings are available:
Table 10. Design Partition Settings
Option
Description
Partition Name
Specifies the partition name. Each partition name must be unique and consist of only alphanumeric characters. The Intel Quartus Prime software automatically creates a top-level (|) “root_partition” for each project revision.
Hierarchy Path
Specifies the hierarchy path of the entity instance that you assign to the partition. You specify this value in the Create New Partition dialog box. The root partition hierarchy path is |.
Type
Double-click to specify one of the following partition types that control how
the Compiler processes and implements the partition:
· Default–Identifies a standard partition. The Compiler processes the
partition using the associated design source files.
· Reconfigurable–Identifies a reconfigurable partition in a partial
reconfiguration flow. Specify the Reconfigurable type to preserve synthesis
results, while allowing refit of the partition in the PR flow.
· Reserved Core–Identifies a partition in a block-based design flow that is
reserved for core development by a Consumer reusing the device periphery.
Preservation Level
Specifies one of the following preservation levels for the partition:
continued…
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Option
Empty Partition Database File Entity Re-binding
Color Post Synthesis Export File Post Final Export File
Description
· Not Set–specifies no preservation level. The partition compiles from source
files. · synthesized–the partition compiles using the synthesized snapshot. ·
final–the partition compiles using the final snapshot. With Preservation Level
of synthesized or final, changes to the source code do not appear in the
synthesis.
Specifies an empty partition that the Compiler skips. This setting is
incompatible with the Reserved Core and Partition Database File settings for
the same partition. The Preservation Level must be Not Set. An empty partition
cannot have any child partitions.
Specifies a Partition Database File (.qdb) that the Compiler uses during
compilation of the partition. You export the .qdb for the stage of compilation
that you want to reuse (synthesized or final). Assign the .qdb to a partition
to reuse those results in another context.
· PR Flow–specifies the entity that replaces the default persona in each
implementation revision.
· Root Partition Reuse Flow –specifies the entity that replaces the reserved
core logic in the consumer project.
Specifies the color-coding of the partition in the Chip Planner and Design
Partition Planner displays.
Automatically exports post-synthesis compilation results for the partition to
the specified .qdb file each time Analysis & Synthesis runs. You can
automatically export any design partition that does not have a preserved
parent partition, including the root_partition.
Automatically exports post-final compilation results for the partition to the
specified .qdb file each time the final stage of the Fitter runs. You can
automatically export any design partition that does not have a preserved
parent partition, including the root_partition.
2.8.4. Exporting a Design Partition
The following steps describe export of design partitions that you create in
your project.
When you compile a design containing design partitions, the Compiler can
preserve a synthesis or final snapshot of results for each partition. You can
export the synthesized or final compilation results for individual design
partitions with the Export Design Partition dialog box.
If the partition includes any entity-bound .sdc files, you can include those
constraints in the .qdb. In addition, you can automate export of one or more
partitions in the Design Partitions Window.
Manual Design Partition Export
Follow these steps to manually export a design partition with the Export
Design Partition dialog box:
1. Open a project and create one or more design partitions. Creating a Design
Partition on page 40 describes this process.
2. Run synthesis (Processing Start Start Analysis & Synthesis) or full
compilation (Processing Start Compilation), depending on which compilation
results that you want to export.
3. Click Project Export Design Partition, and specify one or more options in
the Export Design Partition dialog box:
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Figure 35. Export Design Partition Dialog Box
· Select the Partition name and the compilation Snapshot for export.
· To include any entity-bound .sdc files in the exported .qdb, turn on Include
entity-bound SDC files for the selected partition.
4. Click OK. The compilation results for the design partition exports to the
file that you specify.
Automated Design Partition Export
Follow these steps to automatically export one or more design partitions
following each compilation:
1. Open a project containing one or more design partitions. Creating a Design
Partition on page 40 describes this process.
2. To open the Design Partitions Window, click Assignments Design Partitions
Window.
3. To automatically export a partition with synthesis results after each time
you run synthesis, specify the a .qdb export path and file name for the Post
Synthesis Export File option for that partition. If you specify only a file
name without a path, the file exports to the output_files directory after
compilation.
4. To automatically export a partition with final snapshot results each time
you run the Fitter, specify a .qdb file name for the Post Final Export File
option for that partition. If you specify only a file name without a path, the
file exports to the output_files directory after compilation.
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Figure 36. Specifying Export File in Design Partitions Window
.qsf Equivalent Assignment:
set_instance_assignment -name EXPORT_PARTITIONSNAPSHOT<FINAL|SYNTHESIZED>
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Figure 37. Partition Database File Setting in Design Partitions Window
6. Specify any other properties of the design partition in the Design
Partitions Window. The Compiler uses the partition’s assigned .qdb as the
source.
2.8.6. Viewing Quartus Database File Information Although you cannot directly
read a .qdb file, you can view helpful attributes about
the file to quickly identify its contents and suitability for use. The Intel
Quartus Prime software automatically stores metadata about the project of
origin when you export a Quartus Database File (.qdb). You can then use the
Quartus Database File Viewer to display the attributes of any of these .qdb
files. Figure 38. Quartus Database File Viewer
Follow these steps to view the attributes of a .qdb file:
1. In the Intel Quartus Prime software, click File Open, select Design Files
for Files of Type, and select a .qdb file.
2. Click Open. The Quartus Database File Viewer displays project and resource
utilization attributes of the .qdb.
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Alternatively, run the following command-line equivalent:
quartus_cdb –extract_metadata –file <archive_name.qdb> –type quartus –dir
2.8.6.1. QDB File Attribute Types
The Quartus Database Viewer can display the following attributes of a .qdb file:
Table 11. QDB File Attributes
QDB Attribute Types
Attribute
Example
Project Information
Contents
Partition
Date
Thu Jan 23 10:56:23 2018
Device
10AX016C3U19E2LG
Entity (if Partition)
Counter
Family
Arria 10
Partition Name
root_partition
Revision Name
Top
Revision Type
PR_BASE
Snapshot
synthesized
Version
18.1.0 Pro Edition
Version-Compatible
Yes
Resource Utilization (exported for partition QDB only)
For synthesized snapshot partition lists data from the Synthesis Resource Usage Summary report.
Average fan-out.16 Dedicated logic registers:14 Estimate of Logic utilization:1 I/O pins:35 Maximum fan-out:2 Maximum fan-out node:counter[23] Total DSP Blocks:0 Total fan-out:6 …
For the final snapshot partition, lists data from the Fitter Partition Statistics report.
Average fan-out:.16 Combinational ALUTs: 16 I/O Registers M20Ks …
2.8.7. Clearing Compilation Results
You can clean the project database if you want to remove prior compilation
results for all project revisions or for specific revisions. For example, you
must clear previous compilation results before importing a version-compatible
database to an existing project.
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1. Click Project > Clean Project. 2. Select All revisions to clear the
databases for all revisions of the current project,
or specify a Revision name to clear only the revision’s database you specify.
3. Click OK. A message indicates when the database is clean. Figure 39. Clean
Project Dialog Box Cleans the Project Database
2.9. Migrating Projects Across Operating Systems
Consider the following cross-platform issues when moving your project from one
operating system to another (for example, from Windows to Linux ).
2.9.1. Migrating Design Files and Libraries
Consider file naming differences when migrating projects across operating
systems.
· Use appropriate case for your platform in file path references. · Use a
character set common to both platforms. · Do not change the forward-slash (/)
and back-slash () path separators in
the .qsf. The Intel Quartus Prime software automatically changes all back-
slash () path separators to forward-slashes (/ )in the .qsf. · Observe the
target platform’s file name length limit. · Use underscore instead of spaces
in file and directory names. · Change library absolute path references to
relative paths in the .qsf. · Ensure that any external project library exists
in the new platform’s file system. · Specify file and directory paths as
relative to the project directory. For example, for a project titled
foo_design, specify the source files as: top.v, foo_folder /foo1.v, foo_folder
/foo2.v, and foo_folder/ bar_folder/bar1.vhdl. · Ensure that all the
subdirectories are in the same hierarchical structure and relative path as in
the original platform.
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Figure 40. All Inclusive Project Directory Structure
2.9.1.1. Use Relative Paths Express file paths using relative path notation
(../). For example, in the directory structure shown you can specify top.v as
../source/ top.v and foo1.v as ../source/foo_folder/foo1.v.
Figure 41. Intel Quartus Prime Project Directory Separate from Design Files
2.9.2. Design Library Migration Guidelines
The following guidelines apply to library migration across computing
platforms:
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1. The project directory takes precedence over the project libraries.
2. For Linux, the Intel Quartus Prime software creates the file in the
altera.quartus directory under the
3. All library files are relative to the libraries. For example, if you
specify the user_lib1 directory as a project library and you want to add the
/user_lib1/ foo1.v file to the library, you can specify the foo1.v file in the
.qsf as foo1.v. The Intel Quartus Prime software includes files in specified
libraries.
4. If the directory is outside of the project directory, an absolute path is
created by default. Change the absolute path to a relative path before
migration.
5. When copying projects that include libraries, you must either copy your
project library files along with the project directory or ensure that your
project library files exist in the target platform.
· On Windows, the Intel Quartus Prime software searches for the quartus2.ini
file in the following directories and order:
· USERPROFILE, for example, C:Documents and Settings
· Directory specified by the TMP environmental variable
· Directory specified by the TEMP environmental variable
· Root directory, for example, C:
2.10. Archiving Projects
You can optionally save the elements of a project in a single, compressed
Intel Quartus Prime Archive File (.qar) by clicking Project > Archive Project.
The .qar preserves RTL design, project, and settings files required to restore
the project.
Use this technique to share projects between designers, or to transfer your
project to a new version of the Intel Quartus Prime software, or to Intel
support. Optionally add compilation results, Platform Designer system files,
and third-party EDA tool files to the archive.
Related Information Project Archive Commands on page 54
2.10.1. Manually Adding Files To Archives
Follow these steps to add files to a project archive manually:
Note:
If preserving a custom component as part of an Intel Quartus Prime Archive (.qar), you must first explicitly add the component _hw.tcl file to the project to ensure that the .qar includes the component. Click Project Add/Remove Files in Project to add files to your project.
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1. Click Project Archive Project and specify the archive file name. 2. Click
Advanced. 3. Select the File set for archive or select Custom. Turn on File
subsets for the
archive. 4. Click Add and select Platform Designer system or EDA tool files.
Click OK. 5. Click Archive.
2.10.2. Archiving Projects for Service Requests
When archiving projects for a service request, include all needed file types
for proper debugging by customer support.
To identify and include appropriate archive files for an Intel service
request: 1. Click Project > Archive Project and specify the archive file name.
2. Click Advanced. 3. In File set, select Service request to include files for
Intel Support.
· Project source and setting files (.v, .vhd, .vqm, .qsf, .sdc, .qip, .qpf,
.cmp)
· Automatically detected source files (various) · Programming output files
(.jdi, .sof, .pof) · Report files (.rpt, .pin, .summary, .smsg) 4. Click OK,
and then click Archive.
Figure 42. Archiving Project for Service Request
2.10.3. Archiving Projects for External Revision Control
Your project may involve different team members with distributed
responsibilities, such as sub-module design, device and system integration,
simulation, and timing closure. In such cases, it may be useful to track and
protect file revisions in an external revision control system.
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While Intel Quartus Prime project revisions preserve various project setting and constraint combinations, external revision control systems can also track and merge RTL source code, simulation testbenches, and build scripts. External revision control supports design file version experimentation through branching and merging different versions of source code from multiple designers. Refer to your external revision control documentation for setup information.
2.10.3.1. Project Files to Include In External Revision Control
When archiving Intel Quartus Prime projects for external source control, The
Source control setting in Advanced Archive Settings dialog box is preset to
include all appropriate file types for source control automatically.
Figure 43.
Advanced Archive Settings Dialog Box
Source Control File Set Automatically Selects Appropriate Files for Source
Control
Include the following file types when archiving projects for external revision control:
Table 12.
Project Files to Include In External Revision Control (Included Automatically with’ Source Control’ Archive Setting)
File Type
Description
Intel Quartus Prime project setting and assignment files
· Intel Quartus Prime Project Files (.qpf) · Intel Quartus Prime Settings Files (.qsf) · Intel Quartus Prime Pin Planner File (.ppf)
Timing constraint files
Synopsys Design Constraint Files (.sdc)
Design files
· Verilog HDL Design Files (.v) · SystemVerilog Design Files (.sv) · VHDL Design Files (.vhd) · Block Diagram/Schematic Design Files (.bdf) · Block Symbol Files (.bsf) · Verilog Quartus Mapping Files (.vqm) · Platform Designer System Files (.qsys) · State Machine Editor Files (.smf) · Tcl Script Design Files (.tcl)
System and IP files
· IP variation file (.ip) · Verilog IP design files (.v) · SystemVerilog IP design files (.sv) · VHDL IP design files (.sv)
continued…
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File Type EDA tool integration files
Description
· VHDL Component Declaration Files (.cmp) · Intel Quartus Prime IP file (.qip)
· Intel Quartus Prime Simulation IP File (.sip) · Platform Designer System
Files (.qsys) · Platform Designer connection and parameterization files
(.sopcinfo) · IP upgrade status files (.csv) · IP synthesis parameters files
(.qgsynthc) · IP simulation parameters files (.qgsimc) · Platform Designer
system exported as (.tcl).
· Verilog HDL Output Files (.vo) · VHDL Output Files (.vho) · VHDL simulation
model files (.vhd) · Verilog HDL simulation model files (.v) · Simulation
library files (cds.lib, hdl.var) · Simulation setup scripts (_setup.sh, .tcl,
.spd, .txt)
2.10.4. Creating Database-Only Archives
If your project contains sensitive RTL that you do not want to share with
Intel support, you can create a database-only archive. A database-only archive
contains only the minimum files required to run timing analysis, fitter,
assembler, and GUI designinspection tools like Chip Planner.
A database-only archive includes only the project Quartus databases and any
additional files required for compilation. It does not include RTL files.
You can review the complete list of files included in the archive in a report
generated when you create a database-only archive.
Security Note:
A database-only archive does not guarantee protection for sharing your design without sharing your RTL. The RTL Netlist Viewer, Technology Map Viewer, and other views, along with the EDA Netlist Writer, are still available for projects exported using this feature.
With some effort, the original content can be reverse engineered.
To disable these features, encrypt your design. For details, see Support for the IEEE 1735 Encryption Standard on page 114.
Before creating a database-only archive, your project must have completed one
of the following compilation stages:
· Synthesis
Archives that are created after running Synthesis can be used to run the
fitter and then complete timing analysis, run the assembler, and use GUI-based
designinspection tools.
· Finalized
Archives that are created after completing a full compilation flow for your
project can be used to complete timing analysis, run the assembler, and use
GUI designinspection tools.
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To create a database-only archive, run the following command: quartus_sh
–archive_database -project
The command generates two files: a .qar file that contains the database-only
archive, and a .contents.txt file that lists files that are included in the
.qar file.
You can get command syntax details by running the following command:
quartus_sh –help=archive_database
Related Information Support for the IEEE 1735 Encryption Standard on page 114
2.11. Command-Line Interface
You can optionally use command-line executables or scripts to run project
commands, rather than using the GUI. This technique can be helpful if you have
many settings and wish to track them in a single file or spreadsheet for
iterative comparison. The .qsf supports only a limited subset of Tcl commands.
Therefore, pass settings and constraints using a Tcl script:
1. Create a text file with the extension .tcl that contains your assignments
in Tcl format.
2. Source the Tcl script file by adding the following line to the .qsf:
set_global_assignment -name SOURCE_TCL_SCR IPT_FILE
2.11.1. Project Revision Commands
create_revision Command
create_revision defines the properties of a new project revision.
create_revision
Table 13. create_revision Command Options
Option
Description
based_on (optional)
Specifies the revision name on which the new revision bases its settings.
set_current (optional)
Sets the new revision as the current revision.
-new_rev_type
Specifies a base or impl (implementation) type for a new revision.
root_partition_qdb_file
Specifies the name of a static region .qdb if already known when creating a revision.
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get_project_revisions Command get_project_revisions returns a list of all
revisions in the project. get_project_revisions
delete_revision Command delete_revision deletes the revision you specify from
your project. delete_revision
set_current_revision Command set_current_revision sets the revision you
specify as the current revision. set_current_revision -force
Related Information Optimize Settings with Project Revisions on page 31
2.11.2. Project Archive Commands
project_archive Command project_archive archives your project into a single,
compressed .qar file. project_archive
Table 14. project_archive Command Options
Options
Description
-all_revisions
Includes all revisions of the current project in the archive.
-common_directory /
Preserves original project directory structure in specified subdirectory.
-include_libraries
Includes libraries in archive.
-include_outputs
Includes output files in archive.
-use_file_set
Includes specified fileset in archive.
-version_compatible_database
Includes version-compatible database files in archive.
restore_archive Command
Restores an archived project to a destination directory with optional
overwriting of current contents.
project_restore
Related Information Archiving Projects on page 49
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2.11.3. Project Database Commands
export_database Command
export_design exports the specified project database to the .qdb file you
specify.
These commands require the quartus_cdb executable.
quartus_cdb
import_database Command
import_design imports the specified project database to the .qdb file you
specify.
quartus_cdb
export_block Command
export_block exports the specified partition database to the .qdb file you
specify.
quartus_cdb -r
2.11.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
The command-line arguments to the quartus_cdb executable in the Quartus Prime
Pro software are export_design and import_design. The exported
versioncompatible design files are archived in a file (with a .qdb extension).
This differs from the Intel Quartus Prime Standard Edition software, which
writes all files to a directory.
In the Intel Quartus Prime Standard Edition software, the flow exports both
post-map and post-fit databases. In the Intel Quartus Prime Pro Edition
software, the export command requires the snapshot argument to indicate the
target snapshot to export. If the specified snapshot has not been compiled,
the flow exits with an error. In ACDS 16.0, export is limited to “synthesized”
and “final” snapshots.
quartus_cdb
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Intel Quartus Prime Pro Edition User Guide: Getting Started 55
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2.12. Managing Projects Revision History
Document Version 2023.04.03 2022.12.12
2022.03.28 2021.06.21 2021.03.29 2020.09.28 2020.05.01 2019.09.30 2018.09.24
2018.05.07
Intel Quartus Prime Version
23.1 22.4
22.1 21.2 21.1 20.3 20.1 19.3 18.1
18.0.0
Changes
· Updated product family name to “Intel Agilex 7.”
· Revised Creating a New FPGA Design Project for board-aware features. · Added
Using the Board-Aware Flow topic. · Added Creating a New Project from a Design
Example topic. · Added Family, Device & Board Settings topic. · Added
Accessing Pre-Installed Design Examples topic. · Added Accessing Online Design
Examples topic. · Added Accessing Downloaded Design Examples topic. · Added
Internet Connectivity Options topic. · Added Design Examples Options topic. ·
Added Specifying a Target Board for the Project topic.
· Removed references to obsolete Advisors from Optimizing Project Settings
topic.
· Added Viewing Synthesis Warning Messages topic. · Removed the topic
Automated Problem Reports.
· Added Version-Compatible Compilation Database Support table. · Added
“Promoting Critical Warnings to Errors” topic.
· Added “Creating Database-Only Archives” topic. · Added “Promoting Critical
Warnings to Errors” topic
· Updated “Back-Annotate Optimized Assignments” for support of pins, clocks,
RAMs, and DSPs.
· Added note about .qar file requirements to “Design Guidelines for Component
Instances” topic.
· Added “Disabling Automated Problem Reports” topic. · Added “Suppressing
Messages” topic.
· Subdivided “Exporting, Archiving, and Migrating Projects” into separate
sections.
· Described migration of full chip database in “Exporting a VersionCompatible
Compilation Database” topic.
· Described automated .qdb partition export in “Exporting a Design Partition”
topic.
· Added “Viewing Quartus Database File Information” topic. · Added “Specifying
the Target Device or Board” topic. · Divided “Introduction to Intel FPGA IP
Cores” into separate chapter. · Moved “IP Core Best Practices” topic to
Introduction to Intel FPGA IP
Cores chapter. · Moved “Factors Affecting Compilation Results” topic to Design
Compilation: Intel Quartus Prime Pro Edition User Guide.
· Initial release as chapter of Getting Started User Guide. · Revised
“Exporting a Design Partition” topic to add Include entity-
bound SDC files for the selected partition option, to add prerequisite steps,
and to remove import step covered in separate topic. · Changed title of
“Managing Team-Based Designs” to “Exporting, Archiving, and Migrating
Projects” and updated content. · Changed title of “Migrating Compilation
Results Across Software Versions” to “Exporting the Compilation Database” and
updated content.
continued…
Intel Quartus Prime Pro Edition User Guide: Getting Started 56
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2. Managing Intel Quartus Prime Projects 683463 | 2023.06.26
Document Version
Intel Quartus Prime Version
Changes
· Changed title of “Exporting the Results Database” to “Exporting a Version-
Compatible Design Compilation Database” and updated content.
· Changed title of “Importing the Results Database” to “Importing a Version-
Compatible Design Compilation Database” and updated content.
· Changed title of “Cleaning the Project Database” to “Cleaning the Project
Compilation Database.”
· Updated screenshots of IP Catalog and Parameter Editor for latest IP names.
Date 2017.11.06
2017.05.08
2016.10.31 2016.05.03
2016.02.09 2015.11.02
Version 17.1.0
17.0.0
16.1.0 16.0.0
15.1.1 15.1.0
Changes
· Revised product branding for Intel standards. · Revised topics on Intel FPGA
IP Evaluation Mode (formerly
OpenCore). · Removed -compatible attribute from export_design command
content. · Updated figure: IP Upgrade Alert in Project Navigator. · Updated IP
Core Upgrade Status table with new icons, and added
row for IP Component Outdated status.
· Added Project Tasks pane and update New Project Wizard. · Updated
Compilation Dashboard image to show concurrent analysis. · Removed Smart
Compilation option from Settings dialog box
screenshot. · Updated IP Catalog screenshots for latest GUIs. · Added topic on
Back-Annotate Assignments command. · Added Exporting a Design Partition topic.
· Removed mentions to deprecated Incremental Compilation. · Added reference to
Block-Level Design Flows.
· Added references to compilation stages and snapshots. · Removed support for
comparing revisions. · Added references to .ip file creation during Intel
Quartus Prime Pro
Edition stand-alone IP generation. · Updated IP Core Generation Output files
list and diagram. · Added Support for IP Core Encryption topic. · Rebranding
for Intel
· Removed statements about serial equivalence when using multiple processors.
· Added the “Preserving Compilation Results” section. · Added the “Migrating
Results Across Quartus Prime Software”
section and its subsections for information about importing and exporting
compilation results between different versions of Quartus Prime. · Added the
“Project Database Commands” section and its subsections.
· Clarified instructions for Generating a Combined Simulator Setup Script.
· Clarified location of Save project output files in specified directory
option.
· Added Generating Version-Independent IP Simulation Scripts topic. · Added
example IP simulation script templates for supported
simulators. · Added Incorporating IP Simulation Scripts in Top-Level Scripts
topic.
continued…
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Intel Quartus Prime Pro Edition User Guide: Getting Started 57
Date
2015.05.04
2014.12.15 2014.08.18
2014.06.30 November 2013 May 2013 June 2012 November 2011 December 2010
2. Managing Intel Quartus Prime Projects 683463 | 2023.06.26
Version
15.0.0
14.1.0 14.0a10.0
14.0.0 13.1.0 13.0.0 12.0.0 10.1.1 10.1.0
Changes
· Added Troubleshooting IP Upgrade topic. · Updated IP Catalog and parameter
editor descriptions for GUI
changes. · Updated IP upgrade and migration steps for latest GUI changes. ·
Updated Generating IP Cores process for GUI changes. · Updated Files Generated
for IP Cores and Qsys system description. · Removed references to devices and
features not supported in
version 15.1. · Changed instances of Quartus II to Intel Quartus Prime.
· Added description of design templates feature. · Updated screenshot for DSE
II GUI. · Added qsys_script IP core instantiation information. · Described
changes to generating and processing of instance and
entity names. · Added description of upgrading IP cores at the command line. ·
Updated procedures for upgrading and migrating IP cores. · Gate level timing
simulation supported only for Cyclone IV and
Stratix IV devices.
· Updated content for DSE II GUI and optimizations. · Added information about
new Assignments Settings IP
Settings that control frequency of synthesis file regeneration and automatic
addition of IP files to the project.
· Added information about specifying parameters for IP cores targeting Arria
10 devices.
· Added information about the latest IP output for version 14.0a10 targeting
Arria 10 devices.
· Added information about individual migration of IP cores to the latest
devices.
· Added information about editing existing IP variations.
· Replaced MegaWizard Plug-In Manager information with IP Catalog. · Added
standard information about upgrading IP cores. · Added standard installation
and licensing information. · Removed outdated device support level
information. IP core device
support is now available in IP Catalog and parameter editor.
· Conversion to DITA format
· Overhaul for improved usability and updated information.
· Removed survey link. · Updated information about VERILOG_INCLUDE_FILE.
Template update.
· Changed to new document template. · Removed Figure 41, Figure 46, Table
42. · Moved “Hiding Messages” to Help. · Removed references about the
set_user_option command. · Removed Classic Timing Analyzer references.
Intel Quartus Prime Pro Edition User Guide: Getting Started 58
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Design Planning
3.1. Design Planning
Design planning is an essential step in advanced FPGA design. System
architects must consider the target device characteristics in order to plan
for interface I/O, integration of IP, on-chip debugging tools, and use of
other EDA tools. Designers must consider device power consumption and
programming methods when planning the layout. You can solve potential problems
early in the design cycle by following the design planning considerations in
this chapter.
By default, the Intel Quartus Prime software optimizes designs for the best
overall results; however, you can adjust settings to better optimize one
aspect of your design, such as performance, routability, area, or power
utilization. Consider your own design priorities and trade-offs when reviewing
the techniques in this chapter. For example, certain device features, density,
and performance requirements can increase system cost. Signal integrity and
board issues can impact I/O pin locations. Power, timing performance, and area
utilization all affect one another. Compilation time is affected when
optimizing these priorities.
Determining your design priorities early on helps you to choose the best
device, tools, features, and methodologies for your design.
3.2. Create a Design Specification and Test Plan
Before you create your design logic or complete your system design, it is best
practice to create detailed design specifications that define the system,
specify the I/O interfaces for the FPGA, identify the different clock domains,
and include a block diagram of basic design functions.
In addition, creating a test plan helps you to design for verification and
ease of manufacture. For example, your test plan can include validation of
interfaces incorporated in your design. To perform any built-in self-test
functions to drive interfaces, you can use a UART interface with a Nios® II
processor inside the FPGA device.
If more than one designer contributes to the design, consider a common design
directory structure or source control system to make design integration
easier. Consider whether you want to standardize on an interface protocol for
each design block.
3.3. Plan for the Target Device or Board
Intel offers a broad portfolio of FPGA and PLD devices. The Intel device that
you select determines factors of performance, density, and board layout. To
avoid costly design changes, it is best to carefully consider and determine
the target device family early in
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the design cycle. Intel FPGA device families differ in cost, size, density,
performance, power consumption, packaging, I/O standards, and other factors.
Select the device family that best suits your most critical design
requirements.
Alternatively, you can create a system that targets a specific development
board, rather than only targeting a specific FPGA device. When you target a
specific development board, the Intel Quartus Prime software is aware of the
target board (board-aware) which accelerates the process of appropriately
configuring, connecting, and validating IP for the target board. Refer to
Using the Board-Aware Flow on page 10 for details.
Device and Board Selection Guidelines
· Refer to the Product Selector tool on the Intel website to quickly find and
compare the specifications and features of Intel FPGA devices and development
kits.
· Once you identify the target device family, refer to the device family
documentation for detailed device characteristics. View a summary of each
device’s resources by selecting a device in the Device dialog box (Assignments
Device)
· Consider whether the device family meets any requirements you have for
highspeed transceivers, global or regional clock networks, and the number of
phaselocked loops (PLLs)
· Consider the density requirements of your design. Devices with more logic
resources and higher I/O counts can implement larger and more complex designs,
but at a higher cost. Smaller devices use lower static power. Select a device
larger than what your design requires if you may want to add more logic later
in the design cycle, or to reserve logic and memory for on-chip debugging.
· Consider requirements for types of dedicated logic blocks, such as memory
blocks of different sizes, or digital signal processing (DSP) blocks to
implement certain arithmetic functions.
Related Information
Product Selector Guide Tool To help you choose your device.
3.3.1. Device Migration Planning
Determine whether you want to migrate your design to another device density to
allow flexibility when your design nears completion. You may want to target a
smaller (and less expensive) device and then move to a larger device if
necessary to meet your design requirements. Other designers may prototype
their design in a larger device to reduce optimization time and achieve timing
closure more quickly, and then migrate to a smaller device after prototyping.
If you want the flexibility to migrate your design, you must specify these
migration options in the Intel Quartus Prime software at the beginning of your
design cycle.
Selecting a migration device impacts pin placement because some pins may serve
different functions in different device densities or package sizes. If you
make pin assignments in the Intel Quartus Prime software, the Pin Migration
View in the Pin Planner highlights pins that change function between your
migration devices.
Intel Quartus Prime Pro Edition User Guide: Getting Started 60
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3.4. Plan for Intellectual Property Cores
Intel and third-party intellectual property (IP) partners offer a large
selection of standardized IP cores optimized for Intel FPGA devices. The IP
you select often affects system design and performance, especially if the FPGA
interfaces with other devices in the system. Plan which I/O interfaces or
other blocks in the system that you want to implement using IP cores. Whenever
possible, plan to incorporate these functions into your design using Intel
FPGA IP cores, many of which are available for production use in the Intel
Quartus Prime software without additional license. Figure 44. IP Catalog
Search for IP
Double-Click to Customize IP
Right-Click for IP Info
For IP cores that require additional license for production use, the Intel
FPGA IP Evaluation Mode, allows you to program the FPGA to verify the IP in
the hardware before you purchase the IP license. Refer to Introduction to
Intel FPGA IP Cores on page 76 for general information on using Intel FPGA IP
cores.
Related Information
· Introduction to Intel FPGA IP Cores on page 76
· Intel FPGA IP Portfolio Web Page For descriptions and documentation for all
available Intel FPGA and partner IP cores.
3.5. Plan for Standard Interfaces
To reduce design iterations and costly design changes, plan for use of
standard interfaces in system design. Using standard interfaces ensures
compatibility between design blocks from different design teams or vendors.
You can use the Intel Quartus Prime Interface Planner to help you accurately
plan constraints for design implementation. Use Interface Planner to prototype
interface implementations and rapidly define a legal device floorplan.
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Intel Quartus Prime Pro Edition User Guide: Getting Started 61
3. Design Planning 683463 | 2023.06.26
Standard interfaces simplify the interface logic to each design block, and
enable individual team members to test their individual design blocks against
the specification for the interface protocol to ease system integration.
You can use the Intel Quartus Prime Platform Designer system integration tool
to use standard interfaces and speed-up system-level integration. Platform
Designer components use Avalon® standard interfaces for physical connections,
allowing you to connect any logical device (either on-chip or off-chip) that
has an Avalon interface. Platform Designer allows you to define system
components in a GUI, and then automatically generates the required
interconnect logic, along with clock-crossing and width adapters.
The Avalon standard includes two interface types:
· Avalon memory-mapped–allow a component to use an address-mapped read or
write protocol that connects master components to slave components.
· Avalon streaming–enables point-to-point connections between streaming
components that send and receive data using a high-speed, unidirectional
system interconnect between source and sink ports.
Related Information
Creating a System with Platform Designer
3.6. Plan for Device Programming
You must plan for the devices and hardware that you require for programming or
configuration of the device. Comprehensive system planning includes
determining what companion devices, if any, your system requires. Your
programming or configuration method also impacts the board layout planning.
For example, some programming options require a JTAG interface connection,
requiring a JTAG chain on the board.
You can define a configuration scheme on the Configuration tab of the Device
and Pin Options dialog box. The Intel Quartus Prime software uses the settings
for the configuration scheme, configuration device, and configuration device
voltage to enable the appropriate dual purpose pins as regular I/O pins after
you complete configuration. The Intel Quartus Prime software performs voltage
compatibility checks of those pins during compilation of your design.
Intel Quartus Prime Pro Edition User Guide: Getting Started 62
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Figure 45. Intel Quartus Prime Programmer
Enables Program or Configuration
Starts Download of Configuration Data
Adds SOF File Adds RBF to Program PR region
The technical documentation for each device family describes the available configuration options.
3.7. Plan for Device Power Consumption
You can use the Intel Quartus Prime power estimation and analysis tools to estimate power consumption and guide PCB board and system design. You must accurately estimate device power consumption to develop an appropriate power budget and to design the power supplies, voltage regulators, heat sink, and cooling system. You can use the Early Power Estimator (EPE) spreadsheet to estimate power consumption before running a compilation or creating any source code. Then, you can use the Intel Quartus Prime Power Analyzer to perform a more accurate analysis after your design is complete.
Note:
Because power consumption is heavily dependent on actual design and environmental conditions, make sure to verify the actual power consumption during device operation.
Power estimation and analysis helps you ensure that your design satisfies
thermal and power supply requirements:
· Thermal–ensure that the cooling solution is sufficient to dissipate the heat
generated by the device. The computed junction temperature must fall within
normal device specifications.
· Power supply–ensure that the power supplies provide adequate current to
support device operation.
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Intel Quartus Prime Pro Edition User Guide: Getting Started 63
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Power and Thermal Calculator
The Power and Thermal Calculator (PTC) is a standalone tool that allows you to
estimate power utilization for your design for Intel Stratix 10 and Intel
Agilex 7 device families.
Note:
PTC does not support older devices, such as the Intel Arria 10 and Intel Cyclone 10 families, for which you must use the corresponding Early Power Estimator.
Estimating power consumption early in the design cycle allows you to plan power budgets and avoid unexpected results when designing the PCB.
Figure 46. Power and Thermal Calculator
Intel Quartus Prime Pro Edition User Guide: Getting Started 64
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You can enter data in PTC manually or through the output from an Intel Quartus
Prime software compile. · To manually enter data into PTC, enter the device
resources, operating frequency,
toggle rates, IP usage, and other parameters for your design. If you do not
have an existing design, estimate the number of device resources used in your
design, and then enter the data into PTC manually. · If you have an existing
design or a partially completed design, you can use the Intel Quartus Prime
software to generate a .qptc file, which you can then import into PTC.
For additional information about PTC, refer to the Intel FPGA Power and
Thermal Calculator User Guide.
Early Power Estimator (EPE) Spreadsheet
For devices other than Intel Stratix 10 and Intel Agilex 7, the Early Power
Estimator (EPE) spreadsheet allows you to estimate power utilization for your
design. Estimating power consumption early in the design cycle allows planning
of power budgets and avoids unexpected results when designing the PCB.
Figure 47. Early Power Estimator (EPE) Spreadsheet
You can manually enter data into the EPE spreadsheet, or use the Intel Quartus Prime software to generate device resource information for your design.
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To manually enter data into the EPE spreadsheet, enter the device resources,
operating frequency, toggle rates, and other parameters for your design. If
you do not have an existing design, estimate the number of device resources
used in your design, and then enter the data into the EPE spreadsheet
manually.
If you have an existing design or a partially completed design, you can use
the Intel Quartus Prime software to generate the Early Power Estimator File
(.txt, .csv) to assist you in completing the EPE spreadsheet.
The EPE spreadsheet includes the Import Data macro that parses the information
in the EPE File and transfers the information into the spreadsheet. If you do
not want to use the macro, you can manually transfer the data into the EPE
spreadsheet. For example, after importing the EPE File information into the
EPE spreadsheet, you can add device resource information. If the existing
Intel Quartus Prime project represents only a portion of your full design,
manually enter the additional device resources you use in the final design.
Intel Quartus Prime Power Analyzer
After you complete your design and run the Fitter, you can use the Intel
Quartus Prime Power Analyzer to perform a complete post-fit power analysis to
check the power consumption more accurately. The Power Analyzer provides an
accurate estimation of power, ensuring that thermal and supply limitations are
met. You can specify settings for power analysis by clicking Assignments
Settings Power Analyzer Settings.
Figure 48. Power Analyzer Settings
Intel Quartus Prime Pro Edition User Guide: Getting Started 66
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Related Information Intel Quartus Prime Pro Edition User Guide: Power Analysis
and Optimization
3.8. Plan for Interface I/O Pins
In many design environments, FPGA designers want to plan the top-level FPGA
I/O pins early to help board designers begin the PCB design and layout. The
I/O capabilities and board layout guidelines of the FPGA device influence pin
locations and other types of assignments. If the board design team specifies
an FPGA pin-out, the pin locations must be verified in the FPGA placement and
routing software to avoid board design changes.
You can create a preliminary pin-out for an Intel FPGA with the Intel Quartus
Prime Pin Planner before you develop the source code, based on standard I/O
interfaces (such as memory and bus interfaces) and any other I/O requirements
for your system.
Figure 49. Pin Planner
The Intel Quartus Prime I/O Assignment Analysis checks that the pin locations and assignments are supported in the target FPGA architecture. You can then use I/O Assignment Analysis to validate I/O-related assignments that you create or modify throughout the design process. When you compile your design in the Intel Quartus Prime software, I/O Assignment Analysis runs automatically in the Fitter to validate that the assignments meet all the device requirements and generates error messages.
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Intel Quartus Prime Pro Edition User Guide: Getting Started 67
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Early in the design process, before creating the source code, the system
architect has information about the standard I/O interfaces (such as memory
and bus interfaces), the IP cores in your design, and any other I/O-related
assignments defined by system requirements. You can use this information with
the Early Pin Planning feature in the Pin Planner to specify details about the
design I/O interfaces. You can then create a top-level design file that
includes all I/O information.
The Pin Planner interfaces with the IP core parameter editor, which allows you
to create or import custom IP cores that use I/O interfaces. You can configure
how to connect the functions and cores to each other by specifying matching
node names for selected ports. You can create other I/O-related assignments
for these interfaces or other design I/O pins in the Pin Planner, as described
in this section. The Pin Planner creates virtual pin assignments for internal
nodes, so internal nodes are not assigned to device pins during compilation.
You can use the I/O analysis results to change pin assignments or IP
parameters even before you create your design, and repeat the checking process
until the I/O interface meets your design requirements and passes the pin
checks in the Intel Quartus Prime software. When you complete initial pin
planning, you can create a revision based on the Intel Quartus Prime-generated
netlist. You can then use the generated netlist to develop the top-level
design file for your design, or disregard the generated netlist and use the
generated Intel Quartus Prime Settings File (.qsf) with your design.
During this early pin planning, after you have generated a top-level design
file, or when you have developed your design source code, you can assign pin
locations and assignments with the Pin Planner.
With the Pin Planner, you can identify I/O banks, voltage reference (VREF)
groups, and differential pin pairings to help you through the I/O planning
process. If you selected a migration device, the Pin Migration View highlights
the pins that have changed functions in the migration device when compared to
the currently selected device. Selecting the pins in the Device Migration view
cross-probes to the rest of the Pin Planner, so that you can use device
migration information when planning your pin assignments. You can also
configure board trace models of selected pins for use in “board-awa