ALLEGRO APEK85110KNH-01-T-MH Evaluation Board User Guide

: June 13, 2024
: ALLEGRO

Table of Contents

DESCRIPTION
FEATURES
EVALUATION BOARD CONTENTS
USING THE EVALUATION BOARD
GATE PULL-UP AND PULL-DOWN RESISTORS
ENABLE SEQUENCE
START SEQUENCE
MEASUREMENT POINTS
BIPOLAR GATE DRIVE
PROPAGATION DELAY
DOUBLE-PULSE TEST
DOUBLE PULSE TEST RESULTS DPT
SCHEMATIC
PCB LAYOUT
BILL OF MATERIALS
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APEK85110KNH-01-T-MH
AHV85110 Evaluation Board User Guide

DESCRIPTION

The Allegro Micro Systems Half-Bridge Driver-Switch APEK85110KNH-01-T-MH is a demonstration board containing two APEK85110KNH GaN FET drivers and two GaN FETs configured in a half-bridge configuration.

FEATURES

The APEK85110KNH-01-T-MH can be used to perform double-pulse tests, or to interface the half bridge to an existing LC power section, both as shown below.
The isolated APEK85110KNH driver does not require secondary side power or bootstrap components. Gate drive power is supplied to the secondary side from the primary side supply voltage VDRV. The amplitude of the gate drive can be varied by changing VDRV between 10.8 V and 13.2 V.

EVALUATION BOARD CONTENTS

APEK85110KNH-01-T-MH evaluation board.

DANGER

DO NOT TOUCH THE BOARD WHEN IT IS ENERGIZED AND ALLOW ALL COMPONENTS TO DISCHARGE COMPLETELY PRIOR HANDLING THE BOARD.
HIGH VOLTAGE CAN BE EXPOSED ON THE BOARD WHEN IT IS CONNECTED TO POWER SOURCE. EVEN BRIEF CONTACT DURING OPERATION MAY RESULT IN SEVERE INJURY OR DEATH.
Ensure that appropriate safety procedures are followed. This evaluation kit is designed for engineering evaluation in a controlled lab environment and should be handled by qualified personnel ONLY. Never leave the board operating unattended.

**WARNING

Some components can be hot during and after operation. There is NO built-in electrical or thermal protection on this evaluation kit. The operating voltage, current, and component temperature should be monitored closely during operation to prevent device damage.
CAUTION

This product contains parts that are susceptible to damage by electrostatic discharge (ESD). Always follow ESD prevention procedures when handling the product.

USING THE EVALUATION BOARD

Apply VDRV = 12 V.
Link pins EN_PU and EN (if not using external Enable control).
Apply input gate signals, with adequate dead time, to the IN_L and IN_H inputs.
Convenient test points are located on the test board as shown in Figure 5 below. A suitable differential oscilloscope should be used to monitor the high-side gate signal from VGH to VSW.

GATE PULL-UP AND PULL-DOWN RESISTORS

The APEK85110KNH gate driver has independent output pins for the gate pull-up and gate pull-down allowing control of the turn-on and turn-off rise and fall times. The default values for these resistors are:
OUTPU: R1 and R5 = 10
OUTPD: R3 and R7 = 1
These values can be modified to suit the application.

ENABLE SEQUENCE

The APEK85110KNH has an open-drain enable pin (EN) to facilitate a system- level wired-AND startup.
When the enable pin is externally pulled low, the driver is forced into a low- power mode. The driver output is pulled low in this mode. In the event of an internal fault condition, such as UVLO or normal startup delay, the EN pin is actively pulled low internally by the driver.
During normal operation, the pin is released by the driver, and must be pulled high with an external pull-high resistor. This functionality can be used by the PWM controller as an indication that it can start sending IN pulses to the driver. It is typically wired-AND with the controller enable pin as shown in Figure 3 below.
The APEK85110KNH-01-T-MH EVM board provides direct access to the EN pin on connector CONN1. Internally the board contains a 100 k pull-up resistor connected from VDRV to the EN_PU pin on connector CONN1–see schematic in Figure 12. If external control of the enable function is not required, pins EN and EN_PU must be linked together on CONN1 to make use of the internal 100 k pull-up resistor to enable the driver. If the EN pin is left floating, the drivers will not respond to INL or INH input signals.

Figure 3: APEK85110KNH Wired-AND Enable When the EN pin is pulled low, the driver output is disabled, and pulls down the OUTPD pin, regardless of the IN pin level (high or low). The driver goes to a low-power standby mode, and the isolated VSEC bias rail is allowed to discharge. The rate of decay of VSEC depends on the value of the CSEC capacitor. When the EN pin is subsequently pulled high, the driver will re-enable, and the isolated VSEC bias rail will start to recharge.

START SEQUENCE

The startup sequence of the APEK85110KNH is shown in Figure 4 below. Time tSTART is defined as the time after which VDRV reaches the UVLO rising level to the APEK85110KNH releasing the EN internal pull-down.
Any PWM signal applied to IN must remain low until VDRV > UV threshold to avoid parasitic charging of the VDRV rail through the IN pin internal ESD structures.
After VDRV exceeds the UV enable threshold, a startup time delay tSTART is required to charge VSEC and allow all internal circuits to initialize and stabilize. During tSTART, any IN signal inputs are ignored. EN internal pull- down will remain active during tSTART, and will disable (i.e., go open-drain) only when VDRV has reached its UVLO voltage level, all on-chip voltages are stabilized, and the internal tSTART timer has elapsed. Thus, the EN pin can be used via a shared EN line to flag when tSTART has elapsed, and the driver is ready to respond to PWM signals at the IN pin, as outlined above.

MEASUREMENT POINTS

The APEK85110KNH-01-T-MH EVM contains convenient test points for monitoring the high- and low-side gate drives as well as the switch node as shown in Figure 5 below.
When measuring VGS_H, use a differential probe with suitable ratings for the applied bus voltage. The APEK85110KNH-01-T-MH EVM uses a bipolar gate drive arrangement as shown in Figure 6 below. When measuring VGS, both gate drives are measured relative to the source of their associated GaN FET. Therefore, the off-state voltage will be negative.
It is important to use a low-inductance scope probe ground lead as shown to avoid pickup of spurious switching noise.

BIPOLAR GATE DRIVE

Due to the high rate of change of voltages and currents in power switching circuits, unwanted inductor currents and capacitor voltage drops can be created.
One such example is the false turn-on of a FET due to a dv/dt event. In a half-bridge circuit, after the low-side FET has been turned off and a suitable dead-time elapsed, the high-side FET is turned on. This produces a rapidly changing switch node voltage at the drain of the low-side FET. This voltage will produce a capacitor current:

flowing in the gate-drain capacitance, CGD, and driver output. It will cause the voltage on the gate of the low-side FET to rise. If this voltage spike peaks beyond the threshold voltage VTH, the FET will conduct. Considering that the high-side FET is also conducting, this can result in a potentially destructive shoot-through event.
The APEK85110KNH-01-T-MH EVM uses a bipolar gate drive arrangement which is useful to mitigate against the effects of gate-drain capacitor currents. The secondary supply voltage VSEC is a function of the primary supply voltage VDRV. The zener diode, CR1, will regulate the positive turn-on voltage of the GaN FET. During the turn-off period, the gate voltage will be negative with a value of:

VGS_OFF = VSEC VZENER. VSEC is typically 9 V.

This negative VGS_OFF voltage allows more margin before the threshold voltage can be reached.

PROPAGATION DELAY

VDRV = 12 V
Input = 100 kHz
RPU = 10 , RPD = 1
Power train unloaded. That is, VHV+ = 0 V.

DOUBLE-PULSE TEST

The double-pulse test is used to evaluate the switching characteristics of a power switch under hard switching but in a safe manner. For a low-side switch, the setup is as shown below:

The low-side switch is driven with two pulses as shown below. The high-side switch can be held off or driven with the inverse of the low-side gate switch (with adequate dead time).

An inductor is placed in parallel with the high-side switch. The goal of this inductor is to establish the test level current in the low-side switch at the end of the first on pulse (1). The magnitude of the test level current at the end of period 1 is given by:

During period 2, the inductor current will naturally decay. The duration of period 2 should not be so long that inductor current deviates significantly from the desired test level. During period 3, the inductor current will again rise. Period 3 should not be so long that the inductor current rises to an excessive level. The falling edge of pulse 1 is used to examine the hard turn off characteristics of the switch. The rising edge of pulse 3 is used to examine the hard turn on characteristics of the switch. By only applying these two pulses, the switches are only on for a very short time and should not overheat.

DOUBLE PULSE TEST RESULTS DPT

Result 100 V, 15 A

DPT Result 400 V, 62 A

SCHEMATIC

PCB LAYOUT

BILL OF MATERIALS

Table 1: APEK85110KNH-01-T-MH Evaluation Board Bill of Materials

Ref Name	Description	Value	Qty	Manufacturer	Manufacturer PN
Cl, C2	CAP CERALINK, 1 pF, 500 V, PLZT	1 µF	2	TDK	B58031U5105M062
C14, C15, C16, C17	CAP, CER,100nF,16V, X7R, SO402	100 nF	4	KEMET

Revision History

Number	Date	Description
–	14-Jun-23	Initial release

Copyright 2023, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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