DIODES AP63200QWU-EVM Synchronous DC-DC Buck Converter with Enhanced EMI Reduction User Guide

DIODES AP63200QWU-EVM Synchronous DC-DC Buck Converter with Enhanced EMI

Reduction

Product Information

Product Name: AP63200QWU-EVM

Description: The AP63200QWU-EVM is a 32V, 2A synchronous buck converter with enhanced EMI reduction. It features a wide input voltage range of 3.8V to 32V and integrates a high-side power MOSFET and a low-side power MOSFET for efficient step-down DC-DC conversion. The device utilizes peak current mode control and an integrated compensation network to minimize the external component count.

Features:

• Switching Frequency: 500kHz
• Supports Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM)
• Proprietary Gate Driver Design for Best EMI Reduction
• Frequency Spread Spectrum (FSS) to Reduce EMI
• Low-Dropout (LDO) Mode
• Precision Enable Threshold to Adjust UVLO
• Protection Circuitry:
  • Undervoltage Lockout (UVLO)
  • Cycle-by-Cycle Peak Current Limit
  • Thermal Shutdown

Product Usage Instructions

1. Connect a power supply to the input terminals VIN and GND.
2. Set the input voltage (VIN) to the desired value within the recommended operating range of 3.8V to 32V.
3. For Enable/Disable functionality, place a jumper in the H position to enable the IC and in the L position to disable it.
4. Connect the positive terminal of an electronic load to the VOUT terminal and the negative terminal to GND.
5. Ensure the evaluation board is powered up and observe the output voltage (VOUT).
6. Adjust the load to the desired current value, up to a maximum of 2A, using the electronic load.
7. Monitor the SW signal on an oscilloscope for stable operation and measure the switching frequency if needed.

Measurement/Performance Guidelines:

1. When measuring the output voltage ripple, maintain the shortest possible ground lengths on the oscilloscope probe. Long ground leads can erroneously inject high-frequency noise into the measured ripple.

DESCRIPTION

• The AP63200Q is a 2A, synchronous buck converter with a wide input voltage range of 3.8V to 32V and fully integrates a 125mΩ high-side power MOSFET and a 68mΩ low-side power MOSFET to provide high-efficiency step-down DC-DC conversion.
• The AP63200Q device is easily used by minimizing the external component count due to its adoption of peak current mode control along with its integrated compensation network.
• The AP63200Q has designs optimized for Electromagnetic Interference (EMI) reduction. The converter features Frequency Spread Spectrum (FSS) with a switching frequency jitter of ±6%, which reduces EMI by not allowing emitted energy to stay in any one frequency for a significant period of time. It also has a proprietary gate driver scheme to resist switching node ringing without sacrificing MOSFET turn-on and turn-off times, which further reduces high-frequency radiated EMI noise caused by MOSFET switching.
• The device is available in a low-profile, TSOT26 package.

FEATURES

• VIN 3.8V to 32V
• 2A Continuous Output Current
• 0.8V ± 1% Reference Voltage
• 22µA Low Quiescent Current (Pulse Frequency Modulation)
• 500kHz Switching Frequency
• Supports Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM)
• Proprietary Gate Driver Design for Best EMI Reduction
• Frequency Spread Spectrum (FSS) to Reduce EMI
• Low-Dropout (LDO) Mode
• Precision Enable Threshold to Adjust UVLO
• Protection Circuitry
  • Undervoltage Lockout (UVLO)
  • Cycle-by-Cycle Peak Current Limit
  • Thermal Shutdown

FUNCTIONAL BLOCK

Figure 1. Functional Block Diagram

ABSOLUTE MAXIMUM RATINGS

-0.3 to +40.0 (400ms)
VSW| Switch Node Voltage| -1.0 to VIN + 0.3 (DC)| V
-2.5 to VIN + 2.0 (20ns)
VBST| Bootstrap Voltage| VSW – 0.3 to VSW + 6.0| V
VFB| Feedback Voltage| -0.3 to +6.0| V
VEN| Enable/UVLO Voltage| -0.3 to +35.0| V
TST| Storage Temperature| -65 to +150| °C
TJ| Junction Temperature| +160| °C
TL| Lead Temperature| +260| °C
ESD Susceptibility

HBM| Human Body Mode| 2000| V
CDM| Charge Device Model| 1500| V

RECOMMENDED OPERATING CONDITIONS

EVALUATION BOARD

QUICK START GUIDE

The AP63200QWU-EVM has a simple layout and allows access to the appropriate signals through test points. To evaluate the performance of the AP63200QWU, follow the procedure below:

1. For evaluation board configured at VOUT=5V, connect a power supply to the input terminals VIN and GND. Set VIN to 12V.
2. Connect the positive terminal of the electronic load to VOUT and negative terminal to GND.
3. For Enable, place a jumper to “H” position to enable IC. Jump to “L” position to disable IC.
4. The evaluation board should now power up with a 5V output voltage.
5. Check for the proper output voltage of 5V (±1%) at the output terminals VOUT and GND. Measurement can also be done with a multimeter with the positive and negative leads between VOUT and GND.
6. Set the load to 2A through the electronic load. Check for the stable operation of the SW signal on the oscilloscope. Measure the switching frequency.

MEASUREMENT/PERFORMANCE GUIDELINES

1. When measuring the output voltage ripple, maintain the shortest possible ground lengths on the oscilloscope probe. Long ground leads can erroneously inject high frequency noise into the measured ripple.
2. For efficiency measurements, connect an ammeter in series with the input supply to measure the input current. Connect an electronic load to the output for output current.

SETTING OUTPUT VOLTAGE

1. Setting the output voltage
   The AP63200QWU features external programmable output voltage by using a resistor divider network R3 and R1 as shown in the typical application circuit. The output voltage is calculated as below,

First, select a value for R1 according to the value recommended in the table

1. Then, R3 is determined. The output voltage is given by Table 1 for reference. For accurate output voltage, 1% tolerance is required.
   Table 1. Recommended Component Selections

2. Output feed-forward capacitor selection
   The AP63200QWU has the internal integrated loop compensation as shown in the function block diagram. The compensation network includes an 18k resistor and a 7.6nF capacitor. Usually, the type II compensation network has a phase margin between 60 and 90 degree. However, if the output capacitor has ultra- low ESR, the converter results in low phase margin. To increase the converter phase margin, a feed-forward cap C4 is used to boost the phase margin at the converter cross-over frequency, The feed-forward capacitor is given by
   Table 1 for reference. The feed-forward capacitor is calculated as below,

EVALUATION BOARD SCHEMATIC

BILL OF MATERIALS for AP63200QWU-EVM (VOUT=12V)

TYPICAL PERFORMANCE CHARACTERISTICS

IMPORTANT NOTICE

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