STMicroelectronics STM32U585AI Discovery Kit for IoT Node User Manual
- June 12, 2024
- STMicroelectronics
Table of Contents
STMicroelectronics STM32U585AI Discovery Kit for IoT Node
Product Information
The STM32U585xx is a microcontroller that includes ST state-of-the-art patented technology. It features ultra-low-power consumption with FlexPower Control. The core of the microcontroller is equipped with an ART Accelerator for enhanced performance. It also has power management capabilities and supports various benchmarks.
The microcontroller comes in different package options, including LQFP48 (7 x
7 mm), UFQFPN48, LQFP64 (10 x 10 mm), LQFP100 (14 x 14 mm), LQFP144 (20 x 20
mm), WLCSP90 (4.2 x 3.95 mm),
UFBGA132 (7 x 7 mm), and UFBGA169 (7 x 7 mm). It has built-in memories for
storage and security purposes.
Product Usage Instructions
- Connect the STM32U585xx microcontroller to the power supply according to the specified voltage requirements.
- Ensure that the necessary peripherals and sensors are properly connected to the microcontroller.
- Refer to the datasheet or user manual for pin configurations and pin functionalities.
- Initialize the microcontroller by programming the necessary software code.
- Utilize the ART Accelerator feature to enhance the performance of the core.
- Manage power consumption using the FlexPowerControl feature.
- Take advantage of the various timers, watchdogs, and communication peripherals available on the microcontroller.
- Utilize the rich analog peripherals and capacitive sensing channels as required.
- Implement security measures using the embedded flash memory and memory protection unit.
- Consider the different boot modes available and select the appropriate mode for your application.
- Refer to the Global TrustZone controller (GTZC) for managing the TrustZone security architecture.
STM32U585xx
Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU, 240 DMIPS, up to 2
MB Flash memory, 786 KB SRAM, SMPS
Datasheet – production data
Features
Includes ST state-of-the-art patented technology
Ultra-low-power with FlexPowerControl
· 1.71 V to 3.6 V power supply · 40 °C to +85/125 °C temperature range · Low-
power background autonomous mode
(LPBAM): autonomous peripherals with DMA, functional down to Stop 2 mode ·
VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup
SRAM · 160 nA Shutdown mode (24 wakeup pins) · 210 nA Standby mode (24 wakeup
pins) · 440 nA Standby mode with RTC · 1.9 A Stop 3 mode with 16-Kbyte SRAM ·
4.3 µA Stop 3 mode with full SRAM · 4.0 µA Stop 2 mode with 16-Kbyte SRAM ·
8.95 µA Stop 2 mode with full SRAM · 19.5 A/MHz Run mode @ 3.3 V
Core
· Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU
ART Accelerator
· 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and
external memories: up to 160 MHz, 240 DMIPS
· 4-Kbyte data cache for external memories
Power management
· Embedded regulator (LDO) and SMPS step-down converter supporting switch on-
the-fly and voltage scaling
Benchmarks
· 1.5 DMIPS/MHz (Drystone 2.1)
LQFP48 (7 x 7 mm) UFQFPN48 LQFP64 (10 x 10 mm) (7 x 7 mm) LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm)
WLCSP90 (4.2 x 3.95 mm)
UFBGA132 (7 x 7 mm) UFBGA169 (7 x 7 mm)
· 651 CoreMark® (4.07 CoreMark®/MHz) · 535 ULPMarkTM-CP
· 149 ULPMarkTM-PP · 58.2 ULPMarkTM-CM · 133000 SecureMarkTM-TLS
Memories
· 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512
Kbytes with 100 kcycles
· 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM
with ECC ON
· External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM
memories
· 2 Octo-SPI memory interfaces
Security and cryptography
· PSA level 3 and SESIP level 3 certified · Arm® TrustZone® and securable
I/Os,
memories and peripherals
· Flexible life cycle scheme with RDP and password protected debug
· Root of trust thanks to unique boot entry and secure hide protection area
(HDP)
· Secure firmware installation (SFI) thanks to embedded root secure services
(RSS)
· Secure data storage with hardware unique key (HUK)
· Secure firmware upgrade support with TF-M
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· 2 AES coprocessors including one with DPA resistance
· Public key accelerator, DPA resistant
· On-the-fly decryption of Octo-SPI external memories
· HASH hardware accelerator
· True random number generator, NIST SP800-90B compliant
· 96-bit unique ID
· 512-byte OTP (one-time programmable)
· 3 SPIs (5x SPIs with the dual OCTOSPI) · 1 CAN FD controller · 2 SDMMC
interfaces · 1 multi-function digital filter (6 filters)+ 1 audio
digital filter with sound-activity detection · Parallel synchronous slave
interface
16- and 4-channel DMA controllers, functional in Stop mode
Graphic features
· Active tampers
Clock management
· 4 to 50 MHz crystal oscillator · 32 kHz crystal oscillator for RTC (LSE) ·
Internal 16 MHz factory-trimmed RC (±1%) · Internal low-power 32 kHz RC (±5%)
· 2 internal multispeed 100 kHz to 48 MHz
oscillators, including one auto-trimmed by LSE (better than ±0.25% accuracy) ·
Internal 48 MHz with clock recovery · 3 PLLs for system clock, USB, audio, ADC
General-purpose input/outputs
· Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
· 1 digital camera interface
Mathematical co-processor
· CORDIC for trigonometric functions acceleration
· Filter mathematical accelerator (FMAC)
Up to 24 capacitive sensing channels
· Support touch key, linear and rotary touch sensors
Rich analog peripherals (independent supply)
· Up to 136 fast I/Os with interrupt capability most 5V-tolerant and up to 14
I/Os with independent supply down to 1.08 V
Up to 17 timers and 2 watchdogs
· 2 16-bit advanced motor-control, 4 32-bit, 5 16-bit, 4 low-power 16-bit
(available in Stop mode), 2 SysTick timers and 2 watchdogs
· 14-bit ADC 2.5-Msps with hardware oversampling
· 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode
· 2 12-bit DAC, low-power sample and hold
· 2 operational amplifiers with built-in PGA · 2 ultra-low-power comparators
· RTC with hardware calendar and calibration
CRC calculation unit
Up to 22 communication peripherals
· 1 USB Type-C®/USB power delivery controller · 1 USB OTG 2.0 full-speed
controller · 2 SAIs (serial-audio interface) · 4 I2C FM+(1 Mbit/s),
SMBus/PMBusTM
Debug
· Development support: serial-wire debug (SWD), JTAG, Embedded Trace
MacrocellTM (ETM)
ECOPACK2 compliant packages
· 6 USARTs (ISO 7816, LIN, IrDA, modem)
Table 1. Device summary
Reference
Part numbers
STM32U585xx
STM32U585AI, STM32U585CI,STM32U585OI, STM32U585QI, STM32U585RI, STM32U585VI, STM32U585ZI
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Contents
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Contents
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3.14
3.15 3.16 3.17 3.18 3.19 3.20
3.21 3.22 3.23 3.24
3.25
3.26 3.27 3.28
3.29 3.30 3.31 3.32 3.33
3.34
3.13.1 GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 50
Low-power general-purpose inputs/outputs (LPGPIO) . . . . . . . . . . . . . .
50
3.14.1 LPGPIO TrustZone security . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 51
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 51 System configuration controller (SYSCFG) . . . . . .
. . . . . . . . . . . . . . . . . 51 General purpose direct memory access
controller (GPDMA) . . . . . . . . . 51 Low-power direct memory access
controller (LPDMA) . . . . . . . . . . . . . . 53 Chrom-ART Accelerator
controller (DMA2D) . . . . . . . . . . . . . . . . . . . . . . 55 Interrupts
and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 56
3.20.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . .
. . . . . . . . 56 3.20.2 Extended interrupt/event controller (EXTI) . . . . .
. . . . . . . . . . . . . . . . . 56
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . .
. . . 57 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 57 Filter math accelerator (FMAC) . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 57 Flexible static memory controller
(FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.24.1 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 58 3.24.2 FSMC TrustZone security . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 59
3.25.1 OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 60
OCTOSPI I/O manager (OCTOSPIM) . . . . . . . . . . . . . . . . . . . . . . . .
. . . 60 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 60 Analog-to-digital converter (ADC1 and ADC4)
. . . . . . . . . . . . . . . . . . . . . 60
3.28.1 Analog-to-digital converter 1 (ADC1) . . . . . . . . . . . . . . . . .
. . . . . . . . . . 61 3.28.2 Analog-to-digital converter 4 (ADC4) . . . . . .
. . . . . . . . . . . . . . . . . . . . . 63 3.28.3 Temperature sensor . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.28.4 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . .
. . . . . . . . . 65 3.28.5 VBAT battery voltage monitoring . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 65
Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 65 Voltage reference buffer (VREFBUF) . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 66 Comparators (COMP) . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operational
amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 67 Multi-function digital filter (MDF) and audio digital filter (ADF) . . .
. . . . . . 67
3.33.1 Multi-function digital filter (MDF) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 67 3.33.2 Audio digital filter (ADF) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 71
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3.35 3.36 3.37 3.38 3.39 3.40 3.41 3.42
3.43
3.44 3.45
3.46 3.47 3.48 3.49 3.50 3.51 3.52
Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . .
. . . . . 71 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 71 True random number generator (RNG) . . . . .
. . . . . . . . . . . . . . . . . . . . . 72 Secure advanced encryption
standard hardware accelerator (SAES) and encryption standard hardware
accelerator (AES) . . . . . . . . . . . . . . . 73 HASH hardware accelerator
(HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 On-the-fly
decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . .
76 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 77 Timers and watchdogs . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 77
3.42.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . .
. . . . . . . . 78 3.42.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5,
TIM15,
TIM16,TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 78 3.42.3 Basic timers (TIM6 and TIM7) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 79 3.42.4 Low-power timers
(LPTIM1, LPTIM2, LPTIM3, LPTIM4) . . . . . . . . . . . . 79 3.42.5 Infrared
interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 80 3.42.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 80 3.42.7 Window watchdog (WWDG) . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.42.8 SysTick timer .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 80
Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . .
. 80
3.43.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 80 3.43.2 Tamper and backup registers (TAMP) . . . .
. . . . . . . . . . . . . . . . . . . . . . 81
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 83 Universal synchronous/asynchronous receiver transmitter
(USART/UART) and low-power universal asynchronous receiver transmitter
(LPUART) . 84
3.45.1 Universal synchronous/asynchronous receiver transmitter (USART/UART) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 84
3.45.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 86
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 87 Serial audio interfaces (SAI) . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 88 Secure digital input/output and
MultiMediaCards interface (SDMMC) . . . 89 Controller area network (FDCAN) . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 USB on-the-go full-
speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 USB
Type-C /USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . . 93
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 93
3.52.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . .
. . . . . . . . 93 3.52.2 Embedded Trace Macrocell . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 93
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4
Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . . 94
4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.2 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . 155
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 155
5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.3.6
Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.3.7 External clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.3.8 5.3.9
Internal clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 234
5.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.3.18 14-bit analog-to-digital converter (ADC1) characteristics . . . . . . . . . . 234
5.3.19 12-bit analog-to-digital converter (ADC4) characteristics . . . . . . . . . . 241
5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
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5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 5.3.29 5.3.30 5.3.31 5.3.32 5.3.33 5.3.34 5.3.35 5.3.36 5.3.37 5.3.38 5.3.39 5.3.40 5.3.41 5.3.42
VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 247 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 251 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 255 Temperature and Backup domain supply thresholds monitoring . . . . . 258 ADF/MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 DCMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 PSSI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 SD/SDIO/e·MMC card host interfaces (SDMMC) characteristics . . . . 285 Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 296
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
6.1 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
6.2 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
6.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
6.4 WLSCP90 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
6.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
6.6 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
6.7 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
6.8 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
6.9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
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Contents
STM32U585xx
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table
9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table
17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24.
Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table
32. Table 33. Table 34. Table 35. Table 36. Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32U585xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Access status versus protection level and execution modes when TZEN = 0 . . . . . . . . . . 25 Access status versus protection level and execution modes when TZEN = 1 . . . . . . . . . . 26 Example of memory map security attribution versus SAU configuration regions . . . . . . . . 29 Boot modes when TrustZone is disabled (TZEN = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Boot modes when TrustZone is enabled (TZEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32U585xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 GPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 GPDMA1 autonomous mode and wakeup in low-power modes. . . . . . . . . . . . . . . . . . . . . 53 LPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LPDMA1 autonomous mode and wakeup in low-power modes . . . . . . . . . . . . . . . . . . . . . 55 ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 MDF features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 AES/SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 STM32U585xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Operating conditions at power-up /power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 155 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Current consumption in Run mode on LDO, code with data processing running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 160 Current consumption in Run mode on SMPS, code with data processing running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 161 Current consumption in Run mode on SMPS, code with data processing running from Flash memory, ICACHE ON (1-way), prefetch ON, VDD = 3.0 V . . . . . . . . 162 Typical current consumption in Run mode on LDO, with different codes running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON . . . 163 Typical current consumption in Run mode on LDO, with different codes running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 163 Typical current consumption in Run mode on SMPS, with different codes running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON . . . 165
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List of tables
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Table 43.
Table 44. Table 45. Table 46.
Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table
54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61.
Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table
69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76.
Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table
84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91.
Table 92.
Typical current consumption in Run mode on SMPS, with different codes running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 165 Current consumption in Sleep mode on LDO, Flash memory in power down . . . . . . . . . 167 Current consumption in Sleep mode on SMPS, Flash memory in power down . . . . . . . . 168 Current consumption in Sleep mode on SMPS, Flash memory in power down, VDD = 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS . . . . . . . 170 Static power consumption of Flash banks, when supplied by LDO/SMPS . . . . . . . . . . . . 171 Current consumption in Stop 0 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Current consumption in Stop 0 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Current consumption in Stop 1 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Current consumption during wakeup from Stop 1 mode on LDO . . . . . . . . . . . . . . . . . . . 175 Current consumption in Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Current consumption during wakeup from Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . 177 Current consumption in Stop 2 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Current consumption during wakeup from Stop 2 mode on LDO . . . . . . . . . . . . . . . . . . . 179 Current consumption in Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Current consumption during wakeup from Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . 181 Current consumption in Stop 3 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Current consumption during wakeup from Stop 3 mode on LDO . . . . . . . . . . . . . . . . . . . 183 Current consumption in Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Current consumption during wakeup from Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . 185 SRAM static power consumption in Stop 2 when supplied by LDO . . . . . . . . . . . . . . . . . 186 SRAM static power consumption in Stop 2 when supplied by SMPS. . . . . . . . . . . . . . . . 187 SRAM static power consumption in Stop 3 when supplied by LDO . . . . . . . . . . . . . . . . . 188 SRAM static power consumption in Stop 3 when supplied by SMPS. . . . . . . . . . . . . . . . 189 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Current consumption during wakeup from Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 193 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Current consumption during wakeup from Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . 194 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Typical dynamic current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Low-power mode wakeup timings on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Low-power mode wakeup timings on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SHSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
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List of tables
Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144.
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Output AC characteristics, HSLV OFF (all I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . 228 Output AC characteristics, HSLV ON (all I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . 230 Output AC characteristics for FT_c I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Output AC characteristics for FT_t I/Os in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Maximum RAIN for 14-bit ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 14-bit ADC1 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 12-bit ADC4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Maximum RAIN for 12-bit ADC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12-bit ADC4 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 ADF characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 WWDG min/max timeout value at 160 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 267 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 267 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 268 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 269 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 270 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 272 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 276 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 279 OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 OCTOSPI characteristics in DTR mode (with DQS)/HyperBus . . . . . . . . . . . . . . . . . . . . 282 SD/e·MMC characteristics (VDD = 2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 e·MMC characteristics (VDD = 1.71 V to 1.9 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
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Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166.
Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 LQFP48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 LQFP64 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 WLCSP90 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 WLCSP90 – Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 LQFP100 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 UFBGA132 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 UFBGA132 – Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 315 LQFP144 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 UFBGA169 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 UFBGA169 – Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 322 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure
8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15.
Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22.
Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29.
Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36.
Figure 37. Figure 38.
Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45.
Figure 46. Figure 47.
STM32U585xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32U585xQ power supply overview (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32U585xx power supply overview (without SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power-up /down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 VREFBUF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 LQFP48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 UFQFPN48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP64_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 WLCSP90-SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP100_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 UFBGA132 _SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LQFP144 _SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 UFBGA169_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 STM32U585xx power supply scheme (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 STM32U585xQ power supply scheme (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 AC timing diagram for high-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . 208 AC timing diagram for low-speed external square clock source . . . . . . . . . . . . . . . . . . . . 208 AC timing diagram for low- speed external sinusoidal clock source . . . . . . . . . . . . . . . . . 209 Typical application with a 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 I/O input characteristics (all I/Os except BOOT0 and FT_c). . . . . . . . . . . . . . . . . . . . . . . 226 Output AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 12-bit buffered/non- buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 VREFBUF_OUT versus temperature (VRS = 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 VREFBUF_OUT versus temperature (VRS = 001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 VREFBUF_OUT versus temperature (VRS = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 VREFBUF_OUT versus temperature (VRS = 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 ADF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 MDF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
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Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54.
Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61.
Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68.
Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75.
Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82.
Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89.
Figure 90. Figure 91. Figure 92.
Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98.
PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 266 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 268 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 269 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 271 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 275 Synchronous non- multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 278 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 279 OCTOSPI timing diagram – SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 OCTOSPI timing diagram – DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 USART timing diagram in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 USART timing diagram in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 SPI timing diagram – slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 SPI timing diagram – slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 SPI timing diagram – master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 SAI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 SAI slave timing digram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 UFQFPN48 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 LQFP48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 LQFP48 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 LQFP64 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 LQFP64 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 WLCSP90 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 WLCSP90 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 WLCSP90 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 LQFP100 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 LQFP100 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 UFBGA132 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 UFBGA132 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 UFBGA132 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 LQFP144 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 LQFP144 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
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Figure 99. UFBGA169 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Figure 100. UFBGA169 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Figure 101. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
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Introduction
1
Introduction
STM32U585xx
This document provides the ordering information and mechanical device
characteristics of the STM32U585xx microcontrollers.
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33
Technical Reference Manual, available from the www.arm.com website.
For information on the device errata with respect to the datasheet and reference manual, refer to the STM32U575xx and STM32U585xx errata sheet (ES0499)
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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Description
Description
The STM32U585xx devices belong to an ultra-low-power microcontrollers family
(STM32U5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC
core. They operate at a frequency of up to 160 MHz.
The Cortex®-M33 core features a single-precision FPU (floating-point unit),
that supports all the Arm® single-precision data-processing instructions and
all the data types.
The Cortex®-M33 core also implements a full set of DSP (digital signal
processing) instructions and a MPU (memory protection unit) that enhances the
application security.
The devices embed high-speed memories (2 Mbytes of Flash memory and 786 Kbytes
of SRAM), a FSMC (flexible external memory controller) for static memories
(for devices with packages of 90 pins and more), two Octo-SPI Flash memory
interfaces (at least one Quad-SPI available on all packages) and an extensive
range of enhanced I/Os and peripherals connected to three APB buses, three AHB
buses and a 32-bit multi-AHB bus matrix.
The devices offer security foundation compliant with the TBSA (trusted-based
security architecture) requirements from Arm®. It embeds the necessary
security features to implement a secure boot, secure data storage and secure
firmware update. Besides these capabilities, the devices incorporate a secure
firmware installation feature, that allows the customer to secure the
provisioning of the code during its production. A flexible lifecycle is
managed thanks to multiple levels of readout protection and debug unlock with
password. Firmware hardware isolation is supported thanks to securable
peripherals, memories and I/Os, and privilege configuration of peripherals and
memories.
The devices feature several protection mechanisms for embedded Flash memory
and SRAM: readout protection, write protection, secure and hide protection
areas.
The devices embed several peripherals reinforcing security: a fast AES
coprocessor, a secure AES coprocessor with DPA resistance and hardware unique
key that can be shared by hardware with fast AES, a PKA (public key
accelerator) with DPA resistance, an on-the-fly decryption engine for Octo-SPI
external memories, a HASH hardware accelerator, and a true random number
generator.
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks, thanks to several internal monitoring
generating secret data erase in case of attack. This helps to fit the PCI
requirements for point of sales applications.
The devices offer one fast 14-bit ADC (2.5 Msps), one 12-bit ADC (2.5 Msps),
two comparators, two operational amplifiers, two DAC channels, an internal
voltage reference buffer, a low-power RTC, four 32-bit general-purpose timers,
two 16-bit PWM timers dedicated to motor control, three 16-bit general-purpose
timers, two 16-bit basic timers and four 16-bit low-power timers.
The devices support a MDF (multi-function digital filter) with six filters
dedicated to the connection of external sigma-delta modulators. Another low-
power digital filter dedicated to audio signals is embedded (ADF), with one
filter supporting sound-activity detection. The devices embed also a Chrom-ART
Accelerator dedicated to graphic applications, and mathematical accelerators
(a trigonometric functions accelerator plus a filter mathematical
accelerator). In addition, up to 24 capacitive sensing channels are available.
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Description
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The devices also feature standard and advanced communication interfaces such
as: four I2Cs, three SPIs, three USARTs, two UARTs, one low-power UART, two
SAIs, one digital camera interface (DCMI), two SDMMCs, one FDCAN, one USB OTG
full-speed, one USB Type-C /USB Power Delivery controller, and one generic
synchronous 8-/16-bit PSSI (parallel data input/output slave interface).
The devices operate in the 40 to +85 °C (+105 °C junction) and 40 to +125 °C
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allow the design of low-power
applications. Many peripherals (including communication, analog, timers and
audio peripherals) can be functional and autonomous down to Stop mode with
direct memory access, thanks to LPBAM support (low-power background autonomous
mode).
Some independent power supplies are supported like an analog independent
supply input for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply
input for USB and up to 14 I/Os, that can be supplied independently down to
1.08 V. A VBAT input is available for connecting a backup battery in order to
preserve the RTC functionality and to backup 32 32-bit registers and 2-Kbyte
SRAM.
The devices offer eight packages from 48 to 169 pins.
Table 2. STM32U585xx features and peripheral counts
STM32U585CI STM32U585RI STM32U585OI STM32U585VI STM32U585QI STM32U585ZI STM32U585AI
Peripherals
Flash memory (Mbytes)
SRAM
System (Kbytes) Backup (bytes)
External memory controller for static memories (FSMC)
OCTOSPI
Advanced control
General purpose
Basic
Timers
Low power SysTick timer
Watchdog timers (independent, window)
2 784 (192+64+512+16) 2048 backup SRAM + 128 backup registers
No
Yes(1)
Yes(2)
2(3)
2
2 (16 bits)
4 (32 bits) and 3 (16 bits)
2 (16 bits)
4 (16 bits)
2
2
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DS13086 Rev 3
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Description
Table 2. STM32U585xx features and peripheral counts (continued)
STM32U585CI STM32U585RI STM32U585OI STM32U585VI STM32U585QI STM32U585ZI STM32U585AI
Peripherals
SPI
I2C
USART
UART
1
LPUART
SAI
1
Communication FDCAN
interfaces
OTG FS
UCPD
SDMMC
0
Camera interface
No
Yes/No(5)
PSSI
No
Yes/No(5)
MDF (multi-function digital filter)
Yes (2 filters)
ADF (audio digital filter)
CORDIC co-processor
FMAC (filter mathematical accelerator)
RTC (real-time clock)
Tamper pins (without SMPS / with SMPS)
Active tampers (without SMPS / with SMPS)(6)
3 / 3
4 / 3
– / 8
2 / 2
3 / 2
– / 7
True random number generator
SAES, AES
PKA (public key accelerator)
HASH (SHA-256)
On-the-fly decryption for OCTOSPI
GPIOs (without SMPS / with SMPS)
Wakeup pins (without SMPS / with SMPS)
Number of I/Os down to 1.08 V (without SMPS / with SMPS)
36 / 33 50 / 47
69
17 / 15 18 / 17
23
0 / 0
0 / 0
6
3 4 3
2 1
2 1 Yes Yes
2(4) Yes Yes
Yes (6 filters) Yes Yes
Yes
Yes
8 / 7
8 / 8
8 / 7
8 / 8
7 / 6
7 / 7
7 / 6
7 / 7
Yes Yes Yes Yes Yes
82 / 79 109 / 106 113 / 111 137 / 134
22 / 19 24 / 24 24 / 23 24 / 24
0 / 0 13 / 10 14 / 13 14 / 11
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Description
STM32U585xx
Table 2. STM32U585xx features and peripheral counts (continued)
STM32U585CI STM32U585RI STM32U585OI STM32U585VI STM32U585QI STM32U585ZI STM32U585AI
Peripherals
Capacitive sensing
Number of channels (without SMPS 8 / 7
14 / 13
13
21 / 20 24 / 24 24 / 23 24 / 24
/ with SMPS)
12-bit ADC
1
ADC
14-bit ADC
1
Nbr of channels
(without SMPS / 11 / 10 17 / 15
16
20 / 18 24 / 24 24 / 22 24 / 24
with SMPS)
DAC
Number of 12-bit D-to-A converters
2
Internal voltage reference buffer
No
Yes
Analog comparator
2
Operational amplifiers
2
Maximum CPU frequency
160 MHz
Operating voltage
1.71 to 3.6 V
Operating temperature
Ambient operating temperature: 40 to +85 °C / 40 to +125 °C Junction temperature: 40 to +105 °C / 40 to +130 °C
Package
LQFP48, UFQFPN LQFP64
48
WLCSP 90
LQFP 100
UFBGA 132
LQFP144
UFBGA 169
1. For the WLCSP90 package, FSMC can only support 8-bit LCD interface. 2. For
the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a
multiplexed NOR/PSRAM memory
using the NE1 chip select. 3. Two OCTOSPIs are available only in Muxed mode.
4. When both are used simultaneously, one supports only SDIO interface. 5.
Available on packages without SMPS, not available on packages with SMPS. 6.
Active tampers in output sharing mode (one output shared by all inputs).
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DS13086 Rev 3
STM32U585xx
Description
NJTRST, JTDI, JTCK/SWCLK, JTMS/SWDIO, JTDO
TRACECLK, TRACED[3:0]
JTAG/ SW ETM
MPU NVIC
Arm Cortex-M33
160 MHz
C-BUS
TrustZone FPU
S-BUS
D[7:0], D[3:1]dir CMD, CMDdir,CK, CKin
D0dir, D2dir
SDMMC1 SDMMC2
DMA2D
8 groups of 4 channels max as AF
SDIN[5:0], CKIN[5:0], CCK0, CCK1 as AF PA[15:0] PB[15:0] PC[15:13] PC[12:0]
PD[15:0] PE[15:0] PF[15:0] PG[15:2] PG[1:0] PH[15:0] PI[7:0] 136 AF
17xIN
3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2
as AF
3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2
as AF
2 channels, 1 compl. channel, BKIN as AF
1 channel, 1 compl. channel, BKIN as AF
1 channel, 1 compl. channel, BKIN as AF
RX, TX, CK,CTS, RTS as AF
MOSI, MISO, SCK, NSS as AF
MCLK_A, SD_A, FS_A, SCK_A, MCLK_B, SD_B,
FS_B, SCK_B as AF AUDIOCLK as AF
MCLK_A, SD_A, FS_A, SCK_A, MCLK_B, SD_B,
FS_B, SCK_B as AF
RTC_OUT1, RTC_OUT2, RTC_REFIN, RTC_TS
RTC_OUT[8:1], RTC_IN[8:1] VREF+
INP, INN, OUT
INP, INN, OUT
INP, INN, OUT
INP, INN, OUT IN1, IN2, CH1, CH2,
ETR as AF IN1, IN2, CH1, CH2,
ETR as AF IN1, OUT, ETR as AF
SCL, SDA, SMBA as AF MOSI, MISO, SCK, NSS as
AF RX, TX, CTS, RTS_DE as
AF
GPDMA1
TSC
MDF1 GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port F GPIO port G GPIO port H GPIO port I EXT IT. WKP
@VDDA
ADC1
ITF
TIM1/PWM 16b
TIM8/PWM 16b
TIM15 16b
TIM16 16b
TIM17 16b
smcard irDA
USART1
SPI1
SAI1
SAI2
Temperature monitoring @VSW XTAL 32k RTC TAMP
@VDDA VREF buffer
@VDDA COMP1 COMP2
@VDDA OpAmp1 OpAmp2
LPTIM1
LPTIM3
LPTIM4
I2C3/SMBUS
SPI3
LPUART1
APB3 160 MHz
APB2 160 MHz
FIFO FIFO DCACHE1 ICACHE (4 Kbytes) (8 Kbytes)
AHB bus-matrix
FIFO PHY
Figure 1. STM32U585xx block diagram
Flexible static memory controller (FSMC): SRAM, PSRAM, NOR Flash,FRAM, NAND
Flash
OTFDEC1 and Octo-SPI1 memory interface
OTFDEC2 and Octo-SPI2 memory interface
Flash memory (up to 2 Mbytes)
SRAM1 (192 Kbytes) SRAM2 (64 Kbytes) SRAM3 (512 Kbytes)
AES SAES PKA
RNG HASH
@VDDUSB USB FS
AHB/APB2 SYSCFG
AHB1 160 MHz
@VSW BKPSRAM (2 Kbytes)
GTZC1 CRC
CORDIC FMAC
AHB/APB1
AHB2 160 MHz
@VDD SHSI HSI48 MSI HSI16 LSI PLL 1, 2, 3
Reset and clock control
DCMI/PSSI
VDD
@VDD Power management
Voltage regulator LDO and SMPS 3.3 to 1.2 V
Reset Int
@VDD Supply supervision
BOR
PVD, PVM
@VDD XTAL OSC 4- 50 MHz
IWDG
Standby interface
FCLK HCLKx PCLKx
TIM2 32b
TIM3 32b
CRS
TIM4 32b
TIM5 32b
smcard USART2 irDA
smcard USART3 irDA
UART4
UART5
SPI2
APB1 160 MHz (max)
LPDMA1
SRAM4 (16 Kbytes)
WWDG
TIM6 16b TIM7 16b
I2C1/SMBUS I2C2/SMBUS I2C4/SMBUS FDCAN1 UCPD1
LPTIM2
PHY FIFO
CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE, INT as AF
IO[7:0], CLK, NCLK, NCS. DQS as AF IO[7:0], CLK, NCLK, NCS. DQS as AF
DP DM D[15:0], CK, CMD as AF
VDD = 1.71 to 3.6 V VSS
VDDIO, VDDUSB, VDDA, VSSA, VDD, VSS, NRST
OSC_IN OSC_OUT
WKUPx (x=1 to 8) 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR
as AF 4 channels, ETR as AF RX, TX, CK, CTS, RTS as AF RX, TX, CK, CTS, RTS as
AF RX, TX, CTS, RTS as AF RX, TX, CTS, RTS as AF MOSI, MISO, SCK, NSS as AF
SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF TX, RX as AF
CC1, DBCC1, CC2, DBCC2, FRSCC1, FRSCC2 as AF
IN1, IN2, CH1, CH2, ETR as AF
AHB bus-matrix
AHB/APB3
@VDDA D/A converter 1 ITF D/A converter 2
@VDDA
ITF
ADC4
DAC1_OUT1 DAC1_OUT2
19xIN
AHB3 160 MHz
LPGPIO ADF1
GTZC2
VDD power domain
VDDUSB power domain
VSW power domain
VDDIO2 power domain
VDDA power domain
Note: VSW = VDD when VDD is above VBOR0, and VSW = VBAT when VDD is below VBOR0.
IO[15:0] as AF SDIN0, CKIN0, CCK0, CCK1 as AF
MSv60471V5
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Functional overview
3
Functional overview
STM32U585xx
3.1
Arm Cortex-M33 core with TrustZone and FPU
The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor
designed for microcontrollers and deeply embedded applications, especially
those requiring efficient security.
The Cortex-M33 processor delivers a high computational performance with low-
power consumption and an advanced response to interrupts. It features: · Arm
TrustZone technology, using the Armv8-M main extension supporting secure and
non-secure states · MPUs (memory protection units), supporting up to 16
regions for secure and
non-secure applications · Configurable SAU (secure attribute unit) supporting
up to eight memory regions as
secure or non-secure · Floating-point arithmetic functionality with support
for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient
signal processing and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces: · System AHB
bus:
The S-AHB (system AHB) bus interface is used for any instruction fetch and
data access to the memory-mapped SRAM, peripheral, external RAM and external
device, or Vendor_SYS regions of the Armv8-M memory map. · Code AHB bus: The
C-AHB (code AHB) bus interface is used for any instruction fetch and data
access to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32U585xx devices.
3.2
3.2.1
ART Accelerator (ICACHE and DCACHE)
Instruction cache (ICACHE)
The ICACHE is introduced on C-AHB code bus of Cortex-M33 processor to improve
performance when fetching instruction (or data) from both internal and
external memories.
ICACHE offers the following features: · Multi-bus interface:
Slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
Master1 port performing refill requests to internal memories (Flash memory
and SRAMs)
Master2 port performing refill requests to external memories (external Flash
memory and RAMs through Octo-SPI and FMC interfaces)
Second slave port dedicated to ICACHE registers access
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Functional overview
3.2.2
· Close to zero wait-states instructions/data access performance: 0 wait-
state on cache hit Hit-under-miss capability, allowing to serve new
processor requests while a line refill (due to a previous cache miss) is still
ongoing Critical-word-first refill policy, minimizing processor stalls on
cache miss Hit ratio improved by two-ways set-associative architecture and
pLRU-t replacement policy (pseudo-least-recently-used, based on binary tree),
algorithm with best complexity/performance balance Dual master ports
allowing to decouple internal and external memory traffics, on fast and slow
buses, respectively; also minimizing impact on interrupt latency Optimal
cache line refill thanks to AHB burst transactions (of the cache line size)
Performance monitoring by means of a hit counter and a miss counter
· Extension of cacheable region beyond the code memory space, by means of
address remapping logic that allows four cacheable external regions to be
defined
· Power consumption reduced intrinsically (more accesses to cache memory
rather to bigger main memories); even improved by configuring ICACHE as direct
mapped (rather than the default two-ways set-associative mode)
· TrustZone security support · Maintenance operation for software management
of cache coherency · Error management: detection of unexpected cacheable write
access, with optional
interrupt raising
Data cache (DCACHE)
The DCACHE is introduced on S-AHB system bus of Cortex-M33 processor to
improve the performance of data traffic to/from external memories.
DCACHE offers the following features: · Multi-bus interface:
Slave port receiving the memory requests from the Cortex-M33 S-AHB system
port
Master port performing refill requests to external memories (external Flash
memory and RAMs through Octo-SPI and FMC interfaces)
Second slave port dedicated to DCACHE registers access · Close to zero wait-
states external data access performance:
Zero wait-states on cache hit Hit-under-miss capability, allowing to serve
new processor requests to cached
data, while a line refill (due to a previous cache miss) is still ongoing
Critical-word-first refill policy for read transactions, minimizing processor
stalls on
cache miss Hit ratio improved by two-ways set-associative architecture and
pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree),
algorithm with best complexity/performance balance Optimal cache line refill
thanks to AHB burst transactions (of the cache line size) Performance
monitoring by means of two hit counters (for read and write) and two miss
counters (for read and write)
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Functional overview
STM32U585xx
· Supported cache accesses: Both write-back and write-through policies
supported (selectable with AHB bufferable attribute) Read and write-back
always allocated Write-through always non-allocated (write-around) Byte,
half-word and word writes supported
· TrustZone security support · Maintenance operations for software management
of cache coherency:
Full cache invalidation (non interruptible) Address range clean and/or
invalidate operations (background task, interruptible) · Error management:
detection of error for master port request initiated by DCACHE (line eviction
or clean operation), with optional interrupt raising
3.3
Memory protection unit
The MPU (memory protection unit) is used to manage the CPU accesses to the
memory and to prevent one task to accidentally corrupt the memory or the
resources used by any other active task. This memory area is organized into up
to 16 protected areas. The MPU regions and registers are banked across secure
and non-secure states.
The MPU is especially helpful for applications where some critical or
certified code must be protected against the misbehavior of other tasks. It is
usually managed by a RTOS (real-time operating system).
If a program accesses a memory location that is prohibited by the MPU, the
RTOS can detect it and take action. In a RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.4
Embedded Flash memory
The devices feature 2 Mbytes of embedded Flash memory that is available for
storing programs and data. The Flash memory supports 10 000 cycles and up to
100 000 cycles on 512 Kbytes.
A 128-bit instruction prefetch is implemented and can optionally be enabled.
The Flash memory interface features: · Dual-bank operating modes · Read-while-
write (RWW)
This allows a read operation to be performed from one bank while an erase or
program operation is performed to the other bank. The dual-bank boot is also
supported. Each bank contains 128 pages of 8 Kbytes. The Flash memory also
embeds 512-byte OTP (one-time programmable) for user data.
The whole non-volatile memory embeds the ECC (error correction code) feature
supporting: · single-error detection and correction · double-error detection ·
ECC fail address report
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Functional overview
3.4.1
Note:
Flash memory protection
The option bytes allow the configuration of flexible protections:
· write protection (WRP) to protect areas against erasing and programming. Two
areas per bank can be selected with 8-Kbyte granularity.
· RDP (readout protection) to protect the whole memory, has four levels of
protection available (see Table 3 and Table 4):
Level 0: no readout protection
Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the non-
secure Flash memory are possible. The debug access to secure area is
prohibited. Debug access to non-secure area remains possible.
Level 1: memory readout protection
The Flash memory cannot be read from or written to if either the debug
features are connected or the boot in RAM or bootloader are selected. If
TrustZone is enabled, the non-secure debug is possible and the boot in SRAM is
not possible. Regressions from Level 1 to lower levels can be protected by
password authentication.
Level 2: chip readout protection
The debug features, the boot in RAM and the bootloader selection are disabled.
A secure secret key can be configured in the secure options to allow the
regression capability from Level 2 to Level 1. By default (key not
configured), this Level 2 selection is irreversible and JTAG/SWD interfaces
are disabled. If the secret key was previously configured in lower RDP levels,
the device enables the RDP regression from Level 2 to Level 1 after password
authentication through JTAG/SWD interface.
In order to reach the best protection level, it is recommended to activate
TrustZone and to set the RDP Level 2 with password authentication regression
enabled.
Table 3. Access status versus protection level and execution modes when TZEN = 0
Area
RDP level
User execution (boot from Flash memory)
Read
Write
Erase
Debug/boot from RAM/ bootloader(1)
Read
Write
Erase
1
Yes
Yes
Yes
No
No
No(4)
Flash main memory
2
Yes
Yes
Yes
N/A
N/A
N/A
1
Yes
No
No
System memory (2)
2
Yes
No
No
1
Yes
Yes(4)
N/A
Option bytes(3)
2
Yes
No(5)
N/A
OTP
1
Yes
Yes(6)
N/A
2
Yes
Yes(6)
N/A
Yes
No
No
N/A
N/A
N/A
Yes
Yes(4)
N/A
N/A
N/A
N/A
Yes
Yes(6)
N/A
N/A
N/A
N/A
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STM32U585xx
Table 3. Access status versus protection level and execution modes when TZEN = 0 (continued)
Area
RDP level
User execution (boot from Flash memory)
Read
Write
Erase
Debug/boot from RAM/ bootloader(1)
Read
Write
Erase
1
Yes
Yes
N/A
No
No
N/A(7)
Backup registers
2
Yes
Yes
N/A
N/A
N/A
N/A
SRAM2/backup
1
Yes
Yes
N/A
No
No
N/A(8)
RAM
2
Yes
Yes
N/A
N/A
N/A
N/A
OTFDEC regions
1
Yes
Yes
Yes
No(9)
Yes
Yes
(Octo-SPI)
2
Yes
Yes
Yes
N/A
N/A
N/A
1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled. 2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode. 3. Option bytes are only accessible through the Flash memory registers and OPSTRT bit. 4. The Flash main memory is erased when the RDP option byte changes from level 1 to level 0. 5. SWAP_BANK option bit can be modified. 6. OTP can only be written once. 7. The backup registers are erased when RDP changes from level 1 to level 0. 8. All SRAMs are erased when RDP changes from level 1 to level 0. 9. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.
Table 4. Access status versus protection level and execution modes when TZEN = 1
Area
RDP level
User execution (boot from Flash memory)
Read
Write
Erase
Debug/ bootloader(1)
Read
Write
Erase
0.5
Yes
Yes
Yes
Yes(2)
Yes(2)
Yes(2)
Flash main memory 1
Yes
Yes
Yes
No
No
No(5)
2
Yes
Yes
Yes
N/A
N/A
N/A
0.5
Yes
No
No
Yes
No
No
System memory (3)
1
Yes
No
No
Yes
No
No
2
Yes
No
No
0.5
Yes
Yes(5)
N/A
Option bytes(4)
1
Yes
Yes(5)
N/A
2
Yes
No(6)
N/A
N/A
N/A
N/A
Yes
Yes (5)
N/A
Yes
Yes(5)
N/A
N/A
N/A
N/A
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Functional overview
Table 4. Access status versus protection level and execution modes when TZEN = 1 (continued)
Area
RDP level
User execution (boot from Flash memory)
Read
Write
Erase
Debug/ bootloader(1)
Read
Write
Erase
0.5
Yes
Yes(7)
N/A
Yes
Yes(7)
N/A
OTP
1
Yes
Yes(7)
N/A
Yes
Yes(7)
N/A
2
Yes
Yes(7)
N/A
N/A
N/A
N/A
0.5
Yes
Yes
N/A
Yes(2)
Yes(2)
N/A(8)
Backup registers
1
Yes
Yes
N/A
No
No
N/A(8)
2
Yes
Yes
N/A
N/A
N/A
N/A
0.5
Yes
Yes
N/A
Yes(2)
Yes(2)
N/A(9)
SRAM2/backup RAM
1
Yes
Yes
N/A
No
No
N/A(9)
2
Yes
Yes
N/A
N/A
N/A
N/A
0.5
Yes
Yes
Yes
No(10)
Yes
Yes
OTFDEC regions (Octo-SPI)
1
Yes
Yes
Yes
No(10)
Yes
Yes
2
Yes
Yes
Yes
N/A
N/A
N/A
1. When the protection level 2 is active, the debug port and the bootloader mode are disabled. 2. Depends on TrustZone security access rights. 3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode. 4. Option bytes are only accessible through the Flash memory registers and OPSTRT bit. 5. The Flash main memory is erased when the RDP option byte regresses from level 1 to level 0. 6. SWAP_BANK option bit can be modified. 7. OTP can only be written once. 8. The backup registers are erased when RDP changes from level 1 to level 0. 9. All SRAMs are erased when RDP changes from level 1 to level 0. 10. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.
3.4.2
Additional Flash memory protections when TrustZone activated
When the TrustZone security is enabled through option bytes, the whole Flash
memory is secure after reset and the following protections are available: ·
non-volatile watermark-based secure Flash memory area
The secure area can be accessed only in Secure mode. One area per bank can be
selected with a page granularity. · secure HDP (hide protection area) It is
part of the Flash memory secure area and can be protected to deny an access to
this area by any data read, write and instruction fetch. For example, a
software code in the secure Flash memory hide protection area can be executed
only once and deny
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Functional overview
STM32U585xx
3.4.3
any further access to this area until next system reset. One area per bank can
be selected at the beginning of the secure area. · volatile block-based secure
Flash memory area Each page can be programmed on-the-fly as secure or non-
secure.
FLASH privilege protection
Each Flash memory page can be programmed on-the-fly as privileged or
unprivileged.
3.5
3.5.1 3.5.2
Embedded SRAMs
Five SRAMs are embedded in the STM32U585xx devices, each with specific
features. SRAM1, SRAM2, and SRAM3 are the main SRAMs. SRAM4 is in the SRAM
used for peripherals LPBAM (low-power background autonomous mode) in Stop 2
mode.
These SRAMs are made of several blocks that can be powered down in Stop mode
to reduce consumption: · SRAM1: three 64-Kbyte blocks (total 192 Kbytes) ·
SRAM2: 8-Kbyte + 56-Kbyte blocks (total 64 Kbytes) with optional ECC. In
addition
SRAM2 blocks can be retained in Standby mode. · SRAM3: eight 64-Kbyte blocks
(total 512 Kbytes) with optional ECC. When ECC is
enabled, 256 Kbytes support ECC and 192 Kbytes of SRAM3 can be accessed
without ECC. · SRAM4: 16 Kbytes · BKPSRAM (backup SRAM): 2 Kbytes with
optional ECC. The BKPSRAM can be retained in all low-power modes and when VDD
is off in VBAT mode, but not in Shutdown mode.
SRAMs TrustZone security
When the TrustZone security is enabled, all SRAMs are secure after reset. The
SRAM1, SRAM2, SRAM3, SRAM4 can be programmed as secure or non-secure by
blocks, using the MPCBB (block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM
regions can be programmed as secure or non-secure with watermark, using the
TZSC (TrustZone security controller) in the GTZC (global TrustZone
controller).
SRAMs privilege protection
The SRAM1, SRAM2, SRAM3, SRAM4 can be programmed as privileged or unprivileged
by blocks, using the MPCBB. The granularity of SRAM privilege block based is a
page of 512 bytes. Backup SRAM regions can be programmed as privileged or
unprivileged with watermark, using the TZSC (TrustZone security controller) in
the GTZC (global TrustZone controller).
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3.6
TrustZone security architecture
The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based
on secure and non-secure state.
· SAU: up to eight SAU configurable regions are available for security
attribution.
· IDAU: It provides a first memory partition as non-secure or non-secure
callable attributes. It is then combined with the results from the SAU
security attribution and the higher security state is selected.
Based on IDAU security attribution, the Flash memory, system SRAM and peripheral memory space is aliased twice for secure and non-secure states. However, the external memory space is not aliased.
The table below shows an example of typical SAU region configuration based on
IDAU regions. The user can split and choose the secure, non-secure or NSC
regions for external memories as needed.
Table 5. Example of memory map security attribution versus SAU configuration
regions
Region description
Address range
IDAU security attribution
SAU security attribution typical
configuration
Final security attribution
Code – external memories Code – Flash and SRAM
Code – external memories
SRAM
Peripherals External memories
1. NSC = non-secure callable.
0x0000 0000 0x07FF FFFF
0x0800 0000 0x0BFF FFFF
0x0C00 0000 0x0FFF FFFF
0x1000 0000 0x17FF FFFF
0x1800 0000 0x1FFF FFFF
0x2000 0000 0x2FFF FFFF
0x3000 0000 0x3FFF FFFF
0x4000 0000 0x4FFF FFFF
0x5000 0000 0x5FFF FFFF
0x6000 0000 0xDFFF FFF
Non-secure Non-secure
Secure or
Secure or
non-secure or NSC(1) non-secure or NSC
Non-secure
Non-secure
NSC
Secure or NSC
Secure or NSC
Non-secure
Non-secure NSC
Non-secure NSC
Non-secure
Non-secure
Secure or NSC
Secure or NSC
Non-secure
Non-secure
Secure or NSC
Secure or NSC
Secure or
Secure or
non-secure or NSC non-secure or NSC
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3.6.1 3.6.2
TrustZone peripheral classification
When the TrustZone security is active, a peripheral can be either securable or
TrustZone-aware type as follows: · securable: peripheral protected by an
AHB/APB firewall gate that is controlled from
TZSC to define security properties · TrustZone-aware: peripheral connected
directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure
Default TrustZone security state
The default system security state is detailed below: · CPU:
Cortex-M33 is in secure state after reset. The boot address must be in
secure address.
· Memory map: SAU is fully secure after reset. Consequently, all memory map
is fully secure. Up to eight SAU configurable regions are available for
security attribution.
· Flash memory: Flash memory security area is defined by watermark user
options. Flash memory block based area is non-secure after reset.
· SRAMs: All SRAMs are secure after reset. MPCBB (memory protection block
based controller) is secure.
· External memories: FSMC, OCTOSPI banks are secure after reset. MPCWMx
(memory protection watermark based controller) is secure.
· Peripherals Securable peripherals are non-secure after reset. TrustZone-
aware peripherals are non-secure after reset. Their secure configuration
registers are secure.
· All GPIOs are secure after reset. · Interrupts:
NVIC: All interrupts are secure after reset. NVIC is banked for secure and
nonsecure state.
· TZIC: All illegal access interrupts are disabled after reset.
3.7
Boot modes
At startup, a BOOT0 pin, nBOOT0, NSBOOTADDx[24:0] (x = 0, 1) and SECBOOTADD0[24:0] option bytes are used to select the boot memory address that includes: · Boot from any address in user Flash memory. · Boot from system memory bootloader. · Boot from any address in embedded SRAM. · Boot from RSS (root security services).
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The BOOT0 value comes from the PH3-BOOT0 pin or from an option bit depending
on the value of a user option bit to free the GPIO pad if needed.
The bootloader is located in the system memory, programmed by ST during
production. The bootloader is used to reprogram the Flash memory by using
USART, I2C, SPI, FDCAN or USB FS in device mode through the DFU (device
firmware upgrade).
The bootloader is available on all devices. Refer to the application note
STM32 microcontroller system memory boot mode (AN2606) for more details.
The RSS are embedded in a Flash memory area named secure information block,
programmed during ST production.
For example, the RSS enable the SFI (secure firmware installation), thanks to
the RSSe SFI (RSS extension firmware).
This feature allows customer to produce the confidentiality of the firmware to
be provisioned into the STM32, when production is sub-contracted to untrusted
third party.
The RSS are available on all devices, after enabling the TrustZone through the
TZEN option bit. Refer to the application note Overview secure firmware
install (SFI) (AN4992) for more details.
Refer to Table 6 and Table 7 for boot modes when TrustZone is disabled and
enabled respectively.
nBOOT0 FLASH_ OPTR[27] –
–
1
0
Table 6. Boot modes when TrustZone is disabled (TZEN = 0)
BOOT0 pin PH3
nSWBOOT0 FLASH_ OPTR[26]
Boot address option-byte
selection
Boot area
ST programmed default value
Boot address defined by
0
1
NSBOOTADD0[24:0]
user option bytes
Flash: 0x0800 0000
NSBOOTADD0[24:0]
1
1
Boot address defined by
NSBOOTADD1[24:0]
user option bytes
NSBOOTADD1[24:0]
Bootloader: 0x0BF9 0000
Boot address defined by
–
0
NSBOOTADD0[24:0]
user option bytes
Flash: 0x0800 0000
NSBOOTADD0[24:0]
–
0
Boot address defined by
NSBOOTADD1[24:0]
user option bytes
NSBOOTADD1[24:0]
Bootloader: 0x0BF9 0000
When TrustZone is enabled by setting the TZEN option bit, the boot space must
be in the secure area. The SECBOOTADD0[24:0] option bytes are used to select
the boot secure memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option
bit, allowing to boot always at the address selected by SECBOOTADD0[24:0]
option bytes. All other boot options are ignored.
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Table 7. Boot modes when TrustZone is enabled (TZEN = 1)
BOOT_ LOCK
nBOOT0 FLASH_ OPTR[27]
BOOT0 pin PH3
nSWBOOT0 FLASH_ OPTR[26]
RSS command
Boot address option-bytes
selection
Boot area
ST programmed default value
–
0
Secure boot address
1
0
SECBOOTADD0 [24:0]
defined by user option bytes
Flash: 0x0C00 0000
SECBOOTADD0[24:0]
–
1
1
0
N/A
RSS
RSS: 0x0FF8 0000
0
1
–
Secure boot address
0
0
SECBOOTADD0 [24:0]
defined by user option bytes
Flash: 0x0C00 0000
SECBOOTADD0[24:0]
0
–
–
–
1
–
–
0
0
N/A
RSS
RSS: 0x0FF8 0000
–
0
N/A
RSS
RSS: 0x0FF8 0000
Secure boot address
–
–
SECBOOTADD0 [24:0]
defined by user option bytes
Flash: 0x0C00 0000
SECBOOTADD0[24:0]
The boot address option bytes allow any boot memory address to be programmed.
However, the allowed address space depends on the Flash memory RDP level.
If the programmed boot memory address is out of the allowed memory mapped area
when RDP level is 0.5 or more, the default boot address is forced either in
secure Flash memory or non-secure Flash memory, depending on TrustZone
security option as described in the table below.
RDP 0 0.5 1
2
Table 8. Boot space versus RDP protection
TZEN = 1
TZEN = 0
Any boot address
Any boot address
N/A
Boot address only in RSS or secure Flash memory: 0x0C00 0000 – 0x0C1F FFFF
Otherwise, forced boot address is 0x0FF8 0000.
Any boot address
Boot address only in Flash memory 0x0800 0000 – 0x081F FFFF
Otherwise, forced boot address is 0x0800 0000.
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3.8
Global TrustZone controller (GTZC)
GTZC is used to configure TrustZone and privileged attributes within the full
system.
The GTZC includes three different sub-blocks: · TZSC: TrustZone security
controller
This sub-block defines the secure/privilege state of slave/master peripherals.
It also controls the non-secure area size for the watermark memory peripheral
controller (MPCWM). The TZSC block informs some peripherals (such as RCC or
GPIOs) about the secure status of each securable peripheral, by sharing with
RCC and I/O logic. · TZIC: TrustZone illegal access controller This sub-block
gathers all security illegal access events in the system and generates a
secure interrupt towards NVIC. · MPCBB: MPCBB: block-based memory protection
controller This sub-block controls secure states of all memory blocks
(512-byte pages) of the associated SRAM. This peripheral aims at configuring
the internal RAM in a TrustZone system product having segmented SRAM with
programmable-security and privileged attributes.
The GTZC main features are: · Three independent 32-bit AHB interfaces for
TZSC, TZIC and MPCBB · Secure and non-secure access supported for
privileged/unprivileged part of TZSC · Set of registers to define product
security settings:
Secure/privilege regions for external memories Secure/privilege access
mode for securable peripherals Secure/privilege access mode for securable
legacy masters
3.9
Power supply management
The PWR (power controller) main features are: · Power supplies and supply
domains
Core domain (VCORE) VDD domain Backup domain (VBAT) Analog domain
(VDDA) SMPS power stage (VDDSMPS, available only on SMPS packages) VDDIO2
domain VDDUSB for USB transceiver · System supply voltage regulation SMPS
step down converter Voltage regulator (LDO) · Power supply supervision BOR
monitor PVD monitor PVM monitor (VDDA, VDDUSB, VDDIO2)
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3.9.1
Note:
· Power management
Operating modes
Voltage scaling control
Low-power modes
· VBAT battery charging · TrustZone security and privileged protection
Power supply schemes
The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several
independent supplies can be provided for specific peripherals:
· VDD = 1.71 V to 3.6 V (functionality guaranteed down to VBORx min value) VDD
is the external power supply for the I/Os, the internal regulator and the
system analog such as reset, power management and internal clocks. It is
provided externally through the VDD pins.
· VDDA = 1.58 V (COMPs) / 1.6 V (DACs, OPAMPs) / 1.62 V (ADCs) / 1.8 V
(VREFBUF) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs, voltage reference
buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage and must be connected to VDD or VSS pin
(preferably to VDD) when these peripherals are not used.
· VDDSMPS = 1.71 V to 3.6 V VDDSMPS is the external power supply for the SMPS
step down converter. It is provided externally through VDDSMPS supply pin and
must be connected to the same supply than VDD.
· VLXSMPS is the switched SMPS step down converter output.
The SMPS power supply pins are available only on a specific package with SMPS
step down converter option.
· VDDUSB = 3.0 V to 3.6 V VDDUSB is the external independent power supply for
USB transceivers. VDDUSB voltage level is independent from the VDD voltage and
must be connected to VDD or VSS pin (preferably to VDD) when the USB is not
used.
· VDDIO2 = 1.08 V to 3.6 V VDDIO2 is the external power supply for 14 I/Os
(port G[15:2]). The VDDIO2 voltage level is independent from the VDD voltage
and must be connected to VDD or VSS pin (preferably to VDD) when PG[15:2] are
not used.
· VBAT = 1.65 V to 3.6 V (functionality guaranteed down to VBOR_VBAT min
value) VBAT is the power supply for RTC, TAMP, external clock 32 kHz
oscillator and backup registers (through power switch) when VDD is not
present.
· VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output
of the internal voltage reference buffer when enabled.
VREF+ can be grounded when ADC and DAC are not active. The internal voltage
reference buffer supports four outputs:
VREF+ around 1.5 V. This requires VDDA 1.8 V. VREF+ around 1.8 V. This
requires VDDA 2.1 V.
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VREF+ around 2.048 V. This requires VDDA 2.4 V. VREF+ around 2.5 V. This
requires VDDA 2.8 V. VREF- and VREF+ pins are not available on all packages.
When not available, they are bonded to VSSA and VDDA, respectively. When the
VREF+ is double-bonded with VDDA in a package, the internal voltage reference
buffer is not available and must be kept disabled. VREF- must always be equal
to VSSA.
The STM32U585xx devices embed two regulators: one LDO and one SMPS in parallel
to provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3 and
SRAM4 and embedded Flash memory. The SMPS generates this voltage on VDD11 (two
pins), with a total external capacitor of 4.7 F typical. SMPS requires an
external coil of 2.2 H typical. The LDO generates this voltage on VCAP pin
connected to an external capacitor of 4.7 F typical.
Both regulators can provide four different voltages (voltage scaling) and can
operate in Stop modes.
It is possible to switch from SMPS to LDO and from LDO to SMPS on-the-fly.
Figure 2. STM32U585xQ power supply overview (with SMPS)
VDDA VSSA VDDUSB
VSS VDDIO2
VSS
VSS VDD 2x VDD11 VLXSMPS VDDSMPS VSSSMPS
VBAT
VDDA domain
A/D converters Comparators D/A converters Operational amplifiers Voltage
reference buffer
USB transceiver
VDDIO2 domain
VDDIO2
I/O ring
PG[15:2]
VDD domain VDDIO1 I/O ring
Reset block Temperature sensor 3 x PLL Internal RC oscillators
Standby circuitry (Wakeup logic, IWDG)
Voltage regulator LDO regulator
SMPS regulator
VCORE
VCORE domain
Core
SRAM1 SRAM2 SRAM3 SRAM4
Digital peripherals
Low-voltage detector
Backup domain
LSE crystal 32kHz oscillator Backup registers RCC_BDCR register RTC TAMP
BKPSRAM
Flash memory
MSv63604V2
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Figure 3. STM32U585xx power supply overview (without SMPS)
VDDA VSSA
VDDA domain
A/D converters Comparators D/A converters Operational amplifiers Voltage
reference buffer
VDDUSB VSS
VDDIO2 VSS
VSS VDD VCAP
USB transceiver
VDDIO2 domain
VDDIO2
I/O ring
PG[15:2]
VDD domain
VDDIO1 I/O ring
Reset block Temperature sensor 3 x PLL Internal RC oscillators
Standby circuitry (Wakeup logic, IWDG)
VCORE
LDO regulator
VCORE domain
Core
SRAM1 SRAM2 SRAM3 SRAM4
Digital peripherals
VBAT
Low-voltage detector
Backup domain
LSE crystal 32kHz oscillator Backup registers RCC_BDCR register RTC TAMP
BKPSRAM
Flash memory
MSv64350V3
During power-up and power-down phases, the following power sequence
requirements must be respected:
· When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must
remain below VDD + 300 mV.
· When VDD is above 1 V, all power supplies are independent.
· During the power-down phase, VDD can temporarily become lower than other
supplies only if the energy provided to the MCU remains below 1 mJ. This
allows external decoupling capacitors to be discharged with different time
constants during the power-down transient phase.
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V 3.6
VBOR0 1
Functional overview Figure 4. Power-up /down sequence
VDDX(1) VDD
3.9.2
0.3
Power-on
Operating mode
Power-down
time
Invalid supply area
VDDX < VDD + 300 mV
VDDX independent from VDD
1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.
MSv47490V1
Power supply supervisor
The devices have an integrated ultra-low-power BOR (Brownout reset) active in
all modes (except for Shutdown mode). The BOR ensures proper operation of the
device after power on and during power down. The device remains in reset mode
when the monitored supply voltage VDD is below a specified threshold, without
the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be
selected through option bytes.The devices feature an embedded PVD
(programmable voltage detector) that monitors the VDD power supply and
compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below and/or rises above the VPVD
threshold. The interrupt service routine can then generate a warning message
and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor that compares the
independent supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the
peripheral is in its functional supply range.
The devices support dynamic voltage scaling to optimize its power consumption
in Run mode. The voltage from the main regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
· Range 1 (VCORE = 1.2 V) with CPU and peripherals running at up to 160 MHz ·
Range 2 (VCORE = 1.1 V) with CPU and peripherals running at up to 110 MHz ·
Range 3 (VCORE = 1.0 V) with CPU and peripherals running at up to 55 MHz ·
Range 4 (VCORE = 0.9 V) with CPU and peripherals running at up to 25 MHz
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Mode Run Sleep Stop 0
Stop 1
Low-power modes
The ultra-low-power STM32U585xx devices support seven low-power modes to
achieve the best compromise between low-power consumption, short startup time,
available peripherals and available wakeup sources.
The table below details the related low-power modes.
Table 9. STM32U585xx modes overview
Regulator(1) CPU Flash SRAM Clocks
DMA and peripherals(2)
Wakeup source
Range 1 Range 2 Range 3 Range 4 Range 1 Range 2 Range 3 Range 4 Range 1 Range
2 Range 3 Range 4
LPR
Yes ON(3) ON No ON ON(4)
No OFF ON(5)
All
Any
N/A
All except OTG_FS and UCPD
All Any
Any interrupt or event
All except OTG_FS, and UCPD
BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP (temp. sensor), VREFBUF, ADC4(7), DAC1 (2 channels)(8),
COMPx (x = 1, 2),
OPAMPx (x = 1, 2),
LSE USARTx (x = 1…5)(9),
LSI
(6)
LPUART1,
SPIx (x = 1…3)(10),
I2Cx (x = 1…4)(11),
LPTIMx (x = 1…4)(12),
MDF1(13), ADF1,
GPIO, LPGPIO, GPDMA1(14), LPDMA1
Reset pin, all I/Os, BOR, PVD, PVM, RTC, TAMP, IWDG, TEMP, ADC4, DAC1 (2 channels), COMPx (x = 1, 2), USARTx (x = 1…5), LPUART1, SPIx (x = 1…3), I2Cx (x = 1…4), LPTIMx (x = 1…4), MDF1, ADF1, GPDMA1, LPDMA1, OTG_FS, UCPD
All other peripherals are frozen.
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Mode Stop 2
Table 9. STM32U585xx modes overview (continued)
Regulator(1) CPU Flash SRAM Clocks
DMA and peripherals(2)
BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP, VREFBUF,
ADC4,
DAC1 (2 channels),
COMPx (x = 1, 2),
OPAMPx (x = 1, 2),
LPR
No OFF ON(5)
LSE LPUART1, LSI SPI3,
I2C3,
LPTIMx (x = 1, 3, 4),
ADF1,
LPGPIO,
LPDMA1
Wakeup source
Reset pin, all I/Os, BOR, PVD, PVM, RTC, TAMP, IWDG, TEMP, ADC4, COMPx (x = 1,
2), LPUART1, SPI3, I2C3, LPTIMx (x = 1,3,4), ADF1, LPDMA1
Stop 3
All other peripherals are frozen.
BOR,
Reset pin,
RTC, TAMP, IWDG,
24 I/Os (WKUPx),
DAC1 (2 static channels),
BOR, RTC, TAMP,
LPR
No OFF ON(5)
LSE OPAMPx (x = 1, 2)
IWDG
LSI
All other peripherals are frozen.
LPR Standby
OFF
I/O configuration can be floating, pull-up or pull-down.
BOR, RTC, TAMP, IWDG
All other peripherals are powered off.
Reset pin, 24 I/Os (WKUPx), BOR, RTC, TAMP, IWDG
LSE I/O configuration can be floating, LSI pull-up or pull-down.
64-, 56- or 8-Kbyte SRAM2 2-Kbyte BKPSRAM(5)
all other SRAMs powered off
Powered off
Powered off
OFF
Shutdown
OFF
Powered off
OFF
Powered off
RTC, TAMP
All other peripherals are LSE powered off.
Reset pin, 24 I/Os (WKUPx), RTC, TAMP
I/O configuration can be floating, pull-up or pull-down(15).
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1. LPR means that the main regulator is OFF and the low-power regulator is
ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off
when executing from SRAM. One bank can also be put in power-down mode.
4. The SRAM1, SRAM2, SRAM3, SRAM4 and BKPSRAM clocks can be gated on or off
independently.
5. The SRAM can be individually powered off to save power consumption.
6. MSI and HSI16 can be temporary enabled upon peripheral request, for
autonomous functions with DMA or wakeup from Stop event detections.
7. The ADC4 conversion is functional and autonomous with DMA in Stop mode,
and can generate a wakeup interrupt on conversion events.
8. DAC1 is the digital-to-analog (D/A) converter controller instance name.
This instance controls two D/A converters also called “two channels”. The DAC
conversions are functional and autonomous with DMA in Stop mode.
9. U(S)ART and LPUART transmission and reception is functional and autonomous
with DMA in Stop mode, and can generate a wakeup interrupt on transfer events.
10. SPI transmission and reception is functional and autonomous with DMA in
Stop mode, and can generate a wakeup interrupt on transfer events.
11. I2C transmission and reception is functional and autonomous with DMA in
Stop mode, and can generate a wakeup interrupt on transfer events.
12. LPTIM is functional and autonomous with DMA in Stop mode, and can
generate a wakeup interrupt on all events.
13. MDF and ADF are functional and autonomous with DMA in Stop mode, and can
generate a wakeup interrupt on events.
14. GPDMA and LPDMA are functional and autonomous in Stop mode, and can
generate a wakeup interrupt on events.
15. I/Os can be configured with internal pull-up, pull-down or floating in
Shutdown mode but the configuration is lost when exiting the Shutdown mode.
By default, the microcontroller is in Run mode after a system or a power
reset. It is up to the user to select one of the low-power modes described
below:
· Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate
and can wake up the CPU when an interrupt/event occurs.
· Stop 0, Stop 1, Stop 2 and Stop 3 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the
MSI, the HSI16, the HSI48 and the HSE crystal oscillators are disabled. The
LSE or LSI is still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals are autonomous and can operate in Stop mode by requesting
their kernel clock and their bus (APB or AHB) when needed, in order to
transfer data with DMA (GPDMA1 in Stop 0 and Stop 1 modes, LPDMA1 in Stop 0,
Stop 1 and Stop 2 modes). Refer to Low-power background autonomous mode
(LPBAM) for more details. LPBAM is not supported in Stop 3 mode.
In Stop 2 and Stop 3 modes, most of the VCORE domain is put in a lower leakage
mode. Stop 0 and Stop 1 modes offer the largest number of active peripherals
and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2
mode.
In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup
time but with much higher consumption.
Stop 3 is the lowest power mode with full retention, but the functional
peripherals and sources of wakeup are reduced to the same ones than in Standby
mode.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 mode can be either
MSI up to 24 MHz or HSI16, depending on software configuration.
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· Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off.
The PLL, the MSI, the HSI16, the HSI48 and the HSE crystal oscillators are
also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O
with internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAMs and register contents are lost except for
registers and backup SRAM in the Backup domain and Standby circuitry.
Optionally, the full SRAM2 or 8 Kbytes or 56 Kbytes can be retained in Standby
mode, supplied by the low-power regulator (Standby with SRAM2 retention mode).
The BOR can be configured in ultra-low-power mode to further reduce power
consumption during Standby mode.
The device exits Standby mode when an external reset (NRST pin), an IWDG
reset, WKUP pin event (configurable rising or falling edge), an RTC event
occurs (alarm, periodic wakeup, timestamp), or a tamper detection. The tamper
detection can be raised either due to external pins or due to an internal
failure detection.
The system clock after wakeup is MSI up to 4 MHz.
· Shutdown mode
The lowest power consumption is achieved in Shutdown mode. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL,
the HSI16, the HSI48, the MSI, the LSI and the HSE oscillators are also
switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is
possible in this mode, therefore the switch to Backup domain is not supported
(VBAT). SRAMs and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp), or a tamper detection.
The system clock after wakeup is MSI at 4 MHz.
Low-power background autonomous mode (LPBAM)
The ultra-low-power STM32U585xx devices support LPBAM (low-power background
autonomous mode) that allows peripherals to be functional and autonomous in
Stop mode (Stop 0, Stop 1 and Stop 2 modes), so without any software running.
In Stop 0 and Stop 1 modes, the autonomous peripherals are the following:
ADC4, DAC1, LPTIMx (x = 1 to 4), USARTx (x = 1 to 5), LPUART1, SPIx (x = 1 to
3), I2Cx (x = 1 to 4), MDF1, ADF1, GPDMA1 and LPDMA1. In these modes, SRAM1,
SRAM2, SRAM3 and SRAM4 can be accessed by the GPDMA1, and SRAM4 can be
accessed by the LPDMA1.
In Stop 2 mode, the autonomous peripherals are the following: ADC4, DAC1,
LPTIM1, LPTIM3, LPTIM4, LPUART1, SPI3, I2C3, ADF1 and LPDMA1. In this mode,
the SRAM4 can be accessed by the LPDMA1.
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Those peripherals support the features detailed below:
· Functionality in Stop mode thanks to its own independent clock (named kernel
clock) request capability: the peripheral kernel clock is automatically
switched on when requested by a peripheral, and automatically switched off
when no peripheral requests it.
· DMA transfers supported in Stop mode thanks to system clock request
capability: the system clock (MSI or HSI16) automatically switched on when
requested by a peripheral, and automatically switched off when no peripheral
requests it. When the system clock is requested by an autonomous peripheral,
the system clock is woken up and distributed to all peripherals enabled in the
RCC. This allows the DMA to access the enabled SRAM, and any enabled
peripheral register (for instance GPIO or LPGPIO registers).
· Automatic start of the peripheral thanks to hardware synchronous or
asynchronous triggers (such as I/Os edge detection and low-power timer event).
· Wakeup from Stop mode with peripheral interrupt.
The GPDMA and LPDMA are fully functional and the linked-list is updated in
Stop mode, allowing the different DMA transfers to be linked without any CPU
wakeup. This can be used to chain different peripherals transfers, or to write
peripherals registers in order to change their configuration while remaining
in Stop mode.
The DMA transfers from memory to memory can be started by hardware synchronous
or asynchronous triggers, and the DMA transfers between peripherals and
memories can also be gated by those triggers.
Here below some use-cases that can be done while remaining in Stop mode:
· A/D or D/A conversion triggered by a low-power timer (or any other trigger)
wakeup from Stop mode on analog watchdog if the A/D conversion result is out
of programmed thresholds
wakeup from Stop mode on DMA buffer event
· Audio digital filter data transfer into SRAM
wakeup from Stop on sound-activity detection · I2C slave reception or
transmission, SPI reception, UART/LPUART reception
wakeup at the end of peripheral transfer or on DMA buffer event · I2C master
transfer, SPI transmission, UART/LPUART transmission, triggered by
a low-power timer (or any other trigger):
example: sensor periodic read
wakeup at the end of peripheral transfer or on DMA buffer event
· Bridges between peripherals
example: ADC converted data transferred by communication peripherals
· Data transfer from/to GPIO/LPGPIO to/from SRAM for:
controlling external components
implementing data transmission and reception protocols
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STM32U585xx
Functional overview
Table 10. Functionalities depending on the working mode(1)
Stop 0/1
Stop 2
Stop 3 Standby Shutdown
Peripheral
Run Sleep
VBAT
–
–
–
–
–
Wakeup capability Wakeup capability Wakeup capability Wakeup capability Wakeup capability
CPU
Y
–
–
–
–
– ——
–
Flash memory (2 Mbytes)
O(2)
O(2)
–
–
–
– ——
–
SRAM1 (192 Kbytes) Y(3)(4) Y(3)(4) O(7) – O(7) – O(7) –
–
–
–
–
–
SRAM2 (64 Kbytes)
Y(3)(4) Y(3)(4) O(7) O(5) O(7)
– O(7) – O(6) –
–
–
–
SRAM3 (512 Kbytes) Y(3)(4) Y(3)(4) O(7) O(5) O(7) – O(7) –
–
–
–
–
–
SRAM4 (16 Kbytes)
Y(3)(4) Y(3)(4) O(7) –
O(7)
– O(7) –
–
–
–
–
–
BKPSRAM
O(4)
O(4)
O O(5) O
O
O
–
O
FSMC
O
O
–
–
–
– ——
–
OCTOSPIx (x = 1,2)
O
O
–
–
–
– ——
–
Backup registers
Y
Y
Y
–
Y
– Y-Y-Y-
Y
BOR (Brownout reset) Y
Y
Y Y Y Y YYYY – –
–
PVD (programmable voltage detector)
O
O
OO O O- – – – – –
–
Peripheral voltage monitor
GPDMA1
LPDMA1
O
O
OO O O- – – – – –
–
O
O
O O(8) –
– ——
–
O
O
O O(9) O O(9) –
–
–
–
–
–
–
DMA2D
O
O
HSI16 (high-speed internal)
HSI48 oscillator
O
O
(10)
–
(10)
–
–
–
–
–
–
–
–
O
O
–
–
–
–
–
—-
–
–
HSE (high-speed external)
O
O
–
–
–
– ——
–
LSI (low-speed internal)
O
O
O
–
O
– O-O- – –
O
LSE (low-speed external)
O
O
O
–
O
– O-O-O-
O
MSIS and MSIK (multi-speed internal)
O
O
(10)
–
(10)
–
–
–
–
–
–
–
–
CSS (clock security system)
O
O
–
–
–
– ——
–
Clock security system on LSE
O
O
OO O
O OOOOOO
O
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STM32U585xx
Table 10. Functionalities depending on the working mode(1) (continued)
Stop 0/1
Stop 2
Stop 3 Standby Shutdown
Peripheral
Run Sleep
VBAT
–
–
–
–
–
Wakeup capability Wakeup capability Wakeup capability Wakeup capability Wakeup capability
Backup domain voltage and temperature monitoring
O
O
OO O
O OOOOOO
O
RTC/TAMP
O
O
OO O
O OOOOOO
O
Number of RTC tamper pins
OTG_FS, UCPD
8
8
8 O 8 O 8O8O8O
8
O(11) O(11)
–
O
–
– ——
–
USARTx (x = 1,2,3,4,5)
O
O
O(12) O(12) –
– ——
–
Low-power UART (LPUART1) I2Cx (x = 1,2,4) I2C3 SPIx (x = 1,2) SPI3
O
O
O(12) O(12) O(12) O(12) –
–
–
–
–
–
–
O
O
O(13) O(13) –
– ——
–
O
O
O(13) O(13) O(13) O(13) –
–
–
–
–
–
–
O
O
O(14) O(14) –
– ——
–
O
O
O(14) O(14) O(14) O(14)
FDCAN1
O
O
–
–
–
– ——
–
SDMMCx (x = 1,2)
O
O
–
–
–
– ——
–
SAIx (x = 1,2)
O
O
–
–
–
– ——
–
ADC1 ADC4
O
O
–
–
–
– ——
–
O
O
O(15) O(15) O(15) O(15) –
–
–
–
–
–
–
DAC1 (2 converters)
O
O
O
–
O
–
——
–
VREFBUF
O
O
O
–
O
–
——
–
OPAMPx (x = 1,2)
O
O
O
–
O
–
——
–
COMPx (x = 1,2)
O
O
OOO O- – – – – –
–
Temperature sensor
O
O
O
–
O
– ——
–
Timers (TIMx)
O
O
–
–
–
– ——
–
LPTIMx (x = 1,3,4)
O
O
O(16) O(16) O(16) O(16) –
–
–
–
–
–
–
LPTIM2
O
IWDG (independent watchdog)
O
WWDG (window watchdog)
O
O
O(16) O(16) –
– ——
–
O
O O O O OOOO – –
–
O
–
–
–
– ——
–
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DS13086 Rev 3
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STM32U585xx
Functional overview
Table 10. Functionalities depending on the working mode(1) (continued)
Stop 0/1
Stop 2
Stop 3 Standby Shutdown
Peripheral
Run Sleep
VBAT
–
–
–
–
–
Wakeup capability Wakeup capability Wakeup capability Wakeup capability Wakeup capability
SysTick timer
O
O
–
–
–
– ——
–
MDF1 (multi-function digital filter)
O
O
O(17) O(17) –
– ——
–
ADF1 (audio digital filter)
O
O
O(17) O(17) O(17) O(17) –
–
–
–
–
–
–
DCMI (digital camera interface)
O
O
–
–
–
– ——
–
PSSI (paral. synch. slave interface)
O
O
–
–
–
– ——
–
CORDIC coprocessor O
O
–
–
–
– ——
–
FMAC (filter mathematical accelerator)
O
O
–
–
–
– ——
–
TSC (touch sensing controller)
O
O
–
–
–
– ——
–
RNG (true random number generator)
O
O
–
–
–
– ——
–
AES and secure AES O
O
–
–
–
– ——
–
PKA (public key accelerator)
O
O
–
–
–
– ——
–
OTFDEC (on-the-fly decryption)
O
O
–
–
–
– ——
–
HASH accelerator
O
O
–
–
–
– ——
–
CRC calculation unit
O
GPIOs
O
O
–
–
–
– ——
–
O
O
O
O
O
– 24 – 24 – 24 (18) pins (18) pins (19) pins
–
1. Y = yes (enabled). O = optional (disabled by default, can be enabled by
software). – = not available. Gray cells highlight the wakeup capability in
each mode.
2. The Flash memory can be configured in power-down mode. By default, it is
not in power-down mode.
3. The SRAMs can be powered on or off independently.
4. The SRAM clock can be gated on or off independently.
5. ECC error interrupt or NMI wakeup from Stop mode.
6. 8-Kbyte, 56-Kbyte or full SRAM2 content can be preserved.
7. Sub-blocks or full SRAM1 and SRAM3, full SRAM2 and SRAM4 can be powered-
off to save power consumption. SRAM1, SRAM2, SRAM3 and SRAM4 can be accessed
by GPDMA1 in Stop 0 and Stop 1 modes. SRAM4 can be accessed by LPDMA1 in Stop
0, Stop 1 and Stop 2 modes.
8. GPDMA transfers are functional and autonomous in Stop mode, and generates
a wakeup interrupt on transfer events.
9. LPDMA transfers are functional and autonomous in Stop mode, and generates
a wakeup interrupt on transfer events.
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Functional overview
STM32U585xx
10. Some peripherals with autonomous mode and wakeup from Stop capability can
request HSI16, MSIS or MSIK to be enabled. In this case, the oscillator is
woken up by the peripheral, and is automatically put off when no peripheral
needs it.
11. OTG_FS is functional in voltage scaling range 1, 2 and 3.
12. USART and LPUART reception and transmission are functional and autonomous
in Stop mode in asynchronous and in SPI master modes, and generate a wakeup
interrupt on transfer events.
13. I2C reception and transmission are functional and autonomous in Stop
mode, and generate a wakeup interrupt on transfer events.
14. SPI reception and transmission are functional and autonomous in Stop
mode, and generate a wakeup interrupt on transfer events.
15. A/D conversion is functional and autonomous in Stop mode, and generates a
wakeup interrupt on conversion events.
16. LPTIM is functional and autonomous in Stop mode, and generates a wakeup
interrupt on events.
17. MDF and ADF are functional and autonomous in Stop mode, and generate a
wakeup interrupt on events.
18. I/Os can be configured with internal pull-up, pull-down or floating in
Stop 3 and Standby modes.
19. I/Os can be configured with internal pull-up, pull-down or floating in
Shutdown mode but the configuration is lost when exiting the Shutdown mode.
3.9.3 3.9.4
Note:
3.9.5
Reset mode
In order to improve the consumption under reset, the I/O state under and after
reset is “analog state” (the I/O Schmitt trigger is disabled). In addition,
the internal reset pull-up is deactivated when the reset source is internal.
VBAT operation
The VBAT pin allows the device VBAT domain to be powered from an external
battery or an external super-capacitor.
The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup
registers and 2-Kbyte backup SRAM. Eight anti-tamper detection pins are
available in VBAT mode. The VBAT operation is automatically activated when VDD
is not present. An internal VBAT battery charging circuit is embedded and can
be activated when VDD is present. When the microcontroller is supplied from
VBAT, neither external interrupts nor RTC alarm/events exit the
microcontroller from the VBAT operation.
PWR TrustZone security
When the TrustZone security is activated by the TZEN option bit, the PWR is
switched in TrustZone security mode.
The PWR TrustZone security secures the following configuration: · low-power
mode · WKUP (wakeup) pins · voltage detection and monitoring · VBAT mode Some
of the PWR configuration bits security is defined by the security of other
peripherals: · The VOS (voltage scaling) configuration is secure when the
system clock selection is
secure in RCC. · The I/O pull-up/pull-down in Standby mode configuration is
secure when the
corresponding GPIO is secure.
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STM32U585xx
Functional overview
3.10
Peripheral interconnect matrix
Several peripherals have direct connections between them, that allow
autonomous communication between them and support the saving of CPU resources
(thus power supply consumption). In addition, these hardware connections allow
fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run,
Sleep, Low-power Run and Sleep, Stop 0, Stop 1 and Stop 2 modes.
3.11
Reset and clock controller (RCC)
The RCC (reset and clock control) manages the different reset types, and
generates all clocks for the bus and peripherals.
The RCC distributes the clocks coming from the different oscillators to the
core and to the peripherals. It also manages the clock gating for low-power
modes and ensures the clock robustness. It features:
· Clock prescaler: in order to get the best trade-off between speed and
current consumption, the clock frequency to the CPU and peripherals can be
adjusted by a programmable prescaler.
· Clock security system: clock sources can be changed safely on-the-fly in Run
mode through a configuration register.
· Clock management: in order to reduce the power consumption, the clock
controller can stop the clock to the core, individual peripherals or memory.
· System clock source: four different clock sources can be used to drive the
master clock SYSCLK:
HSE (4 to 50 MHz high-speed external crystal or ceramic resonator) that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
HSI16 (16 MHz high-speed internal RC oscillator) trimmable by software, that
can supply a PLL.
MSI (multispeed internal RC oscillator) trimmable by software, that can
generate 16 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source
is available in the system (LSE), the MSI frequency can be automatically
trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI
can feed the USB device, saving the need of an external high-speed crystal
(HSE). The MSI can supply a PLL.
System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency at
160 MHz.
· HSI48 (RC48 with clock recovery system) internal 48 MHz clock source that
can be used to drive the USB, the SDMMC or the RNG peripherals. This clock can
be output on the MCO.
· UCPD kernel clock, derived from HSI16 clock. The HSI16 RC oscillator must be
enabled prior to the UCPD kernel clock use.
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STM32U585xx
· Auxiliary clock source: two ultra-low-power clock sources that can be used
to drive the real-time clock:
LSE (32.768 kHz low-speed external crystal), supporting three drive
capability modes. The LSE can also be configured in bypass mode for an
external clock.
LSI (32 kHz low-speed internal RC), also used to drive the independent
watchdog. The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided
by 128 to output a 250 Hz as source clock.
· Peripheral clock sources: several peripherals have their own independent
clock whatever the system clock. Three PLLs, each having three independent
outputs allowing the highest flexibility, can generate independent clocks for
the ADC, USB, SDMMC, RNG, MDF, ADF, FDCAN1, OCTOSPIs and SAIs.
· Startup clock: after reset, the microcontroller restarts by default with
MSI. The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
· CSS (clock security system): this feature can be enabled by software. If a
HSE clock failure occurs, the master clock automatically switches to HSI16 and
a software interrupt is generated if enabled. LSE failure can also be detected
and generates an interrupt.
· Clock-out capability:
MCO (microcontroller clock output): it outputs one of the internal clocks
for external use by the application.
LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT mode).
Several prescalers allow AHB and APB frequencies configuration. The maximum
frequency of the AHB and the APB clock domains is 160 MHz.
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Functional overview
LSI RC LSCO 32 kHz or 250 Hz LSI
OSC32_OUT OSC32_IN
MCO
LSE OSC 32.768 kHz
Clock detector
/ 116
LSE
LSI MSIS HSI16 HSE SYSCLK
pll1_r_ck HSI48 MSIK
OSC_OUT OSC_IN
HSE OSC 4-50 MHz
Clock detector
HSE
HSI RC 16 MHz
HSI16
MSI RC MSIS 100 kHz 48 MHz
MSIK 100 kHz 48 MHz
MSIS MSIK
HSI48 RC 48 MHz
HSI48
PLL1 VCO
/ N
/ M / P pll1_p_ck / Q pll1_q_ck / R pll1_r_ck
PLL2 VCO
/ N
/ M / P pll2_p_ck / Q pll2_q_ck / R pll2_r_ck
PLL3 VCO
/ N
/ M / P pll3_p_ck / Q pll3_q_ck / R pll3_r_ck
SHSI RC
/ 2
AUDIOCLK
Figure 5. Clock tree
/32
MSIS HSI16 HSE MSIS HSI16 HSE MSIS HSI16 HSE
LSI LSE MSIK HSI16
To IWDG
HSI16
To UCPD1 To RTC
x2 To LPTIM1, LPTIM3, LPTIM4
Clock source control
SYSCLK
To AHB bus, core, memory and DMA
AHB PRESC / 1,2,..512
HCLK
FCLK Cortex free running clock
LSE LSI / 8
To Cortex system timer
APB1 PRESC / 1,2,4,8,16
LSE HSI16 SYSCLK
MSIK HSI16 SYSCLK
PCLK1 To APB1 peripherals
x1 or x2 To TIMx
(x = 2 to 7) x4
To USARTx (x = 2 to 5)
To SPI2
HSI16 SYSCLK
MSIK
x3
To I2Cx
(X = 1,2,4)
LSI LSE HSI16 HSE pll1_q_ck pll2_p_ck
To LPTIM2 To FDCAN1
SYSCLK MSIK
pll1_q_ck pll2_q_ck
APB2 PRESC / 1,2,4,8,16
CRS clock
PCLK2
To OCTOSPIx (X = 1,2)
To SAES
To APB2 peripherals
x1 or x2
To TIMx
(x = 1,8,15,16,17)
LSE HSI16 SYSCLK
To USART1
pll1_p_ck pll3_q_ck
MSIK
MSIK HSI16 SYSCLK x2
To SPI1 To ADF1 and MDF1
pll1_p_ck
MSIK HSI48 pll1_q_ck pll2_q_ck
ICLK HSI16
pll1_p_ck pll2_p_ck pll3_p_ck
HSI16
x2 To SAIx (X = 1,2)
To SDMMCx (X = 1,2)
48 MHz clock to OTG_FS / 2
To RNG
APB3 PRESC / 1,2,4,8,16
PCLK3 To APB3 peripherals
MSIK HSI16
To I2C3
MSIK HSI16
To SPI3
pll2_r_ck
HSE HSI16 MSIK
MSIK HSI16
LSE
LSI LSE
To LPUART1
To ADC1, ADC4 and DAC1 DAC1 sample and hold clock MSv63634V6
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STM32U585xx
3.11.1
RCC TrustZone security
When the TrustZone security is activated by the TZEN option bit, the RCC is
switched in TrustZone security mode.
The RCC TrustZone security secures some RCC system configuration and
peripheral configuration clock from being read or modified by non-secure
accesses: when a peripheral is secure, the related peripheral clock, reset,
clock source selection and clock enable during low-power modes control bits
are secure.
A peripheral is in secure state: · when its corresponding SEC security bit is
set in the TZSC (TrustZone security
controller), for securable peripherals. · when a security feature of this
peripheral is enabled through its dedicated bits, for
TrustZone-aware peripherals.
Clock recovery system (CRS)
The devices embed a special block that allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole
device operational range. This automatic t
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