FPGA-IPUG-02043-1.6 FIR Filter IP Core

Product Information:

Specifications:

The FIR Filter IP Core is designed for use with LatticeXP2,
LatticeECP3, and LatticeECP5 FPGA devices. It offers configurations
for different channels and taps, along with varying multipliers
based on the device type.

Product Usage Instructions:

1. Introduction:

The FIR Filter IP Core is a powerful tool for filtering signals
in FPGA applications. It provides Finite Impulse Response filtering
capabilities to enhance signal processing tasks.

2. Quick Facts:

LatticeXP2 Devices:

• 1 Channel 64 Taps, 16 Multipliers

• 1 Channel 24 Taps, 6 Multipliers

• 1 Channel 48 Taps, 12 Multipliers

• Minimal Device Needed: LFXP2-5E

• Resource Utilization: LUTs – 211, sysMEM – 4, EBRs – 250,
  Registers – 1

• Design Tool Support: Lattice Diamond 3.10, Synplify Pro
  F-2012.09L-SP1, Modelsim SE 10.2c, Active-HDL 8.2 Lattice
  Edition

LatticeECP3 Devices:

• 4 Channels 64 Taps, 1 Multiplier

• 1 Channel 32 Taps, 32 Multipliers

• 1 Channel 32 Taps, 8 Multipliers

• Minimal Device Needed: LFE3-35EA

• Resource Utilization: LUTs – 866, sysMEM – 32, EBRs – 2041,
  Registers – 64

• Design Tool Support: Lattice Diamond 3.10, Synplify Pro
  F-2012.09L-SP1, Modelsim SE 10.2c, Active-HDL 8.2 Lattice
  Edition

LatticeECP5 Devices:

• 4 Channels 64 Taps, 1 Multiplier

• 1 Channel 32 Taps, 32 Multipliers

• 1 Channel 32 Taps, 8 Multipliers

• Minimal Device Needed: LFE5UM-85FEA

• Resource Utilization: LUTs – 248, sysMEM – 202, EBRs – 201,
  Registers – 2

• Design Tool Support: Lattice Diamond 3.10

FAQ:

Q: What is the purpose of the FIR Filter IP Core?

A: The FIR Filter IP Core is designed to provide Finite Impulse
Response filtering capabilities for signal processing tasks in FPGA
applications.

Q: Which FPGA families are supported by the FIR Filter IP

Core?

A: The FIR Filter IP Core supports LatticeXP2, LatticeECP3, and
LatticeECP5 FPGA families.

Q: What design tools are compatible with the FIR Filter IP

Core?

A: The FIR Filter IP Core can be used with design tools such as
Lattice Diamond, Synplify Pro, Modelsim SE, and Active-HDL Lattice
Edition.

Q: What are the resource utilization requirements for the FIR

Filter IP Core on LatticeECP5 devices?

A: On LatticeECP5 devices, the resource utilization includes
LUTs – 248, sysMEM – 202, EBRs – 201, and Registers – 2.

FIR Filter IP Core
User Guide
FPGA-IPUG-02043-1.6
June 2021
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FIR Filter IP Core User Guide

Contents
Acronyms in This Document ……………………………………………………………………………………………………………………………….5

1. Introduction ………………………………………………………………………………………………………………………………………………6 2. Quick Facts………………………………………………………………………………………………………………………………………………..7 3. Features ……………………………………………………………………………………………………………………………………………………9 4. Functional Description………………………………………………………………………………………………………………………………10
   4.1. Interface Diagram…………………………………………………………………………………………………………………………….10 4.2. FIR Filter Architecture ………………………………………………………………………………………………………………………10
   4.2.1. Direct-form Implementation………………………………………………………………………………………………………….10 4.2.2. Symmetric Implementation …………………………………………………………………………………………………………..11 4.2.3. Polyphase Interpolation FIR Filter…………………………………………………………………………………………………..11 4.2.4. Polyphase Decimation FIR Filter …………………………………………………………………………………………………….12 4.2.5. Multi-channel FIR Filters ……………………………………………………………………………………………………………….12 4.3. Implementation Details…………………………………………………………………………………………………………………….12 4.4. Configuring the FIR Filter Core …………………………………………………………………………………………………………..13 4.4.1. Architecture Options…………………………………………………………………………………………………………………….13
   4.4.1.1. Coefficients Specification ………………………………………………………………………………………………………13 4.4.1.2. Multiplier Multiplexing Factor ……………………………………………………………………………………………….14 4.4.2. I/O Specification Options ………………………………………………………………………………………………………………15 4.4.2.1. Rounding …………………………………………………………………………………………………………………………….15 4.4.3. Implementation Options……………………………………………………………………………………………………………….15 4.4.3.1. Memory Type ………………………………………………………………………………………………………………………15 4.5. Signal Descriptions …………………………………………………………………………………………………………………………..16 4.6. Interfacing with the FIR Filter IP Core …………………………………………………………………………………………………17 4.6.1. Data interface ……………………………………………………………………………………………………………………………..17 4.6.2. Multiple Channels ………………………………………………………………………………………………………………………..17 4.6.3. Variable Interpolation/Decimation Factor……………………………………………………………………………………….17 4.6.4. Reloadable Coefficients ………………………………………………………………………………………………………………..17 4.7. Timing Specifications………………………………………………………………………………………………………………………..18 4.7.1. Timing Specifications Applicable to All Devices ………………………………………………………………………………..18 4.7.2. Timing Specifications Applicable to LatticeXP2, LatticeECP3 and LatticeECP5 Implementations …………….19 4.7.3. Timing Specifications Applicable to LatticeECP3 and LatticeECP5 Implementations ……………………………..20 5. Parameter Settings …………………………………………………………………………………………………………………………………..21 5.1. Architecture Tab………………………………………………………………………………………………………………………………22 5.2. I/O Specification Tab ………………………………………………………………………………………………………………………..24 5.3. Implementation Tab…………………………………………………………………………………………………………………………26 6. IP Core Generation and Evaluation……………………………………………………………………………………………………………..27 6.1. Licensing the IP Core ………………………………………………………………………………………………………………………..27 6.2. Getting Started ………………………………………………………………………………………………………………………………..27 6.3. IPexpress-Created Files and Top Level Directory Structure ……………………………………………………………………31 6.4. Instantiating the Core……………………………………………………………………………………………………………………….32 6.5. Running Functional Simulation ………………………………………………………………………………………………………….32 6.6. Synthesizing and Implementing the Core in a Top-Level Design …………………………………………………………….32 6.7. Hardware Evaluation ………………………………………………………………………………………………………………………..33 6.7.1. Enabling Hardware Evaluation in Diamond………………………………………………………………………………………33 6.8. Updating/Regeneratingthe IP Core…………………………………………………………………………………………………….33 6.8.1. Regenerating an IP Core in Diamond ………………………………………………………………………………………………33 6.9. Regenerating an IP Core in Clarity Designer Tool………………………………………………………………………………….34 6.10. Recreating an IP Core in Clarity Designer Tool ……………………………………………………………………………………..34 References ……………………………………………………………………………………………………………………………………………………..35 Technical Support Assistance ……………………………………………………………………………………………………………………………36 Appendix A. Resource Utilization ………………………………………………………………………………………………………………………37 LatticeECP3 Devices ……………………………………………………………………………………………………………………………………..37

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide
LatticeXP2 Devices……………………………………………………………………………………………………………………………………….37 ECP5 Devices……………………………………………………………………………………………………………………………………………….37 Revision History ………………………………………………………………………………………………………………………………………………38

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Figures
Figure 4.1. Top-Level Interface for the FIR Filter IP Core……………………………………………………………………………………….10 Figure 4.2. Direct-form FIR Filter ……………………………………………………………………………………………………………………….11 Figure 4.3. Symmetric Coefficients FIR Filter Implementation ……………………………………………………………………………….11 Figure 4.4. Polyphase Interpolator …………………………………………………………………………………………………………………….11 Figure 4.5. Polyphase Decimator ……………………………………………………………………………………………………………………….12 Figure 4.6. Functional Block Diagram …………………………………………………………………………………………………………………12 Figure 4.7. Tap and Coefficient Memory Management for a Sample FIR Filter ………………………………………………………..13 Figure 4.8. Single Channel, Single Rate FIR Filter with Continuous Inputs ……………………………………………………………….18 Figure 4.9. Single Channel, Single Rate FIR Filter with Gaps in Input ………………………………………………………………………18 Figure 4.10. Factorset Signals ……………………………………………………………………………………………………………………………18 Figure 4.11. Coefficient Reloading……………………………………………………………………………………………………………………..18 Figure 4.12. Multi- Channel Single Rate FIR Filter (3 Channels) ………………………………………………………………………………19 Figure 4.13. Multi-Channel (3 Channels) Interpolator (Factor of 3) ………………………………………………………………………..19 Figure 4.14. Multi-Channel (3 Channels) Decimator (Factor of 3) …………………………………………………………………………..19 Figure 4.15. Multi- Channel Single Rate FIR Filter (3 Channels) ………………………………………………………………………………20 Figure 4.16. Multi-Channel (3 Channels) Interpolator (Factor of 3) ………………………………………………………………………..20 Figure 4.17. Multi-Channel (3 Channels) Decimator (Factor of 3) …………………………………………………………………………..20 Figure 5.1. Architecture Tab of the FIR Filter IP Core Interface ………………………………………………………………………………22 Figure 5.2. I/O Specification Tab of the FIR Filter IP Core Interface ………………………………………………………………………..24 Figure 5.3. Implementation Tab of the FIR Filter IP Core Interface …………………………………………………………………………26 Figure 6.1. IPexpress Dialog Box ………………………………………………………………………………………………………………………..27 Figure 6.2. Configuration Dialog Box ………………………………………………………………………………………………………………….28 Figure 6.3. Clarity Designer Tool Dialog Box ………………………………………………………………………………………………………..28 Figure 6.4. Clarity Designer Catalog Tab ……………………………………………………………………………………………………………..29 Figure 6.5. Fir Filter Dialog Box ………………………………………………………………………………………………………………………….29 Figure 6.6. IP Configuration Interface…………………………………………………………………………………………………………………30 Figure 6.7. FIR Filter IP Core Generated Directory Structure………………………………………………………………………………….31
Tables
Table 2.1. FIR Filter IP Core for LatticeXP2 Devices Quick Facts ……………………………………………………………………………….7 Table 2.2. FIR Filter IP Core for LatticeECP3 Devices Quick Facts ……………………………………………………………………………..7 Table 2.3. FIR Filter IP Core for LatticeECP5 Devices Quick Facts ……………………………………………………………………………..8 Table 4.1. Maximum Multiplier Multiplexing Factor for Different Configurations…………………………………………………..15 Table 4.2. Top-Level Port Definitions………………………………………………………………………………………………………………….16 Table 5.1. Parameter Specifications for the FIR Filter IP Core ………………………………………………………………………………..21 Table 5.2. Architecture Tab……………………………………………………………………………………………………………………………….23 Table 5.3. I/O Specification Tab …………………………………………………………………………………………………………………………25 Table 5.4. Implementation Tab………………………………………………………………………………………………………………………….26 Table 6.1. File List ……………………………………………………………………………………………………………………………………………31 Table A.1. Performance and Resource Utilization (LatticeECP3) …………………………………………………………………………..37 Table A.2. Performance and Resource Utilization (LatticeXP2) …………………………………………………………………………….37 Table A.3. Performance and Resource Utilization (LFE5U) …………………………………………………………………………………..37

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Acronyms in This Document

A list of acronyms used in this document.

Acronym

Definition

FIR

Finite Impulse Response

FPGA

Field-Programmable Gate Array

LED

light-emitting diode

MLE

Machine Learning Engine

SDHC

Secure Digital High Capacity

SDXC

Secure Digital eXtended Capacity

SPI

Serial Peripheral Interface

VIP

Video Interface Platform

USB

Universal Serial Bus

NN

Neuro Network

FIR Filter IP Core User Guide

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide
1. Introduction
The Lattice FIR (Finite Impulse Response) Filter IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSPTM blocks available in Lattice devices. In addition to single rate filters, the IP core also supports a range of polyphase decimation and interpolation filters. The utilization versus throughput trade-off can be controlled by specifying the multiplier multiplexing factor used for implementing the filter. The FIR Filter IP core supports as high as 256 channels, with each having up to 2048 taps. The input data, coefficient and output data widths are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for saturation and rounding. The coefficients of the filter can be specified at generation time and/or reloadable during run-time through input ports. The FIR Filter IP core can also be generated using the Lattice FIR Filter Simulink® Model. For information on the Simulink flow, refer to the FPGA Design with ispLEVER tutorial.

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide

2. Quick Facts

Table 2.1 through Table 2.3 provide quick facts about the FIR Filter IP core for LatticeXP2TM, LatticeECP3TM, and LatticeECP5TM devices.

Table 2.1. FIR Filter IP Core for LatticeXP2 Devices Quick Facts

FIR IP Configuration

1 Channels 64 Taps
16 Multipliers

1 Channel 24 Taps 6 Multipliers

1 Channel 48 Taps 12 Multipliers

Core Requirements Resource Utilization
Design Tool Support

FPGA Families Supported Minimal Device Needed Targeted Device LUTs sysMEM EBRs Registers DSP Slice Lattice Implementation Synthesis Simulation

LFXP2-5E
211 4
250 1

LatticeXP2 LFXP2-40E LFXP2-40E-7F672C
241 4
272 1
Lattice Diamond 3.10 Synplify Pro F-2012.09L-SP1
Modelsim SE 10.2c Active-HDL 8.2 Lattice Edition

LFXP2-8E
246 4
281 1

Table 2.2. FIR Filter IP Core for LatticeECP3 Devices Quick Facts

Core Requirements Resource Utilization
Design Tool Support

FPGA Families Supported Minimal Device Needed Targeted Device LUTs sysMEM EBRs Registers MULT18X18 Lattice Implementation Synthesis Simulation

4 Channels 64 Taps
1 Multiplier
866 32 2041 64

FIR IP Configuration
1 Channel 32 Taps 32 Multipliers
LatticeECP3 LFE3-35EA LFE3-150EA-6FN672C
212 2
199 4
Lattice Diamond 3.10 Synplify Pro F-2012.09L-SP1
Modelsim SE 10.2c Active-HDL 8.2 Lattice Edition

1 Channel 32 Taps 8 Multipliers
200 4
303 6

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide

Table 2.3. FIR Filter IP Core for LatticeECP5 Devices Quick Facts

FIR IP Configuration

4 Channels 64 Taps
1 Multiplier

1 Channel 32 Taps 32 Multipliers

1 Channel 32 Taps 8 Multipliers

Core Requirements Resource Utilization
Design Tool Support

FPGA Families Supported Minimal Device Needed Targeted Device LUTs sysMEM EBRs Registers DSP Slice Lattice Implementation Synthesis Simulation

ECP5

LFE5UM-85FEA

LFE5UM-85FEA

LFE5UM-85FEA

LFE5U-85F-6BG756C

248

202

201

2

2

4

222

199

303

6

6

9

Lattice Diamond 3.10

Synplify Pro F-2012.09L-SP1

Aldec Active-HDL 10.3 Lattice Edition

ModelSim SE 10.2c

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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3. Features
· Variable number of taps up to 2048 · Input and coefficients widths of 4 to 32 bits · Multi-channel support for up to 256 channels · Decimation and Interpolation ratios from 2 to 256 · Support for half-band filter · Configurable parallelism from fully parallel to serial · Signed or unsigned data and coefficients · Coefficients symmetry and negative symmetry optimization · Re-loadable coefficients support · Full precision arithmetic · Selectable output width and precision · Selectable overflow: wrap-around or saturation · Selectable rounding: truncation, round towards zero, round away from zero, round to nearest and convergent
rounding · Width and precision specified using fixed point notations · Handshake signals to facilitate smooth interfacing

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide
4. Functional Description
This chapter provides a functional description of the FIR Filter IP core.
4.1. Interface Diagram
The top-level interface diagram for the FIR Filter IP core is shown in Figure 4.1.

Figure 4.1. Top-Level Interface for the FIR Filter IP Core
4.2. FIR Filter Architecture
FIR filter operation on data samples can be described as a sum-of-products operation. For an N-tap FIR filter, the current input sample and (N-1) previous input samples are multiplied by N filter coefficients and the resulting N products are added to give one output sample as shown below.
(1)
In the above equation, hn , n=0,1,…, N-1 is the impulse response; xn, n=0,1,…, is the input; and yn, n=0,1,…, is the
output. The number of delay elements (N-1) represents the order of the filter. The number of input data samples (current and previous) used in the calculation of one output sample represents the number of filter taps (N).
4.2.1. Direct-form Implementation
In the direct-form implementation shown in Figure 4.2, the input samples will be shifted into a shift register queue and each shift register is connected to a multiplier. The products from the multipliers are summed to get the FIR filter’s output sample.

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Figure 4.2. Direct-form FIR Filter
4.2.2. Symmetric Implementation
The impulse response for most FIR filters is symmetric. This symmetry can generally be exploited to reduce the arithmetic requirements and produce area- efficient filter realizations. It is possible to use only one half of the multipliers for symmetric coefficients compared to that used for a similar filter with non-symmetric coefficients. An implementation for symmetric coefficients is shown in Figure 4.3.

Figure 4.3. Symmetric Coefficients FIR Filter Implementation
4.2.3. Polyphase Interpolation FIR Filter
The polyphase interpolation filter option implements the computationally efficient 1-to-P interpolation filter shown below, where P is an integer greater than 1. Figure 4.4 shows a polyphase interpolator, where each branch is referred to as a polyphase.

Figure 4.4. Polyphase Interpolator

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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In this structure, the input data will be loaded into each polyphase at the same time and the output data of each polyphase will be unloaded as an output sample of the FIR. The number of polyphases is equal to the interpolation factor. The coefficients are assigned to all polyphases evenly.
4.2.4. Polyphase Decimation FIR Filter
The polyphase decimation filter option implements the computationally efficient P-to-1 decimation filter shown in Figure 4.5, where P is an integer greater than 1.

Figure 4.5. Polyphase Decimator
In this structure, the input sample is loaded sequentially into each of the polyphases with only one polyphase fed at a time. When all the polyphases are loaded with a sample, the result from the polyphases are summed and unloaded as the FIR filter’s output. In this scheme, P input samples generate one output sample, where P is the decimation factor.
4.2.5. Multi-channel FIR Filters
It is very common to see FIR filters used in multi-channel processing scenarios. The maximum possible throughput of a FIR filter implementation is often much higher than the throughput required for a single channel being processed. For such applications, it is desirable to use the same resources in a time multiplexed way to realize multi- channel FIR filters. Except in fully parallel implementations, where enough multipliers are used to perform all the necessary computations in one clock cycle, the FIR filter uses independent tap and coefficient memories to feed each multiplier. Hence, multi-channel implementations result in lower memory usage compared to multiple instantiations of FIR filters. For cases, where all the channels use the same coefficient set, using a multi-channel FIR filter has the clear advantage of requiring smaller coefficient memories.

4.3. Implementation Details
Figure 4.6 shows the functional block diagram of the FIR Filter IP core.

coeffin coeffwe coeffset

Coefficient Memory

din

Input Registers

Tap Memory

Symmetry Adder

Multiplier Array

Adder Tree

Output Processing

dout

inpvalid ibstart ifactor dfactor
factorset

Control Logic
Figure 4.6. Functional Block Diagram

outvalid obstart rfi

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide
The data and coefficients are stored in different memories shown as tap memory and coefficients memory in the above diagram. The symmetry adder is used if the coefficients are symmetric. The multiplier array contains one or more multipliers depending on the user specification. The adder tree performs the sum of products. Depending on the configuration, the adder tree, or a part of it, is implemented inside DSP blocks. The output processing block performs the output width reduction and precision control. This block contains logic to support different types of rounding and overflow. The block labeled Control Logic manages the scheduling of data and arithmetic operations based on the type of filter (interpolation, decimation or multi-channel) and multiplier multiplexing.
The tap and coefficient memories are managed differently for different configurations of the FIR filter. Figure 4.7 shows the memory assignments for a 16-tap, 3-channel, symmetric FIR filter with two multipliers.

Figure 4.7. Tap and Coefficient Memory Management for a Sample FIR Filter
In the diagram, there are two tap memories and a coefficient memory for each multiplier. The depth of each memory is ceil(taps/2/multiplier) *channel, which is 12 in this example, where the operator ceil(x) returns the next higher integer, if the argument x is fractional.

4.4. Configuring the FIR Filter Core
4.4.1. Architecture Options
The options for number of channels, number of taps, and filter type are independent and directly specified in the Architecture tab of the IP core interface (see Parameter Settings for details). If a polyphase decimator or interpolator is required, the decimation or interpolation factor can be directly specified in the interface. The decimation or interpolation factor can also be specified through input ports during operation by selecting the corresponding Variable option. If the Variable decimation (or Variable interpolation) factor option is selected, the decimation (or interpolation) factor can be varied from two to Decimation factor (or Interpolation factor) through the input port.
4.4.1.1. Coefficients Specification The coefficients of the filter are specified using a coefficients file. The coefficients file is a text file with one coefficient per line. If the coefficients are symmetric, the check box Symmetric Coefficients must be checked so the IP core uses symmetry adders to reduce the number of multipliers used. If the Symmetric Coefficients box is checked, only onehalf of the coefficients are read from the coefficient file. For an n-tap symmetric coefficients filter, the number of

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide
coefficients read from the coefficients file is equal to ceil(n/2). For multi- channel filters, the coefficients for channel 0 are specified first, followed by those for channel 1, and so on. For multi-channel filters, there is an option to specify whether the coefficients are different for each channel or the same (common) for all the channels. If the coefficients are common, only one set of coefficients needs to be specified in the coefficients file. The coefficient values in the file can be in any radix (decimal, hexadecimal or binary) selected by the user. A unary negative operator is used only if the coefficients are specified in decimal radix. For hexadecimal and binary radices, the numbers must be represented in twos complement form. An example coefficients file in decimal format for an 11tap, 16-bit coefficients set is given below. In this example, the coefficients binary point is 0. -556 -706 -857 -419 1424 5309 11275 18547 25649 30848 32758 An example coefficients file in floating point format for the above case when the Coefficients binary point position is 8, is given below. The coefficients will be quantized to conform to the 16.8 fractional data in which 16 is the full width of coefficients, and 8 is the width of fractional part. -2.1719 -2.7578 -3.3477 -1.6367 5.5625 20.7383 44.043 72.45 100.0191 120.5 127.96 If the check box Reloadable Coefficients is checked, the coefficients can be reloaded to the FIR filter during the operation of the core. With this option, the desired coefficients must be loaded before the operation of the filter. The coefficients must be loaded in a specific order that is determined by the program supplied with the IP core. The IP core can also optionally do the reordering internally, albeit using more resources. If this option is desired, the check box Reorder Coefficients Inside can be checked. With this option, the coefficients can be loaded in the normal sequential order to the core.
4.4.1.2. Multiplier Multiplexing Factor The throughput and the resource utilization can be controlled by assigning a proper value to the Multiplier Multiplexing Factor parameter. Full parallel operation (one output data per clock cycle) can be achieved by setting the Multiplier Multiplexing Factor to

1. If the Multiplier Multiplexing Factor is set to the maximum value displayed in the interface, full series operation is supported and it takes up to n clocks to compute one output data sample, where n is the number of taps for a non-symmetric FIR filter and half the number of taps for a symmetric FIR filter. The maximum value of the Multiplier Multiplexing Factor for different configurations of an n-tap FIR filter is given in Table 4.1.

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Table 4.1. Maximum Multiplier Multiplexing Factor for Different Configurations*

FIR Type Non-symmetric Symmetric Half-band

Single Rate n Ceil(n/2) floor((n+1)/4)+1

Interpolator with Factor=i Ceil(n/i) Ceil(n/2i) floor((n+1)/4)

*Note: The operator floor (x) returns the next lower integer, if x is a fractional value.

Decimator with Factor Ceil(n/d) Ceil(n/2d) floor((n+1)/8)+1

4.4.2. I/O Specification Options
The controls in the I/O Specifications interface tab are used to define the various widths and precision methods in the data path. The width and binary point positions of the input data and coefficients can be defined independently. From the input data width, coefficient width and the number of taps, the full precision output width and true location of the output binary point automatically get fixed. The full precision output is converted to user specified output width by dropping some least significant (LS) and some most significant (MS) bits and by performing the specified rounding and overflow processing. The output is specified by the output width and the output binary point position parameter.
4.4.2.1. Rounding
The following five options are supported for rounding: · None ­ Discards all bits to the right of the output least significant bit and leaves the output uncorrected. · Rounding up ­ Rounds to nearest more positive number. · Rounding away from zero ­ Rounds away from zero if the fractional part is exactly one-half. · Rounding towards zero ­ Rounds towards zero if the fractional part is exactly one-half. · Convergent rounding ­ Rounds to the nearest even value if the fractional part is exactly one-half.

4.4.3. Implementation Options
4.4.3.1. Memory Type
The FIR Filter IP core uses memories for storing delay tap data, coefficients and for some configurations, input or output data. The number of memory units used depends on several parameters including data width, number of taps, filter type, number of channels and coefficient symmetry. In most cases, each multiplier requires one data memory unit and one coefficient memory unit. Interpolation or decimation filters may additionally use input or output buffers. The memory type interface option can be used to specify whether EBR or distributed memory is used for data, coefficient, input and output storage. The option called Auto leaves that choice to the IP generator tool, which uses EBR if the memory is deeper than 128 locations and distributed memory otherwise.

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4.5. Signal Descriptions
A description of the Input/Output (I/O) ports for the FIR Filter IP core is provided in Table 4.2.

Table 4.2. Top-Level Port Definitions

Port

Bits

General I/O

clk

1

rstn

1

din

Input data width

inpvalid

1

dout outvalid
rfi

Output width 1
1

When Reloadable coefficients is selected

coeffin

Notes 1*

coeffwe

1

I/O

Description

I

System clock for data and control inputs and outputs.

I

System wide asynchronous active-low reset signal.

I

Input data.

I

Input valid signal. The input data is read-in only when

inpvalid is high.

O

Output data.

O

Output data qualifier. Output data dout is valid only when

this signal is high.

O

Ready for input. This output, when high, indicates that the IP

core is ready to receive the next input data. A valid data may

be applied at din only if rfi was high during the previous clock

cycle.

I

Coefficients input. The coefficients have to be loaded

through this port in a specific order. Refer to the section

Interfacing with the FIR Filter IP core for details.

I

When asserted, the value on bus coeffin will be written into

coefficient memories.

coeffset

1

I

This input is used to signal the filter to use the recently

loaded coefficient set. This signal must be pulsed high for

one clock cycle after the loading the entire coefficient set

using coeffin and coeffwe.

When Number of channels is greater than 1

ibstart

1

I

Input block start. For multi-channel configurations, this input

identifies channel 0 of the input.

obstart

1

O

Output block start. For multi-channel configurations, this

output identifies channel 0.

When Variable interpolation factor or Variable decimation factor is checked

ifactor

ceil(Log2(Interpolation

I

Interpolation factor value

factor+1))

dfactor

ceil(Log2(Decimation factor+1))

I

Decimation factor value

factorset

1

I

Sets the interpolation factor or the decimation factor.

Optional I/Os

ce

1

I

Clock Enable. While this signal is de-asserted, the core will

ignore all other synchronous inputs and maintain its current

state

sr

1

I

Synchronous Reset. When asserted for at least one clock

cycle, all the registers in the IP core are initialized to reset

state.

Notes: 1. Width for signed type and symmetric interpolation is Coefficients width +1. 2. Width for unsigned and symmetric interpolation is Coefficients width +2. 3. Width for all other cases is Coefficients width.

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4.6. Interfacing with the FIR Filter IP Core
4.6.1. Data interface
Data is fed into the core through din and out from the core through dout.

4.6.2. Multiple Channels
For multi-channel implementations, two ports, ibstart and obstart, are available in the IP core to synchronize the channel numbers. The input ibstart is used to identify channel 0 data applied at the inputs. The output obstart goes high simultaneously with channel 0 output data.

4.6.3. Variable Interpolation/Decimation Factor
When the interpolation (or decimation) factor is variable, the ports ifactor (or dfactor) and factorset are added to the IP core. The interpolation (or decimation) factor applied on the port ifactor (or dfactor) is set when the strobe signal factorset is high. When the interpolation (or decimation) factor changes, the output rfi goes low for a few cycles. When it becomes high again, the filter performs as an interpolating (or decimating) filter corresponding to the new factor value.

4.6.4. Reloadable Coefficients
When Reloadable Coefficients is selected, the two added ports, coeffin and coeffwe, are used to reload the coefficients. All the coefficients need to be loaded in one batch, while keeping the signal coeffwe high during the entire duration of loading. After all the coefficients are loaded, the input signal coeffset must be pulsed high for one clock cycle for the new coefficients to take effect.
There are two ways in which coefficients can be applied for reloading the coefficients memory, as specified by the Reorder Coefficients Inside parameter.
When Reorder Coefficients Inside is not selected, the coefficients have to be applied in a particular sequence for reloading the coefficients memory. The raw coefficients, as specified in the coefficients file, can be converted to the reloadable sequence by using the coefficients generation program coeff_gen.exe (for Windows) available under the gui folder in the IP installation directory (for example, under the C:LatticeCorefir_core_v6.0gui folder). The names of the coefficient generation program for UNIX and Linux are coeff_gen_s and coeff_gen_l respectively. For Windows, the program is invoked as follows:
coeff_gen.exe .lpc
Note: If in lpc file, the value of parameter varcoeff= is Yes, please change it to No before generating ROM files manually.
This command converts the coefficients in the input file, as referred by the coefffile= parameter in the lpc file, to the loadable coefficients sequence file called coeff.mem. Note that the output file may contain more coefficients than there originally were due to inserted zero coefficients. All the coefficients in the output file, including the zeros, have to be applied sequentially through the coeffin port. To obtain the sequence of application of coefficients, edit the input coefficients file with sequential numbers (e.g. 1,2) and the IP will run the file automatically. In the reloadable coefficients mode, the core will not be ready for operation (the rfi output will not be high) until the coefficients are loaded and coeffset is asserted high.
When the parameter Reorder Coefficients Inside is selected, the coefficients will be reordered inside the IP core without requiring manual reordering described previously. With this option, reordering logic is added to the IP core and the user can apply the coefficients in the normal sequence.
In this mode, if the parameter Symmetric Coefficients is selected, only half of the coefficients provided will be used. For example, if the raw coefficient input sequence is: 1 2 3 4 5 6 5 4 3 2 1, the coefficients that will be used will be 1 2 3 4 5 6.
Similarly, if Half Band is selected, all of the input coefficients in the even locations, except the last one, will be discarded. For example, if the raw coefficient input sequence is: 1 0 2 0 3 0 4 0 5 6 5 0 4 0 3 0 2 0 1, the coefficients that will be used will be 1 2 3 4 5 6.
Note: If the parameter varcoeff= in the lpc file is set to Yes, change it to No before generating the new coefficients file.

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4.7. Timing Specifications
Timing diagrams for the FIR Filter IP core are given in Figure 4.8 through Figure 4.17. Note that there are different timing specifications for certain FIR filter applications using Lattice XP2/ECP3/ECP5 devices. Figure 4.8 through Figure 4.11 apply to all FIR applications.
4.7.1. Timing Specifications Applicable to All Devices
Figure 4.8. Single Channel, Single Rate FIR Filter with Continuous Inputs

Figure 4.9. Single Channel, Single Rate FIR Filter with Gaps in Input Figure 4.10. Factorset Signals
Figure 4.11. Coefficient Reloading

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4.7.2. Timing Specifications Applicable to LatticeXP2, LatticeECP3 and LatticeECP5 Implementations
In addition to the previous figures, Figure 4.12 through Figure 4.14 apply in using both LatticeXP2, LatticeECP3, and LatticeECP5 devices: negative symmetry, half band, factor variable interpolation and decimation, and applications using 36×36 multipliers.
Figure 4.12. Multi-Channel Single Rate FIR Filter (3 Channels)

Figure 4.13. Multi-Channel (3 Channels) Interpolator (Factor of 3)

Figure 4.14. Multi-Channel (3 Channels) Decimator (Factor of 3)

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4.7.3. Timing Specifications Applicable to LatticeECP3 and LatticeECP5 Implementations
As indicated previously, Figure 4.15 through Figure 4.17 apply to all LatticeECP3 and Lattice ECP5 devices other than those specifically listed in the previous section.

Figure 4.15. Multi-Channel Single Rate FIR Filter (3 Channels)

Figure 4.16. Multi-Channel (3 Channels) Interpolator (Factor of 3)

Figure 4.17. Multi-Channel (3 Channels) Decimator (Factor of 3)

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5. Parameter Settings

The IPexpress and Clarity Designer tools are used to create IP and architectural modules in the Diamond software. You may refer to the IP Core Generation and Evaluation section on how to generate the IP.
Table 5.1 provides the list of user configurable parameters for the FIR Filter IP core. The parameter settings are specified using the FIR Filter IP core Configuration interface in IPexpress or Clarity Designer. The numerous FIR Filter IP core parameter options are partitioned across multiple interface tabs as described in this chapter.

Table 5.1. Parameter Specifications for the FIR Filter IP Core

Parameter

Range

Filter Specifications

Number of channels

1 to 256

Number of taps

1 to 2048

Filter type

{Single rate, Interpolator, Decimator}

Interpolation factor

2 to 256

Variable interpolation factor

{Yes, No}

Decimation factor

2 to 256

Variable decimation factor

{Yes, No}

Coefficients Specifications

Reloadable coefficients

{Yes, No}

Reorder coefficients inside

{Yes, No}

coefficients set

{Common, One per channel}

Symmetric coefficients

{Yes, No}

Negative symmetry

{Yes, No}

Half band

{Yes, No}

Coefficient radix

{Floating point, Decimal, Hex, Binary}

Coefficients file

Type or Browse

Advanced Options

Multiplier Multiplexing factor

Note 1, Note 2

Number of SysDSP blocks in a row

5 – Note 3

I/O Specifications

Input data type

{Signed, Unsigned}

Input data width

4 to 32

Input data binary point position

-2 to Input data width + 2

Coefficients type

{Signed, Unsigned}

Coefficients width

4 to 32

Coefficients binary point position

-2 to Coefficients width + 2

Output width

4 to Max Output Width

Output binary point position

(4+Input data binary point position + coefficient binary point position ­ Max output width) to (Output width + Input data binary
point position + Coefficient binary point position – 4)

Precision control

Overflow Rounding

{Saturation, Wrap-around}
{None, Round-up, Round away from zero, Round towards zero, Convergent rounding}

Default
4 64 Single rate 2 No 2 No
Yes No Common No No No Decimal –
Note 2 Note 3
Signed 16 0
Signed 16 0 38 0
Saturation None

Memory Type Data memory type Coefficient memory type Input buffer type

{EBR, Distributed, Auto}

EBR

{EBR, Distributed, Auto}

EBR

{EBR, Distributed, Auto}

EBR

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Parameter

Range

Default

Output buffer type

{EBR, Distributed, Auto}

EBR

Optimization

{Area, Speed}

{Area}

Optional Ports

ce

{Yes, No}

No

sr

{Yes, No}

No

Synthesis Options

Frequency constraint

1 ­ 400

300

Notes:

1. The Multiplier Multiplexing Factor is limited by the number of DSP blocks in a device (A) and the actual number of DSP blocks a

design needs (B). When A>B, the Multiplier Multiplexing Factor is set to 1; otherwise the value will be greater than 1.

2. See Multiplier Multiplexing Factor for details. 3. Maximum number of DSP blocks available in a row in the selected device.

The default values shown in the following pages are those used for the FIR Filter reference design. IP core options for each tab are discussed in further detail.

5.1. Architecture Tab
Figure 5.1 shows the contents of the Architecture tab.

Figure 5.1. Architecture Tab of the FIR Filter IP Core Interface

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Table 5.2. Architecture Tab Interface Item
Number of Channels Number of Taps Filter Type Interpolation Factor Variable Interpolation Factor Decimation Factor Variable Decimation Factor Reloadable Coefficients Reorder Coefficients Inside
Coefficients set Symmetric Coefficients
Negative Symmetry Half Band
Coefficient Radix

FIR Filter IP Core User Guide
Description
This option allows the user to specify the number of channels.
This option allows the user to specify the number of taps.
This option allows the user to specify whether the filter is single rate, interpolator, or decimator.
This option allows the user to specify the value of the fixed interpolation factor. When FIR type is interpolation, the value should be 2 to 256. Otherwise, it will be set to 1 automatically.
This option allows the user to specify whether the interpolation factor is fixed at the time of IP generation, or variable during run-time. If this is checked, the interpolation factor is set through the input port ifactor when factorset is high. This option allows the user to specify the value of the fixed decimation factor. When FIR type is decimation, the value should be 2 to 256. Otherwise, it will be set to 1 automatically.
This option allows the user to specify whether the decimation factor is fixed at the time of IP generation or variable during run-time. If this is checked, the decimation factor is set through the input port dfactor when factorset is high. This option allows the user to specify whether the coefficients are fixed or reloadable. If checked, the coefficients can be reloaded during core operation using the input port coeffin.
When coefficients are reloadable, they need to be entered in a particular order. The reordering can be done using the program supplied along with the IP core. However, the core also provides for optional hardware reordering at the expense of additional hardware resources. If this option is selected, the coefficients can be entered in the normal sequence to the core, and the core will internally reorder hem as required. This option is not available when Filter type is interpolator, and Symmetric coefficients is enabled.
This option allows the user to specify whether the same coefficient set is used for all channels, or an independent coefficient set is used for each channel.
This option allows the user to specify whether the coefficients are symmetric. If this is checked, only one half of the number of coefficients (if number of taps is odd, the half value is rounded to the next higher integer) is read from the initialization file.
If this is checked, the coefficients are considered to be negative symmetric. That is the second half of the coefficients are made equal to the negative of the corresponding first-half coefficients.
This option allows the user to specify whether a half band filter is realized. If this is checked, only one half of the number of coefficients (if the number of taps is odd, the half value is rounded to the next higher integer) is read from the initialization file.
This option allows the user to specify the radix for the coefficients in the coefficients file. For decimal radix, the negative values have a preceding unary minus sign. For hexadecimal (Hex) and binary radices, the negative values must be written in 2’s complement form using exactly as many digits as specified by the coefficients width parameter. The floating point coefficients are specified in the form <nn…n>.<dd…d>, where the digits ‘n’ denote the integer part and the digits ‘d’, the decimal part. The values of the floating point coefficients must be consistent with the Coefficients width and Coefficients binary point position parameters. For example, if <nn…n>.<dd…d> is 8.4 and Coefficients type is unsigned, the value of the coefficients should be between 0 and 11111111.1111 (255.9375).

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Interface Item Coefficients File
Multiplier Multiplexing Factor
Number of sysDSP Blocks in a Row

Description
This option allows the user to specify the name and location of the coefficients file. If the coefficients file is not specified, the filter is initialized with a default coefficient set.
This option allows the user to specify the Multiplier Multiplexing Factor. This parameter should be set to 1 for full parallel applications and to the maximum value supported in the interface for full series applications.
This parameter allows the user to specify the maximum number of DSP multipliers to be use in a DSP row to achieve optimal performance. For example, if the targeted device has 20 multipliers in a DSP row and the design requires 22 multipliers, the user can select to use all 20 multipliers in one row and two multipliers in another row, or fewer than 20 multipliers in each row (e.g. 8), which may yield better performance. Multipliers spread across a maximum of three DSP rows may be used in a single FIR instance. This parameter is only valid on LatticeECP3 and ECP5 devices.

5.2. I/O Specification Tab
Figure 5.2 shows the contents of the I/O Specification tab.

Figure 5.2. I/O Specification Tab of the FIR Filter IP Core Interface

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Table 5.3. I/O Specification Tab Interface Item
Input Data Type Input Data Width Input Data Binary Point Position Coefficients Type Coefficients Width Coefficients Binary Point Position Output Width
Output Binary Points
Overflow
Rounding

FIR Filter IP Core User Guide
Description
This option allows the user to specify the input data type as signed or unsigned. This option allows the user to specify input data twwiod’tsh.complement number.
This option allows the user to specify the location of the binary point in the input data. This number specifies the bit position of the binary point from the LSB of the input data. If the number is zero, the point is right after LSB, if positive, it is to the left of LSB and if negative, it is to the right of LSB.
This option allows the user to specify the coefficients type as signed or unsigned. If the type is signed, the coefficient data is interpreted as a 2’s complement number. This option allows the user to specify the coefficients width. This option allows the user to specify the location of the binary point in the coefficients. This number specifies the bit position of the binary point from the LSB of the coefficients. If the number is zero, the point is right after LSB; if positive, it is to the left of LSB and if negative, it is to the right of LSB.
This option allows the user to specify the output data width. The maximum full precision output width is defined by Max Output Width = Input data width + Coefficients width +ceil (Log2(Number of taps/Interpolation factor)). The core’s output is usually a part of the full precision output equal to the Output width and extracted based on the different binary point position parameters. The format for the internal full precision output is displayed as static text next to the Output width control in the interface. The format is displayed as W.F, where W is the full precision output width and F is the location of the binary point from the LSB of the full precision output, counted to the left. For example, if W.F is 16.4, then the output value will be yyyyyyyyyyyy.yyyy in binary radix.For example, 110010010010.0101.
This option allows the user to specify the bit position of the binary point from the LSB of the actual core output. If the number is zero, the point is right after LSB, if positive, it is to the left of LSB and if negative, it is to the right of LSB. This number, together with the parameter Output width, determines how the actual core output is extracted from the true full precision output. The precision control parameters Overflow and Rounding are applied respectively when MSBs and LSBs are discarded from the true full precision output.
This option allows the user to specify what kind of overflow control is to be used. This parameter is available when- ever there is a need to drop some of the MSBs from the true output. If the selection is Saturation, the output value is clipped to the maximum, if positive or minimum, if negative, while discarding the MSBs. If the selection is Wrap- around, the MSBs are simply discarded without making any correction.
This option allows the user to specify the rounding method when there is a need to drop one or more LSBs from the true output.

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5.3. Implementation Tab
Figure 5.3 shows the contents of the Implementation tab.

Figure 5.3. Implementation Tab of the FIR Filter IP Core Interface

Table 5.4. Implementation Tab Interface Item
Data Memory Type
Coefficient Memory Type
Input Buffer Type Output Buffer Type Synchronous Reset (sr) Clock Enable (ce)
Optimization Synthesis Options

Description
This option allows the user to specify select the type of memory that is used for storing the data. If the selection is EBR, Lattice Embedded Block RAM memories are used for storing the data. If the selection is Distributed, look- up-table based distributed memories are used for storing data. If “Auto” is selected, EBR memories are used for memory sizes deeper than 128 locations and distributed memories are used for all other memories. If the type is signed, the data is interpreted as a two’s complement number.
This option allows the user to specify the type of memory that is used for storing the coefficients. If the selection is EBR, EBR memories are used for storing the coefficients. If the selection is Distributed, distributed memories are used for storing coefficients. If Auto is selected, EBR memories are used for memory sizes deeper than 128 locations and distributed memories are used for all other memories.
This option allows the user to specify the memory type for the input buffer. This option allows the user to specify the memory type for the output buffer.
This option allows the user to specify if a synchronous reset port is needed in the IP. Synchronous reset signal resets all the registers in the FIR filter IP core.
This option allows the user to specify if a clock enable port is needed in the IP. Clock enable control can be used for power saving when the core is not being used. Use of clock enable port increases the resource utilization and may affect the performance due to the increased routing congestion.
This option specifies the optimization method. If Area is selected, the core is optimized for lower resource utilization. If Speed is selected, the core is optimized for higher performance, but with slightly higher resource utilization.
Lattice LSE or Synplify Pro

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6. IP Core Generation and Evaluation
This chapter provides information on how to generate the Lattice FIR Filter IP core using the ispLEVER software IPexpress tool included in the Diamond or ispLEVER software, and how to include the core in a top-level design.
6.1. Licensing the IP Core
An IP core- and device-specific license is required to enable full, unrestricted use of the FIR Filter IP core in a complete, top-level design. Instructions on how to obtain licenses for Lattice IP cores are given at: http://www.latticesemi.com/products/intellectualproperty/aboutip/isplevercoreonlinepurchas.cfm Users may download and generate the FIR Filter IP core and fully evaluate the core through functional simulation and implementation (synthesis, map, place and route) without an IP license. The FIR Filter IP core also supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited time (approximately four hours) without requiring an IP license. See for further details. However, a license is required to enable timing simulation, to open the design in the Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hardware evaluation timeout limitation.
6.2. Getting Started
The FIR Filter IP core is available for download from Lattice’s IP server using the IPexpress or the Clarity Designer tool. The IP files are automatically installed using ispUPDATE technology in any customer-specified directory. After the IP core has been installed, the IP core will be available in the IPexpress Interface or the Clarity Designer tool. The IPexpress tool interface dialog box for the FIR Filter IP core is shown in Figure 6.1. To generate a specific IP core configuration, the user specifies: · Project Path ­ Path to the directory where the generated IP files will be located. · File Name ­ Username designation given to the generated IP core and corresponding folders and files. · (Diamond) Module Output ­ Verilog or VHDL. · Device Family ­ Device family to which IP is to be targeted (such as LatticeXP2, LatticeECP3, and others). Only
families that support the particular IP core are listed. · Part Name ­ Specific targeted part within the selected device family.

Figure 6.1. IPexpress Dialog Box

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Note that if the IPexpress tool is called from within an existing project, Project Path, Module Output, Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool online help for further information. To create a custom configuration, the user clicks the Customize button in the IPexpress tool dialog box to display the FIR Filter IP core Configuration interface, as shown in Figure 6.2. From this dialog box, the user can select the IP parameter options specific to their application. Refer to Parameter Settings for more information on the FIR Filer IP core parameter settings.

Figure 6.2. Configuration Dialog Box
The Clarity Designer tool interface dialog box for the FIR Filter IP core is shown in Figure 6.3. · Create new Clarity design ­ Choose to create a new Clarity Design project directory in which the FIR IP core will be
generated. · Design Location ­ Clarity Design project directory Path. · Design Name ­ Clarity Design project name. · HDL Output ­ Hardware Description Language Output Format (Verilog or VHDL). · Open Clarity design ­ Open an existing Clarity Design project. · Design File ­ Name of existing Clarity Design project file with .sbx extension.

Figure 6.3. Clarity Designer Tool Dialog Box

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The Clarity Designer Catalog tab is shown in Figure 6.4. To generate FIR IP core configuration, double-click the IP name in the Catalog tab.

Figure 6.4. Clarity Designer Catalog Tab
In the Fir Filter dialog box shown in Figure 6.5, specify the following: · Instance Name ­ The instance module name of FIR IP core.

Figure 6.5. Fir Filter Dialog Box
Note that if the Clarity Designer tool is called from within an existing project, Design Location, Device Family, and Part Name default to the specified project parameters. Refer to the Clarity Designer tool online help for further information. To create a custom configuration, click the Customize button in the Clarity Designer tool dialog box to display the FIR IP core Configuration interface, as shown in Figure 6.6. From this dialog box, the user can select the IP parameter options specific to their application. Refer to Parameter Settings for more information on the FIR parameter settings.

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide

Figure 6.6. IP Configuration Interface

© 2008-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FIR Filter IP Core User Guide
6.3. IPexpress-Created Files and Top Level Directory Structure
When the user clicks the Generate button, the IP core and supporting files are generated in the specified Project Path directory. The directory structure of the generated files is shown in Figure 6.7.

Figure 6.7. FIR Filter IP Core Generated Directory Structure

The design flow for IP created with the IPexpress tool uses a post-synthesized module (NGO) for synthesis and a protected model for simulation. The post- synthesized module is customized and created during the IPexpress tool generation.
Table 6.1 provides a list of key files created by the IPexpress tool. The names of most of the created files are customized to the user’s module name specified in the IPexpress tool. The files shown in Table 6.1 are all of the files necessary to implement and verify the FIR Filter IP core in a top-level design.

Table 6.1. File List File

Description