multiLane AT93000-1900002 Family Board with DUT Loadboard Development User Manual
- June 3, 2024
- multiLane
Table of Contents
USER MANUAL
AT93000-1900002 User Manual
Family Board Overview to help with DUT Loadboard Development
User Manual Revision 0.4, April 2022
AT93000-1900002 Family Board with DUT Loadboard Development
Notices
Copyright © MultiLane Inc. All rights reserved. Licensed software products
are owned by MultiLane Inc. or its suppliers and are protected by United
States copyright laws and international treaty provisions.
Use, duplication, or disclosure by the Government is subject to restrictions
as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and
Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and
(2) of the Commercial Computer Software — Restricted Rights clause at FAR
52.227-19, as applicable.
MultiLane Inc. products are covered by U.S. and foreign patents, issued and
pending. Information in this publication supersedes that in all previously
published material. Specifications and price change privileges reserved.
General Safety Summary
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use
this product only as specified. Only qualified personnel should perform
service procedures. While using this product, you may need to access other
parts of the system. Read the General Safety Summary in other system manuals
for warnings and cautions related to operating the system.
To Avoid Fire or Personal Injury
Use Proper Power Cord. Only use the power cord specified for this product and
certified for the country of use.
Observe All Terminal Ratings. To avoid fire or shock hazard, observe all
ratings and markings on the product. Consult the product manual for further
ratings information before making connections to the product. Do not apply a
potential to any terminal, including the common terminal that exceeds the
maximum rating of that terminal
Do Not Operate Without Covers.
Do not operate this product with covers or panels removed.
Avoid Exposed Circuitry.
Do not touch exposed connections and components when power is present.
Do Not Operate with Suspected Failures.
If you suspect there is damage to this product, have it inspected by qualified
service personnel.
Do Not Operate in Wet/Damp Conditions. Do Not Operate in an Explosive Atmosphere. Keep Product Surfaces Clean and Dry
Caution statements identify conditions or practices that could result in damage to this product or other property.
Purpose of this User Manual
A “device under test” (DUT) loadboard will be designed by the test engineer
either a package test loadboard or a wafer test loadboard. Since the tester
resources come up through the twinning frame via the Family Board, this
AT93000-1900002 Family Board User Manual can be used to determine the pin
assignments for the DUT PCB Loadboard.
The following is provided to help design a DUT PCB loadboard for the AT93000 twinning frame:
- A mechanical outline and DXF files with V93K resource landing pad coordinate locations on the PCB: Visit the Advantest TDC at AT93000 Package and Probe PCB information
- A detailed pin list Excel file for the AT93000-1900002 family board is located on the MultiLane public website at AT93000-1900002
- This AT93000-1900002 Family Board User Guide: An overview of pin mapping from V93K tester resources, through the Family Board, through the Advantest Pogo Blocks, and ultimately to the DUT PCB loadboard landing pads.
Overview of the Advantest V93000 High Speed I/O (HSIO) Test System
In Figure 1, the AT93000 twinning system is hard docked on top of a V93000 (V93K) test head. The AT93000 is compatible with CTH and STH Advantest V93K testheads. In the case of package test, the user’s DUT loadboard is hard docked on top of the AT93000 system and the device handler is hard docked on top of the DUT loadboard. For wafer probe, the AT93000 system would be upside down from this picture and would be hard docked to the wafer prober at the bottom of this picture. Figure 1 shows the AT93000 twinning frame with the green-colored Family Board and one Pogo Segment. The DUT loadboard is not shown in this picture. Note: “Top View” references in this manual are defined by Figure 1.
Overview of the Family Board
An exploded view of the AT93000 twinning frame assembly is shown in Figure 2.
The family board is the bottom green PCB of Figure 2.
The Family board’s function is to deliver the Advantest V93K testhead resources through the HSIO Card Cage, via the pogo block groups 1A through 8B, up to the DUT loadboard. The 16 HSIO card cage cavities around the perimeter of the AT93000 system are labeled in Figure 3. Any number of these 16 cavities will be populated with a Pogo Block.
Figure 4: Pogo Block loads into 1 of 16 groups. Ordered through Advantest. P/N E8028PSD
V93K mapped resources delivered through the AT93000-1900002 are as follows
- 11x PS1600 (1408 pins)
- 3x PS9G (192 pins)
- 4x DPS64 (256 supplies)
- 2x DPS128 (256 supplies)
- 2x UHC4 (8 supplies @ 40A)
- 1x MBAV8
Find additional tester resource information on page 8.
Referring to Figure 3, Groups 7B,7A,8B,8A,2B,2A,6B,6A are referred to here as
the “top-row” (top view). Groups 4A,4B,3A,3B,1A,1B,5A,5B are referred to here
as the “bottom-row” (top view).
Referring to Figure 3, the [top view] pin coordinates for bottom-row and top-
row pogo blocks are shown in Figure 5.
Note: Top-Row and Bottom-Row signal pin coordinates are rotated 180
degrees with respect to each other.
Note: The extra detail shown in Figure 6 and Figure 7 shows how some
letters are skipped in this coordinate system: skipped letters are I, O, Q, S,
X, and Z.
1 AT93000-1900002 is a general-purpose custom family board. Customers may also choose to design their own custom family board to map a different configuration of V93K tester resources to their loadboard. In the case of their own custom family board, this manual’s resource mapping descriptions may not apply.
Family Board SMP connections
There are SMP connectors on the Family Board. That provide a path between
the customer’s loadboard and the Family Board, via the Advantest Pogo Blocks.
This means that the loadboard and Family board can be electrically connected
when the loadboard is docked to the twinning frame without having to manually
connect/disconnect any cables. The SMP connectors are labeled so that it is
easy to identify which pogo block pin is connected to which Family Board SMP
connector. For example, in Figure 8 on page 9, the SMP silkscreen for SMP2
also has the label “TP-1A-B3”.
- TP = Test Point (used for bringing DUT loadboard signals down to family board)
- 1A = POGO BLOCK 1A (see Figure 3 on page 5)
- B3 = POGO pin coordinate B3 in the POGO BLOCK (see Figure 6 on page 7)
In addition to bring single-ended signals from the loadboard, some of the SMP traces are laid out as differential pairs on the Family Board. While this is not an ideal different pair, it is the best compromise going through the digital pogo blocks.
- Differential pair traces on DUT loadboard (customer responsibility)
- POGO block pins are run as single-ended (no ability to run as differential)
- Differential pair traces on Family Board
o SMP1/SMP2, same trace lengths
o SMP3/SMP4, same trace lengths
o SMP5 (no paired trace)
o SMP6/SMP7, same trace lengths
Refer to Appendix 1 on page 11 for more information about detailed pin list
file.
Basically, B1 to B17 are all equal length traces, could be taken any two of
them as a differential pair.
One application for this additional path is to bring a Multisite REFCLK up to
the DUT loadboard or visa-versa. Figure 9 on page 9 shows how signals can be
connected via the POGO BLOCK. The coax cable connection choices are arbitrary
and shown for informational purposes. The populated SMP connectors on the
Family Board are SMP2 and SMP3. The clock sync circuits on the MultiLane
backplanes can be driven as either single-ended or differential. In this
example, they are being driven as single-ended.
Figure 9: Example connections from DUT Load board to ML Backplane
The Input impedance to the CLK IN connector on the backplane AT4000 is 100 . The schematic shows a 100 Ω Single Ended to GND (R29/R30), the clock buffer requires this termination when the input is LVPECL.
Figure 10: Clock Sync CLK IN circuit, backplanes #1 and #2
Figure 11: LVPECL Interface (AC-Coupled)
Quite often, a customer creates a clock on his loadboard using a SiLab device.
The clock output from the SiLab device can travel down to the Family Board
using the path just described through the POGO BLOCK.
The SiLab output is usually differential LVPECL. The MultiLane clock sync will
accept either a singleended or differential input from the SiLab device.
Ideally, the SiLab output will be routed in a differential fashion to minimize
the clock noise and jitter being disseminated through the backplane. However,
for slower clock sync signals in the 100’s of MHz, a single ended signal is
often used.
Note: The impedance for the differential pair should be 100 Ω.
After the cables are connected, there are jumpers on backplane #1 and #2 that have to be configured. Instructions how to set these jumpers can be found in the AT93000 System User Manual.
Appendix 1: Additional Resource Layout Views
A detailed pin list file is on the Multi Lane public website in Excel format:
AT93000-1900002 | Multi Lane (MultiLaneinc.com)
Rev. No.| Amendments| Revision
date
---|---|---
Section| Description
0.1| All| Initial revision DRAFT under review| 24-DEC-20
0.2| Overview of Family Board| Added link to pin list| 4-JAN-21
0.3| Title Page| Updated creation date from Jan 2020 to Jan 2021| 19-JAN-21
0.4| Family Board SMP Conn’s| New section added| 1-MAR-21
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