STMicroelectronics STM32H5 Series Microcontrollers User Manual

STMicroelectronics STM32H5 Series Microcontrollers

Introduction

This application note describes the instruction cache (ICACHE) and the data cache (DCACHE), the first caches developed by STMicroelectronics. The ICACHE and DCACHE introduced on the AHB bus of the Arm® Cortex®-M33 processor are embedded in the STM32 microcontroller (MCUs) listed in the table below. These caches allow users to improve their application performance and reduce the consumption when fetching instruction and data from both internal and external memories, or for data traffic from external memories. This document gives typical examples to highlight the ICACHE and DCACHE features and facilitate their configuration.

Table 1. Applicable products

General information

Note:

This application note applies to the STM32 series microcontrollers that are Arm® Cortex® core-based devices. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

ICACHE and DCACHE overview

This section provides an overview of the ICACHE and DCACHE interfaces embedded in the STM32 Arm® Cortex® core-based microcontrollers. This section details the ICACHE and DCACHE diagram and integration in the system architecture.
STM32L5 series smart architecture
This architecture is based on a bus matrix allowing multiple masters (Cortex-M33, ICACHE, DMA1/2, and SDMMC1) to access multiple slaves (such as flash memory, SRAM1/2, OCTOSPI1, or FSMC). The figure below describes the STM32L5 series smart architecture.

Figure 1. STM32L5 series smart architecture

The Cortex-M33 performance is improved by using the 8-Kbyte ICACHE interface introduced to its C-AHB bus, when fetching code or data from the internal memories (flash memory, SRAM1, or SRAM2) through the fast bus, and also from the external memories (OCTOSPI1 or FSMC) through the slow bus.
STM32U5 series smart architecture
This architecture is based on a bus matrix allowing multiple masters (Cortex-M33, ICACHE, DCACHE, GPDMA, DMA2D and SDMMCs, OTG_HS, LTDC, GPU2D, GFXMMU) to access multiple slaves (such as flash memory, SRAMs, BKPSRAM, HSPI/OCTOSPI, or FSMC).The figure below describes the STM32U5 series smart architecture.

Figure 2. STM32U5 series smart architecture

The Cortex-M33 and the GPU2D interfaces both benefit from using CACHE.

• ICACHE improves the performance of Cortex-M33 when fetching code or data from the internal memories through the fast bus (flash memory, SRAMs) and from external memories through the slow bus (OCTOSPI1/2 and HSPI1, or FSMC). DCACHE1 improves the performance when fetching data from internal or external memories through the s‑bus (GFXMMU, OCTOSPI1/2 and HSPI1, or FSMC).
•  DCACHE2 improves the performance of GPU2D when fetching data from internal and external memories (GFXMMU, flash memory, SRAMs, OCTOSPI1/2 and HSPI1, or FSMC) through the M0 port bus.

STM32H5 series smart architecture
STM32H523/H533, STM32H563/H573 and STM32H562 smart architecture This architecture is based on a bus matrix allowing multiple masters (Cortex-M33, ICACHE, DCACHE, GPDMAs, Ethernet and SDMMCs) to access multiple slaves (such as flash memory, SRAMs, BKPSRAM, OCTOSPI and FMC). The figure below describes the STM32H5 series smart architecture.

Figure 3. STM32H563/H573 and STM32H562 series smart architecture

The Cortex-M33 benefits from using CACHE.

• ICACHE improves the performance of Cortex-M33 when fetching code or data from the internal memories through a fast bus (flash memory, SRAMs) and from external memories through slow bus (OCTOSPI and FMC).
• DCACHE improves the performance when fetching data from external memories through the slow bus (OCTOSPI and FMC).

STM32H503 smart architecture
This architecture is based on a bus matrix allowing multiple masters (Cortex-M33, ICACHE and GPDMAs) to access multiple slaves (such as flash memory, SRAMs and BKPSRAM).  The figure below describes the STM32H5 series smart architecture.

Figure 4. STM32H503 series smart architecture

The Cortex-M33 benefits from using CACHE.

• ICACHE improves the performance of Cortex-M33 when fetching code or data from the internal memories through fast bus (flash memory, SRAMs).

ICACHE block diagram
The ICACHE block diagram is given in the figure below.

Figure 5. ICACHE block diagram

The ICACHE memory includes:

• the TAG memory with:
  • the address tags that indicate which data are contained in the cache data memory
  • the validity bits
•  the data memory, which contains the cached data

DCACHE block diagram
The DCACHE block diagram is given in the figure below.

Figure 6. DCACHE block diagram

The DCACHE memory includes:

• the TAG memory with:
  • the address tags that indicate which data are contained in the cache data memory
  • the validity bits
  • the privilege bits
  • the dirty bits
• the data memory, which contains the cached data

ICACHE and DCACHE features

Dual masters
The ICACHE accesses the AHB bus matrix either over:

• One AHB master port: master1 (fast bus)
• Two AHB master ports: master1 (fast bus) and master2 (slow bus)

This feature allows the traffic to be decoupled when accessing different memory regions (such as internal flash memory, internal SRAM and external memories), in order to reduce the CPU stalls on cache misses. The following table summarizes memory regions and their addresses.

Table 2. Memory regions and their addresses

Peripheral| Cacheable memory access| Not cacheable memory access
---|---|---

Type

| ****

Name

| ****

Product name and region size

| ****

Bus name

| ****

Nonsecure region starting address

| Secure, nonsecure callable region starting address| ****

Bus name

| ****

Nonsecure region starting address

| Secure, nonsecure callable region starting address

Internal

| ****

FLASH

| STM32H503| 128 KB| ****

ICACHE

fast bus

| ****

0x0800 0000

| N/A| ****

N/A

| ****

N/A

| ****

N/A

STM32L5

series/ STM32U535/ 545/ STM32H523/ 533

| ****

512 KB

| ****

0x0C00 0000

STM32U575/ 585

STM32H563/ 573/562

| ****

2 MB

STM32U59x/

5Ax/5Fx/5Gx

| 4 MB

SRAM1

| STM32H503| 16 KB| ****

0x0A00 0000

| N/A| ****

S‑bus

| ****

0x2000 0000

| ****

0x3000 0000

STM32L5

series/ STM32U535/ 545/575/585

| ****

192 KB

| ****

0x0E00 0000

STM32H523/ 533| 128 KB
STM32H563/ 573/562| 256 KB
STM32U59x/

5Ax/5Fx/5Gx

| 768 KB

SRAM2

| STM32H503

series

| 16 KB| 0x0A00 4000| N/A| 0x2000 4000| N/A
STM32L5

series/ STM32U535/ 545/575/585

| ****

64 KB

| ****

0x0A03 0000

| ****

0x0E03 0000

| ****

0x2003 0000

| ****

0x3003 0000

STM32H523/ 533| 64 KB| ****

0x0A04 0000

| ****

0x0E04 0000

| ****

0x2004 0000

| ****

0x3004 0000

Peripheral| Cacheable memory access| Not cacheable memory access
---|---|---

Internal

| ****

SRAM2

| STM32H563/ 573/562| 80 KB| ****

ICACHE

fast bus

| 0x0A04 0000| 0x0E04 0000| ****

S‑bus

| 0x2004 0000| 0x3004 0000
STM32U59x/

5Ax/5Fx/5Gx

| 64 KB| 0x0A0C 0000| 0x0E0C 0000| 0x200C 0000| 0x300C 0000

SRAM3

| STM32U575/ 585| 512 KB| 0x0A04 0000| 0x0E04 0000| 0x2004 0000| 0x3004 0000
STM32H523/ 533| 64 KB| ****

0x0A05 0000

| ****

0x0E05 0000

| ****

0x2005 0000

| ****

0x3005 0000

STM32H563/ 573/562| 320 KB
STM32U59x/

5Ax/5Fx/5Gx

| 832 KB| 0x0A0D 0000| 0x0E0D 0000| 0x200D 0000| 0x300D 0000
SRAM5| STM32U59x/

5Ax/5Fx/5Gx

| 832 KB| 0x0A1A 0000| 0x0E1A 0000| 0x201A 0000| 0x301A 0000
SRAM6| STM32U5Fx/

5Gx

| 512 KB| 0x0A27 0000| 0x0E27 0000| 0x2027 0000| ****

N/A

External

| HSPI1| STM32U59x/

5Ax/5Fx/5Gx

| ****

256 MB

| ****

ICACHE

slow bus

(1)

| ****

Alias address in the range of [0x0000 0000

to 0x07FF FFFF] or [0x1000 0000:0x1FFF

FFFF] defined by means of remapping feature

| ****

N/A

| 0xA000 0000
FMC SDRAM| STM32H563/ 573/562| 0xC000 0000

OCTOSPI1

bank nonsecure

| STM32L5/U5

series

STM32H563/ 573/562

| ****

0x9000 0000

FMC bank 3

nonsecure

| STM32L5/U5

series

STM32H563/ 573/562

| ****

0x8000 0000

OCTOSPI2

bank nonsecure

| STM32U575/

585/59x/5Ax/

5Fx/5Gx

| ****

0x7000 0000

FMC bank 1

nonsecure

| STM32L5/U5

series

STM32H563/ 573/562

| ****

0x6000 0000

1. To be selected when remapping such regions.

1-way versus 2-way ICACHE
By default, the ICACHE is configured in the associative operating mode (two ways enabled), but it is possible to configure the ICACHE in direct-mapped mode (one-way enabled), for applications requiring a very-low power consumption. The ICACHE configuration is done with the WAYSEL bit in ICACHE_CR as follows:

• WAYSEL = 0: direct mapped operating mode (1-way)
• WAYSEL = 1 (default): associative operating mode (2-way)

Table 3. 1-way versus 2-way ICACHE

1. For STM32L5 series /STM32H5 series /STM32U535/545/575/585
2. For STM32U59x/5Ax/5Fx/5Gx

Burst type
Some Octo-SPI memories support the WRAP burst, which provides the benefit of critical word-first feature performance. The ICACHE burst type of the AHB memory transaction for remapped regions is configurable. It implements incremental burst or WRAP burst, selected with the HBURST bit in the ICACHE_CRRx register. The differences between the WRAP and the incremental bursts are given below (see also the figure):

• WRAP burst:
  • cache line size = 128 bits
  • burst to start address = word address of the first data requested by the CPU
•  Incremental burst:
  • cache line size = 128 bits
  • burst starting address = address aligned on the boundary of the cache line containing the requested word

Figure 7. Incremental versus WRAP burst

Cacheable regions and remapping feature
The ICACHE is connected to the Cortex-M33 through the C-AHB bus and caches the code region from addresses [0x0000 0000 to 0x1FFF FFFF]. Since the external memories are mapped at an address in the range [0x6000 0000 to 0xAFFF FFFF], the ICACHE supports a remap feature that allows any external memory region to be remapped at an address in the range of [0x0000 0000 to 0x07FF FFFF] or [0x1000 0000 to 0x1FFF FFFF], and to become accessible through the C-AHB bus. Up to four external memory regions can be remapped with this feature. Once a region is remapped, the remap operation occurs even if the ICACHE is disabled or if the transaction is not cacheable. The cacheable memory regions can be defi ed and programmed by the user in the memory protection unit (MPU). The table below summarizes the configurations of the STM32L5 and STM32U5 series memories.

Table 4. Configuration of STM32L5 and STM32U5 series memories

Product memory

| Cacheable

(MPU programming)

| Remapped in ICACHE

(ICACHE_CRRx programming)

---|---|---
Flash memory| Yes or No| ****

Not required

SRAM| Not recommended
External memories (HSPI/ OCTOSPI or FSMC)| Yes or No| Required if the user wants external code fetching on C- AHB bus (else on S-AHB bus)

Benefit of ICACHE external memory remapping
The example in the figure below shows how to benefit from the ICACHE enhanced performance during code execution or data read when accessing an external 8-Mbyte external Octo-SPI memory (such as external flash memory or RAM).

Figure 8. Octo-SPI memory remap example

The following steps are needed to remap this external memory:

OCTOSPI configuration for the external memory

Configure the OCTOSPI interface in order to access the external memory in Memory mapped mode (the external memory is seen as an internal memory mapped in the [0x9000 0000 to 0x9FFF FFFF] region). Since the external memory size is 8 Mbytes, it is seen at the region [0x9000 0000 to 0x907F FFFF]. The external memory at this region is accessed through the S‑bus and is not cacheable. The next step shows the ICACHE configuration in order to remap this region.
Note: For the OCTOSPI configuration in memory-mapped mode, refer to the application note Octo‑ SPI interface on STM32 microcontrollers (AN5050

ICACHE configuration to remap the external memory-mapped region
The 8 Mbytes placed in the [0x9000 0000 to 0x907F FFFF] region are remapped to the [0x1000 0000 to 0x107F FFFF] region. They can then be accessed through the slow bus (ICACHE master2 bus).

• ICACHE_CR register configuration
  • Disable ICACHE with EN = 0.
  • Select 1-way or 2-way (depending on the application needs) with WAYSEL = 0 or 1, respectively.
• ICACHE_CRRx register configuration (up to four regions, x = 0 to 3)
  • Select the 0x1000 0000 base address (remap address) with BASEADDR [28:21] = 0x80.
  • Select the 8-Mbyte region size to remap with RSIZE[2:0] = 0x3.
  • Select the 0x9000 0000 remapped address REMAPADDR[31:21] = 0x480.
  • Select the ICACHE AHB master2 port for external memories with MSTSEL = 1.
  • Select the WRAP burst type with HBURST = 0.
  • Enable the remapping for region x with REN = 1.

The following figure shows how the memory regions are seen with IAR after enabling the remap.

Figure 9. Memory regions remapping example

The 8-Mbyte external memory is now remapped and can be accessed over the [0x1000 0000 to 0x107F FFFF] region.

ICACHE enable

• ICACHE_CR register configuration Enable the ICACHE with EN = 1.

Hit-and-miss monitors
ICACHE provides two monitors for performance analysis: a 32-bit hit monitor and a 16-bit miss monitor.

• The hit monitor counts the cacheable AHB transactions on the slave cache port that hits ICACHE content (fetched data already available in the cache). The hit monitor counter is available in the ICACHE_HMONR register.
• The miss monitor counts the cacheable AHB transactions on the slave cache port that miss ICACHE content (fetched data not already available in the cache). The missing monitor counter is available in the ICACHE_MMONR register.

Note:

These two monitors do not wrap over when reaching their maximum values. These monitors are managed from the following bits in the ICACHE_CR register:

• HITMEN bit (respectively MISSMEN bit) to enable/stop the hit (respectively miss) monitor
• HITMRST bit (respectively MISSMRST bit) to reset the hit (respectively miss) monitor By default, theses monitors are disabled in order to reduce power consumption.

ICACHE maintenance
The software can invalidate the ICACHE by setting the CACHEINV bit in the ICACHE_CR register. This action invalidates the whole cache, making it empty. Meanwhile, if some remapped regions are enabled, the remap feature is still active, even when the ICACHE is disabled. As the ICACHE only manages read transactions and does not manage write transactions, it does not ensure coherency in the case of writes. Consequently, the software must invalidate the ICACHE after programming a region.

ICACHE security
ICACHE is a securable peripheral that can be configured as secure through the GTZC TZSC secure configuration register. When it is configured as secure, only secure accesses are allowed to the ICACHE registers. ICACHE can also be configured as privileged through the GTZC TZSC privilege configuration register. When ICACHE is configured as privileged, only privileged accesses are allowed to the ICACHE registers. By default, the ICACHE is nonsecure and non-privileged through the GTZC TZSC.

Event and interrupt management

The ICACHE manages the functional errors when detected, by setting the ERRF flag in ICACHE_SR. An interrupt can also be generated if the ERRIE bit is set in ICACHE_IER. In case of ICACHE invalidation, when the cache busy state finished, the BSYENDF flag is set in ICACHE_SR. An interrupt can also be generated if the BSYENDIE bit is set in ICACHE_IER. The table below lists the ICACHE interrupt and event flags.

Table 5. ICACHE interrupt and event management bits

ICACHE_SR

| BUSY| Cache executing a full invalidate operation| ****

Read-only

BSYENDF| The cache invalidation operation finished
ERROR| An error occurred during caching operation

ICACHE_IER

| ERRIE| Enable interrupt for cache error| ****

Read/write

BSYENDIE| Enable interrupt in case of invalidation operation finished

ICACHE_FCR

| CERRF| Clears ERRF in ICACHE_SR| ****

Write-only

CBSYENDF| Clears BSYENDF in ICACHE_SR

DCACHE features
The purpose of the data cache is to cache external memory data loads and data stores coming from the processor or from another bus master peripheral. DCACHE manages both read and write transactions.
DCACHE cacheability traffic

The DCACHE caches the external memories from the master port interface through the AHB bus. The incoming memory requests are defined as cacheable according to its AHB transaction memory lockup attribute.  The DCACHE write policy is defined as write-through or write-back depending to the memory attribute configured by the MPU. When a region is configured as non-cacheable, the DCACHE is bypassed.

Table 6. DCACHE cacheability for AHB transaction

1

| ****

0

| Read: cacheable

Write: (cacheable) write-through

1

| ****

1

| Read: cacheable

Write: (cacheable) write-back

DCACHE cacheable regions
For the STM32U5 series, the DCACHE1 slave interface is connected to the Cortex-M33 through the S-AHB bus and caches the GFXMMU, FMC, and HSPI/OCTOSPIs. The DCACHE2 slave interface is connected to the DMA2D through the M0 port bus, and caches all the internal and external memories (except SRAM4 and BRKPSRAM). For the STM32H5 series, the DCACHE slave interface is connected to the Cortex-M33 through the S-AHB external memories through FMC and OCTOSPI.

Table 7. DCACHE cacheable regions and interfaces

Cacheable memory address region| DCACHE1 cacheable interfaces| DCACHE2 cacheable interfaces
---|---|---
GFXMMU| X| X
SRAM1| ****

N/A

| X
SRAM2| X
SRAM3| X
SRAM5| X
SRAM6| X
HSPI1| X| X
OCTOSPI1| X| X
FMC BANKs| X| X
OCTOSPI2| X| X

Note

Some interfaces are not supported in certain products. Refer to Figure 1 or the specific product reference manual.
Burst type
Same as ICACHE, the DCACHE supports incremental and wrapped bursts (see Section 3.1.3). For DCACHE, the burst type is configured through the HBURST bit in DCACHE_CR.
DCACHE configuration
During boot, DCACHE is disabled by default making the slave memory requests forwarded directly to the master port. To enable DCACHE, EN bit must be set in the DCACHE_CR register. Hit-and-miss monitors The DCACHE implements four monitors for cache performance analysis:

• Two 32-bit (R/W) hit monitor: counts the number of times the CPU read or write data in the cache memory without generating a transaction on DCACHE master ports (data already available in the cache). The (R/W) hit monitors counters are available respectively in the DCACHE_RHMONR and DCACHE_WHMONR registers.
• Two 16-bit (R/W) miss monitors: count the number of times the CPU read or write data in the cache memory and generates a transaction on DCACHE master ports, in order to load the data from the memory region (fetched data not already available in the cache). The (R/W) miss monitors counters are available respectively in the DCACHE_RMMONR and DCACHE_WMMONR registers.

Note:

These four monitors do not wrap over when reaching their maximum values. These monitors are managed from the following bits in the DCACHE_CR register:

• WHITMAN bit (respectively WMISSMEN bit) to enable/stop the write hit (respectively miss) monitor
• RHITMEN bit (respectively RMISSMEN bit) to enable/stop the read hit (respectively miss) monitor
• WHITMRST bit (respectively WMISSMRST bit) to reset the write hit (respectively miss) monitor
• RHITMRST bit (respectively RMISSMRST bit) to reset the read hit (respectively miss) monitor

By default, these monitors are disabled in order to reduce power consumption.

DCACHE maintenance
The DCACHE offers multiple maintenance operations that can be configured through CACHECMD[2:0] in DCACHE_CR.

• 000: no operation (default)
• 001: clean range. Clean a certain range in the cache
• 010: invalidate range. Invalidate a certain range in the cache
• 010: clean and invalidate range. Clean and invalidate a certain range in the cache

The selected range is configured through:

• CMDSTARTADDR register: command starting address
• CMDENDADDR register: command ending address

Note:

This register must be set before CACHECMD is written. The cache command maintenance starts when the STARTCMD bit is set in the DCACHE_CR register. The DCACHE also support a full CACHE invalidation by setting the CACHEINV bit in the DCACHE_CR register.

DCACHE security
The DCACHE is a secure peripheral that can be configured as secure through the GTZC TZSC secure configuration register. When it is configured as secure, only secure accesses are allowed to the DCACHE registers. DCACHE can also be configured as privileged through the GTZC TZSC privilege configuration register. When DCACHE is configured as privileged, only privileged accesses are allowed to the DCACHE registers. By default, the DCACHE is nonsecure and non-privileged through the GTZC TZSC.

Event and interrupt management
The DCACHE manages the functional errors when detected, by setting the ERRF flag in DCACHE_SR. An interrupt can also be generated if the ERRIE bit is set in DCACHE_IER. In case of DCACHE invalidation, when the cache busy state is finished, the BSYENDF flag is set in DCACHE_SR. An interrupt can also be generated if the BSYENDIE bit is set in DCACHE_IER. The DCACHE command status can be checked through CMDENF and BUSYCMDF through the DCACHE_SR An interrupt can also be generated if the CMDENDIE bit is set in DCACHE_IER. The table below lists the DCACHE interrupts and event flags

Table 8. DCACHE Interrupt and events management bits

DCACHE_SR

| BUSY| Cache executing a full invalidate operation| ****

Read-only

BSYENDF| Cache full invalidate operation ended
BUSYCMDF| Cache executing a range command
CMDENDF| A range command end
ERRF| An error occurred during caching operation

DCACHE_IER

| ERRIE| Enable interrupt for cache error| ****

Read/write

CMDENDIE| Enable interrupt on range command end
BSYENDIE| Enable interrupt on full invalidate operation end

DCACHE_FCR

| CERRF| Clears ERRF in DCACHE_SR| ****

Write-only

CCMDENDF| Clears CMDENDF in DCACHE_SR
CBSYENDF| Clears BSYENDF in DCACHE_SR

ICACHE and DCACHE performance and power consumption

Using ICACHE and DCACHE improve the application performance when accessing external memories. The following table shows the impact of ICACHE and DCACHE on CoreMark® execution when accessing external memories.

Table 9. ICACHE and DCACHE performance on CoreMark execution with external memories

(1)

CoreMark code| CoreMark Data| ICACHE configuration| DCACHE configuration| CoreMark score/Mhz
Internal Flash memory| Internal SRAM| Enabled (2-ways)| Disabled| 3.89
Internal Flash memory| External Octo-SPI PSRAM ( S‑bus)| Enabled (2-ways)| Enabled| 3.89
Internal Flash memory| External Octo-SPI PSRAM ( S‑bus)| Enabled (2-ways)| Disabled| 0.48
External Octo-SPI Flash (C-bus)| Internal SRAM| Enabled (2-ways)| Disabled| 3.86
External Octo-SPI Flash (C-bus)| Internal SRAM| Disabled| Disabled| 0.24
Internal Flash memory| Internal SRAM| Disabled| Disabled| 2.69

Test Conditions:

• Applicable product: STM32U575/585
• System frequency: 160 MHz.
• External Octo-SPI PSRAM memory: 80 MHz (DTR mode).
• External Octo-SPI flash memory: 80 MHz (STR mode).
• Compiler: IAR V8.50.4.
• Internal Flash PREFETCH: ON.

Using ICACHE and DCACHE reduce the power consumption when accessing internal and external memories. The following table shows the impact of ICACHE on power consumption during CoreMark execution.

Table 10. CoreMark execution ICACHE impact on power consumption

1. Test Conditions:
   • Applicable product: STM32U575/585
   • CoreMark code: internal Flash memory.
   • CoreMark data: internal SRAM.
   • Internal Flash memory PREFETCH: ON.
   • System frequency: 160 MHz.
   • Compiler: IAR V8.32.2.
   • Voltage range: 1.
   • SMPS: ON.
2. way set associative configuration is more performing than 1-way set associative configuration for code that cannot be fully loaded in cache. Meanwhile, 1-way set associative cache is almost always more power efficient than 2-way set associative cache. Each code has to be evaluated in both associativity configurations, in order to select the best trade-off between performance and power consumption. The selection depends on the user priority.

Conclusion

The first caches developed by STMicroelectronics, ICACHE and DCACHE, are able to cache internal and external memories, offering performance enhancement for data traffic and instruction fetches. This document shows the different features supported by the ICACHE and DCACHE, their configuration simplicity and flexibility allow lower development cost and faster time to market.

Revision history

Table 11. Document revision history

27-Feb-2020

| ****

2

| Updated:

•         Table 2. Memory regions and their addresses

•         Section 2.1.7 ICACHE maintenance

•         Section 2.1.8 ICACHE security

7-Dec-2021

| ****

3

| Updated:

•         Document title

•         Introduction

•         Section 1 ICACHE and DCACHE overview

•         Section 4 Conclusion Added:

•         Section 2 ICACHE and DCACHE features

•         Section 3 ICACHE and DCACHE performance and power consumption

15-Feb-2023

| ****

4

| Updated:

•         Section 2.2: STM32U5 series smart architecture

•         Section 2.5: DCACHE block diagram

•         Section 3.1.1: Dual masters

•         Section 3.1.2: 1-way versus 2-way ICACHE

•         Section 3.1.4: Cacheable regions and remapping feature

•         Section 3.2: DCACHE features

•         Section 3.2.2: DCACHE cacheable regions

•         Section 4: ICACHE and DCACHE performance and power consumption Added:

•         Section 1: General information

11-Mar-2024

| ****

5

| Updated:

•         Section 2.3: STM32H5 series smart architecture

•         Section 3.1.1: Dual masters

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