AzureWave XM549 Wireless LAN Bluetooth User Guide

AzureWave XM549 Wireless LAN Bluetooth

Features

WLAN

• IEEE 802.11a/b/g/n/ac/ax, 1×1 SISO 2.4 GHz and 5 GHz, up to 80 MHz channel
• Integrated high power PA up to +21 dBm transmit power
• Integrated LNA and T/R switches
• UL/DL OFDMA, UL/DL MU-MIMO
• 802.11ax ER, DCM, TWT
• 802.11az accurate ranging
• Security: WPA3 security with hardware encryption engines

Bluetooth

• Supports Bluetooth 5.3 Class 2 and Bluetooth Low Energy
• BDR/EDR packet types—1 Mbps (GFSK), 2 Mbps ( /4-DQPSK), 3 Mbps (8DPSK)
• Bluetooth LE long range (125/500 kbps) support improving range by 4x
• Bluetooth LE 2 Mbps
• Bluetooth LE advertising extensions for improved capacity
• Isochronous channels (ISOC) supporting Bluetooth Low Energy (LE) audio
• Security: AES

802.15.4

• IEEE 802.15.4-2015 compliant supporting Thread in 2.4 GHz band
• Shared transmitter and antenna pin with Bluetooth
• Simultaneous receive with Wi-Fi and Bluetooth
• MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers

Revision History

Document NO: R2-2549-DST-01

Version| Revision Date| DCN NO.| Description| Initials| Approved
---|---|---|---|---|---
A| 2022/07/01| DCN026641| l   Draft version| Roger Liu| N.C Chen
B| 2023/08/05| DCN029872| l   Update BT feature to 5.3

l   Update RF specification Update power consumption

| Roger Liu| N.C Chen
 |  |  |  |  |
 |  |  |  |  |

Introduction

Product Overview
AzureWave Technologies, Inc. introduces the IEEE 802.11a/b/g/n/ac/ax 1×1 dual- band WLAN, BT, and 802.15.4 tri-radio module – AW-XM549. With a full-feature Wi-Fi subsystem integrated into a module, AW-XM549 provides the best and most convenient SMT process. The module is targeted to smart entertainment, gateways, hubs, bridges, smart homes, industrial, point of sale (POS) terminals, smart appliances that need a convenient SMT process. By using AW- XM549, the customers can easily integrate the Wi-Fi, BT, 802.15.4 by a combo module with the benefits of high design flexibility, high success rate on the SMT process, short development cycle, and quick time-to-market. Compliance with the IEEE 802.11 a/b/g/n/ac/ax standard, the AW-XM549 uses DSSS, OFDM, DBPSK, DQPSK, CCK and QAM baseband modulation technologies. A high level of integration and full implementation of the power management functions specified in the IEEE 802.11 standard minimizes the system power requirements by using AW-XM549. The AW-XM549 supports standard interface SDIO3.0 for WLAN, UART for BT and SPI for 802.15.4. AW-XM549 is suitable for multiple mobile processors for different applications. With the combo functions and the good performance, the AW-XM549 is the best solution for consumer electronics and smart applications.

Block Diagram

• TBD

Specifications Table

General

5.3 and 802.15.4 tri-radio Module
Major Chipset| NXP IW612 WLCSP (140pins)
Host Interface| WiFi + BT + 802.15.4

l   SDIO + UART + SPI

Dimension| 12 mm X 12 mm x 2 mm(Max)
Form Factor| LGA module, 48 pins
Antenna| For LGA, “1T1R, external”

ANT(Main)：Wi-Fi / Bluetooth/802.15.4à TX / RX

Weight| 0.6 g

WLAN

Frequency Rage

| 2.4 GHz ISM Bands 2.412-2.472 GHz

5.15-5.25 GHz (FCC UNII-low band) for US/Canada and Europe 5.25-5.35 GHz (FCC UNII-middle band) for US/Canada and Europe 5.47-5.725 GHz for Europe

5.725-5.825 GHz (FCC UNII-high band) for US/Canada

Modulation| DSSS, OFDM, DBPSK, DQPSK, CCK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, OFDMA

Number of Channels

| 2.4GHz:

n   USA, NORTH AMERICA, Canada and Taiwan – 1 ~ 11

n   China, Australia, Most European Countries – 1 ~ 13

n   Japan, 1 ~ 13

5GHz:

n   USA, Canada, Most European Countries

-36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,

136,140,149,153,157,161,165

n   Japan – 36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,1 36,140

n   China – 36,40,44,48,52,56,60,64, 149,153,157,161,165

---|---

Output Power (Board Level **Limit)***

| 2.4G

5G

 |  | Min| Typ| Max| Unit|
11a (54Mbps)

@EVM≦-27 dB

| 14| 16| 18| dBm
11n (HT20 MCS7)

@EVM≦-28 dB

| 14| 16| 18| dBm
11n (HT40 MCS7)

@EVM≦-28 dB

| 14| 16| 18| dBm
11ac(VHT20 MCS8)

@EVM≦-31 dB

| 12| 14| 16| dBm
11ac(VHT40 MCS9)

@EVM≦-32 dB

| 12| 14| 16| dBm
11ac(VHT80 MCS9)

@EVM≦-32 dB

| 12| 14| 16| dBm
11ax(HE20 MCS11)

@EVM≦-35 dB

| 9| 11| 13| dBm
11ax(HE40 MCS11)

@EVM≦-35 dB

| 9| 11| 13| dBm
 |  | 11ax(HE80 MCS11) @EVM≦-35 dB| 9| 11| 13| dBm|
---|---|---|---|---|---|---|---

Receiver Sensitivity

| ****

2.4G

5G

Data Rate

| WLAN:

802.11b : 1, 2, 5.5, 11Mbps

802.11a/g : 6, 9, 12, 18, 24, 36, 48, 54Mbps

802.11n : Maximum data rates up to 72 Mbps (20 MHz channel), 150 Mbps (40 MHz channel)

802.11ac: Maximum data rates up to 433 Mbps (80 MHz channel) 802.11ax: Maximum data rates up to 600 Mbps (80 MHz channel)

Security

| n   WiFi: WPA3, WPA2, WPA2 and WPA mixed mode, WEP

n   BT: AES

n   802.15.4 :AES

• If you have any certification questions about output power please contact FAE directly.

Bluetooth

Modulation

| Header GFSK

Payload 2M: π/4-DQPSK Payload 3M: 8DPSK

Output Power

| |  | Min| Typ| Max| Unit
---|---|---|---|---
BDR| 0| 2| 4| dBm
EDR| 0| 2| 4| dBm
Low Energy| 0| 2| 4| dBm

Receiver Sensitivity

| BT Sensitivity (BER<0.1%)|  | Min| Typ| Max| Unit
---|---|---|---|---
BDR(DH1)| –| -89| -86| dBm
EDR(2DH5)| –| -87| -84| dBm
EDR(3DH5)| –| -81| -78| dBm
Low Energy| –| -91| -88| dBm

Thread

2.4 GHz band
Frequency Rage| 2400MHz~2483.5MHz
Modulation| O-QPSK

Output Power

| |  | Min| Typ| Max| Unit
---|---|---|---|---
Thread| 2| 4| 6| dBm

Receiver Sensitivity

| ****

Thread Sensitivity (PER<1%)

Operating Conditions

Operating Conditions
Voltage| 3.3V +-5%
Operating Temperature| 0 oC to +70 oC
Operating Humidity| Less than 85% R.H.
Storage Temperature| -40 oC to +85 oC
Storage Humidity| Less than 60% R.H.
ESD Protection
Human Body Model| +-2kV
Changed Device Model| +-500V

Pin Definition

Pin Map

Pin Table

Pin No| Definition| Basic Description| Voltage| Type
---|---|---|---|---
1| GND1| Ground| —| —
2| RF_ANT| RF pin out| —| I/O
3| GND3| Ground| —| —
4| SPI_TXD| SPI receive output signal| VDDIO| I/O
5| SPI_RXD| SPI receive input signal| VDDIO| I/O
6| HOSTWAKE BT| GPIO Mode : GPIO[18].

BT Device Wake

| VDDIO| I/O
7| BT_WAKE_HOST| GPIO Mode : GPIO[19].

BT Host Wake

| VDDIO| I/O
8| SPI_FRM| SPI_FRM – SPI frame signal| VDDIO| I/O
9| VBAT| 3.3V power voltage source input| 3.3V| P
10| JTAG_TMS| JTAG test mode select input signal. GPIO[29]| VDDIO| I/O
11| SPI_CLK| SPI_CLK – SPI clock signal| VDDIO| I/O

12

| ****

PDn

| Full Power-down (input) (active low) 0 = full power-down mode

1 = normal mode

(Need external pull high 51k resistor to VDDIO)

| 1.8V/3.3V| ****

I

13| WL_WAKE_HOST| GPIO Mode : GPIO[17].

Wi-Fi radio wake-up output signal

| VDDIO| O
14| SDIO_DATA2| SDIO Data line Bit[2]| VDDIO| I/O
15| SDIO_DATA3| SDIO Data line Bit[3]| VDDIO| I/O
16| SDIO_CMD| SDIO Command| VDDIO| I/O
17| SDIO_CLK| SDIO Clock input| VDDIO| I
18| SDIO_DATA0| SDIO Data line Bit[0]| VDDIO| I/O
19| SDIO_DATA1| SDIO Data line Bit[1]| VDDIO| I/O
20| GND20| Ground| —| —
21| DCDC_1V8_OUT| Internal DC-DC output

(Need external 1uH power inductor)

| 1.8V| P
22| VDDIO| 1.8V/3.3V Digital I/O Power Supply| 1.8V/3.3V| P
23| 1V8_IN| 1.8V power voltage source input| 1.8V| P
24| NC24| Floating Pin, No connect to anything.| —| Floating
25| BT_PCM_OUT| PCM Data output / GPIO[5]| VDDIO| O
26| BT_PCM_CLK| PCM Clock / GPIO[4]| VDDIO| I/O
27| BT_PCM_IN| PCM data input / GPIO[6]| VDDIO| I
28| BT_PCM_SYNC| PCM sync signal / GPIO[7]| VDDIO| I/O
29| JTAG_TDO| JTAG test data output signal. GPIO[31]| VDDIO| O
30| JTAG_TDI| JTAG test data input signal. GPIO[30]| VDDIO| I
31| GND31| Ground| —| —
32| NC32| Floating Pin, No connect to anything.| —| Floating
33| GND33| Ground| —| —
34| BT_DIS| Host-to-BT reset /IND_RST_BT – Independent software reset for Bluetooth / GPIO[2]| VDDIO| I
35| JTAG_TCK| JTAG test clock input signal. GPIO[28]| VDDIO| I
36| GND36| Ground| —| —
---|---|---|---|---
37| Host-to-Wi-Fi reset| GPIO Mode: GPIO[1].

Independent software reset for Wi-Fi

| VDDIO| I
38| MWS_SOUT| WCI-2 MWS coexistence serial transport interface(TX) / GPIO[26]| VDDIO| I/O
39| MWS_SIN| WCI-2 MWS coexistence serial transport interface(RX) / GPIO[25]| VDDIO| I/O

40

| ****

HOST_WAKE_WL

| GPIO Mode: GPIO[16].

Host-to-WLAN wake

/ Wi-Fi radio wake-up input signal

| ****

VDDIO

| ****

I

41| UART_RTS_N| UART_RTSn (active low)| VDDIO| O
42| UART_TXD| UART_SOUT| VDDIO| O
43| UART_RXD| UART_SIN(active high)| VDDIO| I
44| UART_CTS| UART_CTS(active high)| VDDIO| I
45| GND45| Ground| —| —
46| IND_RST_15.4| Independent software reset for 802.15.4 / GPIO[24]| VDDIO| I/O
47| RST_IND| Independent software reset indicator output signal to host / GPIO[22]| VDDIO| I/O
48| SPI_INT| SPI interrupt signal / GPIO[20]| VDDIO| I/O

Electrical Characteristics

Absolute Maximum Ratings

Symbol| Parameter| Minimum| Typical| Maximum| Unit
---|---|---|---|---|---
VBAT| DC supply for the 3.3V input| –| 3.3| 3.96| V

VDDIO

| ****

I/O power supply

| –| 3.3| 3.96| ****

V

–| 1.8| 2.16

Recommended Operating Conditions

Symbol| Parameter| Minimum| Typical| Maximum| Unit
---|---|---|---|---|---
VBAT| DC supply for the 3.3V input| 3.14| 3.3| 3.46| V

VDDIO

| 1.8V/3.3V digital I/O power supply| 3.14| 3.3| 3.46| ****

V

1.71| 1.8| 1.98

Digital IO Pin DC Characteristics

Operation (VDDIO)

Symbol| Parameter| Minimum| Typical| Maximum| Unit
---|---|---|---|---|---
VIH| Input high voltage| 0.7*VIO| –| VIO+0.4| ****

V

VIL| Input low voltage| -0.4| –| 0.3*VIO
VOH| Output high voltage| VIO-0.4| –| –
VOL| Output low voltage| –| –| 0.4
VHYS| Input Hysteresis| 100|  |  | mV

Operation (VDDIO)

Symbol| Parameter| Minimum| Typical| Maximum| Unit
---|---|---|---|---|---
VIH| Input high voltage| 0.7*VIO| –| VIO+0.4| ****

V

VIL| Input low voltage| -0.4| –| 0.3*VIO
VOH| Output High Voltage| VIO-0.4| –| –
VOL| Output Low Voltage| –| –| 0.4
VHYS| Input Hysteresis| 100|  |  | mV

Host Interface

SDIO Interface
The AW-XM549 supports a SDIO device interface that conforms to the industry SDIO Full-Speed card specification and allows a host controller using the SDIO bus protocol to access the Wireless SoC device. The AW-XM549 acts as the device on the SDIO bus. The host unit can access registers of the SDIO interface directly and can access shared memory in the device through the use of BARs and a DMA engine.

• Support SDIO 3.0 Standard.
• On-chip memory used for CIS.
• Supports 4-bit SDIO and 1-bit SDIO transfer modes.
• Special interrupt register for information exchange.
• Allows card to interrupt host.

SDIO Interface Signals

AW- XM549

SDIO Pin Name

| ****

Type

| ****

Description

---|---|---
SDIO_CLK| I| SDIO 4-bit mode: Clock SDIO 1-bit mode: Clock
SDIO_CMD| I/O| SDIO 4-bit mode: Command line SDIO 1-bit mode: Command line
SDIO_DATA3| I/O| SDIO 4-bit mode: Data line Bit[3] SDIO 1-bit mode: Not used
SDIO_DATA2| I/O| SDIO 4-bit mode: Data line Bit[2] or Read Wait (optional) SDIO 1-bit mode: Read Wait (optional)
SDIO_DATA1| I/O| SDIO 4-bit mode: Data line Bit[1] SDIO 1-bit mode: Interrupt
SDIO_DATA0| I/O| SDIO 4-bit mode: Data line Bit[0] SDIO 1-bit mode: Data line

SDIO Protocol Timing

Default Speed, High-Speed Modes (3.3V)

Symbol| Parameter| Condition| Min| Typ| Max| Units
---|---|---|---|---|---|---
fpp| CLK Frequency| Normal| 0| —| 25| MHz
High Speed| 0| —| 50| MHz
TWH| CLK High Time| Normal| 10| —| —| ns
High Speed| 7| —| —| ns
TWL| CLK Low Time| Normal| 10| —| —| ns
High Speed| 7| —| —| ns
TISU| Input Setup Time| Normal| 5| —| —| ns
High Speed| 6| —| —| ns
TIH| Input Hold Time| Normal| 5| —| —| ns
High Speed| 2| —| —| ns
TODLY| Output Delay Time| Normal| —| —| 14| ns
CL ≦ 40pF (1 card)| High Speed| —| —| 14| ns
TOH| Output Hold Time| High Speed| 2.5| —| —| ns

SDIO Timing Data – Default Speed / High-Speed modes. (3.3V)

SDR12, SDR25, SDR50 Modes (up to 100MHz) (1.8V)

Symbol| Parameter| Condition| Min| Typ| Max| Units
---|---|---|---|---|---|---
Fpp| CLK Frequency| SDR12/25/50| 25| –| 100| MHz
TCLK| Clock Time| SDR12/25/50| 10| –| 40| ns
TIS| Input Setup Time| SDR12/25/50| 3| –| –| ns
TIH| Input Hold Time| SDR12/25/50| 0.8| –| –| ns
TCR ,TCF| Rise time, fail time

TCR ,TCF <2ns(max) at 100MHz CCARD =10pF

|

SDR12/25/50

|

–

|

–

|

0.2*TCLK

|

ns

TODLY| Output Delay Time

CL ≦ 30pF

| SDR12/25/50| –| –| 7.5| ns
TOH| Output Hold Time CL =15pF| SDR12/25/50| 1.5| –| –| ns

SDIO Timing Data – SDR12/25/50 modes. (1.8V)

SDR104 mode (208MHz) (1.8V)

Symbol| Parameter| Condition| Min| Typ| Max| Units
---|---|---|---|---|---|---
Fpp| CLK Frequency| SDR104| 0| –| 208| MHz
TCLK| Clock Time| SDR104| 4.8| –| –| ns
TIS| Input Setup Time| SDR104| 1.4| –| –| ns
TIH| Input Hold Time| SDR104| 0.8| –| –| ns
TCR ,TCF| Rise time, fail time

TCR,TCF<0.96ns(max) at 208MHz

CARD =10pF

| SDR104| ****

–

| ****

–

| ****

0.2*TCLK

| ****

ns

TOP| Card output phase| SDR104| 0| –| 10| ns
TODD| Output timing of variable data window| SDR104| 2.88| –| –| ns

High-Speed UART Interface
The AW-XM549 supports a high-speed Universal Asynchronous Receiver/Transmitter (UART) interface, compliant to the industry standard 16550 specification. High-speed baud rates are supported to provide the physical transport between the device and the host for exchanging Bluetooth data.

Symbol| Parameter| Condition| Min| Typ| Max| Units
---|---|---|---|---|---|---
TBAUD| Baud rate| 26MHz or 40MHz input clock| 250| –| –| ns

PCM Interface

PCM Timing Specification – Master Mode

Symbol| Parameter| Condition| Min| Typ| Max| Units
---|---|---|---|---|---|---
FBCLK| —| —| —| 2/2.048| —| MHz
Duty CycleBCLK| —| —| 0.4| 0.5| 0.6| —
TBCLK rise/fall| —| —| —| 3| —| ns
TDO| —| —| —| —| 15| ns
TDISU| —| —| 20| —| —| ns
TDIHO| —| —| 15| —| —| ns
TBF| —| —| —| —| 15| ns

PCM Timing Specification – Slave Mode

Symbol| Parameter| Condition| Min| Typ| Max| Units
---|---|---|---|---|---|---
FBCLK| —| —| —| 2/2.048| —| MHz
Duty CycleBCLK| —| —| 0.4| 0.5| 0.6| —
TBCLK rise/fall| —| —| —| 3| —| ns
TDO| —| —| —| —| 30| ns
TDISU| —| —| 15| —| —| ns
TDIHO| —| —| 10| —| —| ns
TBFSU| —| —| 15| —| —| ns
TBFHO|  |  | 10|  | —| ns

SPI Interface

Symbol| Parameter| Condition| Min| Typ| Max| Units
---|---|---|---|---|---|---
TSLCH| Chip select setup time| —| 12| —| —| ns
TSHCH| Chip select hold time| —| 12| —| —| ns
TCLK| Clock period| —| 40| —| —| ns
TIS| Input setup time| —| 12| —| —| ns
TIH| Input hold time| —| 0| —| —| ns
TODLY| Output delay| —| —| —| 12| ns

Timing Sequence
AW-XM549 power up timing sequence.

Power Consumption

WLAN

Band (GHz)

| ****

Mode

| ****

BW (MHz)

| ****

RF Power (dBm)

| Transmit (mA)

Max.

| ****

Avg.

| Duty Cycle Avg. (%)

2.4

| 11b@1Mbps| 20| 17| 295| 294| 99
11g@54Mbps| 20| 16| 278| 276| 88
11n@MCS0| 40| 14| 271| 269| 96
11n@MCS7| 40| 14| 251| 248| 81
11ax@MCS0 NSS1| 40| 12| 258| 255| 96
11ax@MCS11 NSS1| 40| 12| 232| 231| 77

5

| 11a@6Mbps| 20| 16| 410| 404| 98
11n@MCS0| 40| 16| 415| 410| 96
11n@MCS7| 40| 16| 375| 369| 80
11ac@MSC0 NSS1| 80| 14| 378| 372| 93
11ac@MSC9 NSS1| 80| 14| 332| 328| 72
11ax@MSC0 NSS1| 80| 11| 327| 324| 92
11ax@MSC11 NSS1| 80| 11| 296| 294| 76
Band (GHz)| Mode| BW(MHz)| Receive (mA)
Max.| Avg.

2.4

| 11b@11Mbps| 20| 61| 58
11n@MCS7| 40| 73| 71
11ax@MCS11 NSS1| 40| 73| 69

5

| 11a@54Mbps| 20| 73| 72
11n@MCS7| 40| 83| 82
11ac@MCS9 NSS1| 80| 101| 100
11ax@MCS11 NSS1| 80| 100| 98
No.| Item| JP4_PIN2 VIO_3.3V (uA)
---|---|---
Max.| Avg.
1| Pdn (1)(2)| 23| 23
2| Deepsleep(2)(3)| 181| 181
3| Power Save 2.4GHz (DTIM-1)(2)(3)(4)| 327| 189
4| Power Save 5GHz (DTIM-1)(2)(3)(4)| 327| 187
Band (GHz)| Mode| BW (MHz)| RF Power (dBm)| Transmit (uA)
Max.| Avg.

2.4

| 11b@1Mbps| 20| 17| 480| 479
11ax@MCS11 NSS1| 40| 12| 473| 472

5

| 11a@6Mbps| 20| 16| 498| 496
11ax@MSC11 NSS1| 80| 11| 484| 484
Band (GHz)| Mode| BW(MHz)| Receive (uA)
Max.| Avg.
2.4| 11b@11Mbps| 20| 448| 447
5| 11ax@MCS11 NSS1| 80| 453| 453
No.| Item| JP4_PIN2 VIO_1.8V (uA)
---|---|---
Max.| Avg.
1| Pdn (1)(2)| 2| 2
2| Deepsleep(2)(3)| 61| 61
3| Power Save 2.4GHz (DTIM-1)(2)(3)(4)(5)| 61| 61
4| Power Save 5GHz (DTIM-1)(2)(3)(4)(5)| 61| 61
Band (GHz)| Mode| BW (MHz)| RF Power (dBm)| Transmit (uA)
Max.| Avg.

2.4

| 11b@1Mbps| 20| 17| 44| 44
11ax@MCS11 NSS1| 40| 12| 44| 44

5

| 11a@6Mbps| 20| 16| 45| 44
11ax@MSC11 NSS1| 80| 11| 45| 44
Band (GHz)| Mode| BW(MHz)| Receive (uA)
Max.| Avg.
2.4| 11b@11Mbps| 20| 44| 44
5| 11ax@MCS11 NSS1| 80| 44| 44
1| Deepsleep(1)| N/A| 0.6| 0.4|
---|---|---|---|---|---
2| Transmit(2)| DH5| 2| 53| 36|
3| Receive*(2)| DH5| N/A| 53| 31|

No.

| ****

Mode

| ****

Packet Type

| RF Power (dBm)| JP4_PIN2 VIO_3.3V (uA)
Max.| Avg.
1| Deepsleep(1)| N/A| 180| 179
2| Transmit(2)| DH5| 2| 437| 436
3| Receive*(2)| DH5| N/A| 437| 436

No.

| ****

Mode

| ****

Packet Type

| RF Power (dBm)| JP4_PIN2 VIO_1.8V (uA)|
Max.| Avg.|
1| Deepsleep(1)| N/A| 61| 61|
2| Transmit(2)| DH5| 2| 43| 42|
3| Receive*(2)| DH5| N/A| 43| 42|

802.15.4

No.

| ****

Mode

| Modulation Type| RF Power (dBm)| JP1_PIN2 VBAT_3.3V (mA)
---|---|---|---|---
Max.| Avg.
1| Deepsleep(1)(2)| N/A| 0.3| 0.13
2| Transmit(3)(4)| O-QPSK| 4| 81| 53
3| Receive*(3)(5)| O-QPSK| N/A| 43| 42

No.

| ****

Mode

| ****

Packet Type

| RF Power (dBm)| JP4_PIN2 VIO_3.3V (uA)
Max.| Avg.
1| Deepsleep(1)(2)| N/A| 457| 457
2| Transmit(3)(4)| O-QPSK| 4| 571| 570
3| Receive*(3)(5)| O-QPSK| N/A| 571| 570

No.

| ****

Mode

| ****

Packet Type

| RF Power (dBm)| JP4_PIN2 VIO_1.8V (uA)
Max.| Avg.
1| Deepsleep(1)(2)| N/A| 118| 118
2| Transmit(3)(4)| O-QPSK| 4| 194| 193
3| Receive*(3)(5)| O-QPSK| N/A| 194| 193

Sleep Clock (Optional)
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.

External 32.768KHz Low-Power Oscillator

CLK

| Clock frequency range/ accuracy

n   CMOS input clock signal type

n   ±250 ppm (initial, aging, temperature)

| ****

–

| 32.768| ****

–

| ****

kHz

PN| Phase noise requirement (@ 100KHz)| –| -125| –| dBc/Hz
JC| Cycle jitter| –| 1.5| –| ns (RMS)
SR| Slew rate limit (10-90%)| –| –| 100| ns
DC| Duty cycle tolerance| 20| –| 80| %

Mechanical Information

Mechanical Drawing

Packing Information

1. One reel can pack 1,500pcs 12×12 LGA modules
2. One production label is pasted on the reel, one desiccant and one humidity indicator card are put on the reel
3. One reel is put into the anti-static moisture barrier bag, and then one label is pasted on the bag
4. A bag is put into the anti-static pink bubble wrap
5. A bubble wrap is put into the inner box and then one label is pasted on the inner box
6. 5 inner boxes could be put into one carton
7. Sealing the carton by AzureWave tape
8. One carton label and one box label are pasted on the carton. If one carton is not full, one balance label pasted on the carton

FCC

Federal Communication Commission Interference Statement
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and the receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.

FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate this equipment. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

IMPORTANT NOTE

FCC Radiation Exposure Statement
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance 20cm between the radiator & your body.

IMPORTANT NOTE
This module is intended for OEM integrators. This module is only FCC- authorized for the specific rule parts listed on the grant, and the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. The final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. Additional testing and certification may be necessary when multiple modules are used. The host manufacturer should reference KDB Publication 996369 D04 Module Integration Guide.

USERS MANUAL OF THE END PRODUCT:
In the users manual of the end product, the end-user has to be informed to keep at least 20cm separation with the antenna while this end product is installed and operated. The end user has to be informed that the FCC radio- frequency exposure guidelines for an uncontrolled environment can be satisfied. The end user has to also be informed that any changes or modifications not expressly approved by the manufacturer could void the user’s authority to operate this equipment. This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation.

LABEL OF THE END PRODUCT
The final end product must be labeled in a visible area with the following ” Contains TX FCC ID: TLZ-XM549″. This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation.

IC:
This device contains licence-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic Development Canada’s licence-exempt RSS(s). Operation is subject to the following two conditions:

1. This device may not cause interference.
2. This device must accept any interference, including interference that may cause undesired operation of the device.

This device and its antenna(s) must not be co-located with any other transmitters except following IC multi-transmitter product procedures. Referring to the multi-transmitter policy, multiple-transmitter(s) and module(s) can be operated simultaneously without reassessment permissive change.This radio transmitter [6100A-XM549] has been approved by Innovation, Science and Economic Development Canada to operate with the antenna types listed below, with the maximum permissible gain indicated. Antenna types not included in this list that have a gain greater than the maximum gain indicated for any type listed are strictly prohibited for use with this device. The device for operation in the band 5150–5250 MHz is only for indoor use to reduce the potential for harmful interference to co-channel mobile satellite systems.The maximum antenna gain permitted for devices in the bands 5250-5350 MHz and 5470-5725 MHz shall be such that the equipment still complies with the e.i.r.p. limit. The maximum antenna gain permitted for devices in the band 5725-5850 MHz shall be such that the equipment still complies with the e.i.r.p. limits specified for point-to-point and non-point-to-point operation as appropriate. For indoor use only.

IMPORTANT NOTE:

IC Radiation Exposure Statement
This equipment complies with IC RSS-102 radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance 20cm between the radiator & your body.

IMPORTANT NOTE:
This module is intended for OEM integrators. The OEM integrator is responsible for compliance to all the rules that apply to the product into which this certified RF module is integrated. Additional testing and certification may be necessary when multiple modules are used. Any changes or modifications not expressly approved by the manufacturer could void the user’s authority to operate this equipment.

USERS MANUAL OF THE END PRODUCT
In the user’s manual of the end product, the end-user has to be informed to keep at least 20cm separation with the antenna while this end product is installed and operated. The end-user has to be informed that the IC radio- frequency exposure guidelines for an uncontrolled environment can be satisfied. The end user has to also be informed that any changes or modifications not expressly approved by the manufacturer could void the user’s authority to operate this equipment. Operation is subject to the following two conditions: (1) this device may not cause harmful interference (2) this device must accept any interference received, including interference that may cause undesired operation.

LABEL OF THE END PRODUCT:
The final end product must be labeled in a visible area with the following ” Contains IC: 6100A-XM549 “. The Host Model Number (HMN) must be indicated at any location on the exterior of the end product or product packaging or product literature which shall be available with the end product or online.

Ant list

Ant.| Port| Brand| Model Name| Antenna Type| Connector| Gain (dBi)
---|---|---|---|---|---|---
1| 1| MAG. LAYERS| MSA-4008-25GC1-A2| PIFA Antenna| I-PEX|

Note1

2| –| CEL| 0032-02-07-00-001| PIFA Antenna| I-PEX

Note1:

Ant.

| Gain (dBi)
---|---
WLAN 2.4GHz/Bluetooth/Thread| WLAN 5GHz
1| 2.98| 5.16
2| 1.30| 4.30

The information contained herein is the exclusive property of AzureWave and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of AzureWave.

Revision History

Version| Revision Date| Description| Initials| Approved
---|---|---|---|---
01| 2022/04/06| l   Initial Version| Roger Liu| N.C. Chen

INTRODUCTION

This document provides key guidelines and recommendations to be followed when creating AW- XM553 layout. It is strongly recommended that layouts be reviewed by the AzureWave engineering team before being released for fabrication. The following is a summary of the major items that are covered in detail in this application note. Each of these areas of the layout should be carefully reviewed against the provided recommendations before the PCB goes to fabrication.

• GENERAL RF GUIDELINES
• Ground Layout
• Power Layout
• Digital Interface
• RF Trace
• Antenna
• Antenna Matching
• GENERAL LAYOUT GUIDELINES
• THE OTHER LAYOUT GUIDE INFORMATION

GENERAL RF GUIDELINES

Follow these steps for optimal WLAN performance.

1. Control WLAN 50 ohm RF traces by doing the following:
   • Route traces on the top layer as much as possible and use a continuous reference ground plane underneath them.
   • Verify trace distance from ground flooding. At a minimum, there should be a gap equal to the width of one trace between the trace and ground flooding. Also keep RF signal lines away from metal shields. This will ensure that the shield does not detune the signals or allow for spurious signals to be coupled in.
   • Keep all trace routing inside the ground plane area by at least the width of a trace.
   • Check for RF trace stubs, particularly when bypassing a circuit.
2. Keep RF traces properly isolated by doing the following:
   • Do not route any digital or analog signal traces between the RF traces and the reference ground.
   • Keep the balls and traces associated with RF inputs away from RF outputs. If two RF traces are close each other, then make sure there is enough room between them to provide isolation with ground fill.
   • Verify that there are plenty of ground vias in the shield attachment area. Also verify that there are no non-ground vias in the shield attachment area. Avoid traces crossing into the shield area on the shield layer.
3. Consider the following RF design practices:
   • Confirm antenna ground keep-outs.
   • Verify that the RF path is short, smooth, and neat. Use curved traces or microwave corners for all turns; never use 90-degree turns. Avoid width discontinuities over pads. If trace widths differ significantly from component pad widths, then the width change should be mitred. Verify there are no stubs.
   • Do not use thermals on RF traces because of their high loss.
   • The RF traces between the AW-XM553 RF_ANT pin and antenna must be made using a 50Ω controlled-impedance transmission line.

Ground Layout
Please follow general ground layout guidelines. Here are some general rules for customers’ reference.

• The layer 2 of PCB should be a complete ground plane. The rule has to be obeyed strictly in the RF section while RF traces are on the top layer.
• Each ground pad of components on the top layer should have via drilled to PCB layer 2 and via should be as close to pad as possible. A bulk decoupling capacitor needs two or more.
• Don’t place the ground plane and route signal trace below the printed antenna or chip antenna to avoid destroying its electromagnetic field, and there is no organic coating on the printed antenna. Check the antenna chip vendor for the layout guidelines and clearance.
• Move GND vias close to the pads.

Power Layout
Please follow general power layout guidelines. Here are some general rules for customers’ reference.

• A 4.7uF capacitor is used to decouple high-frequency noise at digital and RF power terminals. This capacitor should be placed as close to power terminals as possible.
• To reduce PCB’s parasitic effects, placing more via on the ground plane is better.

Digital Interface
Please follow power and ground layout guidelines. Here are some general rules for customers’ reference.

• The digital interface to the module must be routed using good engineering practices to minimize coupling to power planes and other digital signals.
• The digital interface must be isolated from RF trace.

RF Trace and RF PAD

• A. RF Trace

The RF trace is critical to route. Here are some general rules for customers’ reference.

• The RF trace impedance should be 50Ω between ANT port and antenna matching network.
• The length of the RF trace should be minimized.
• To reduce the signal loss, RF trace should laid on the top of PCB and avoid any via on it.
• The CPW (coplanar waveguide) design and the microstrip line are both recommended; the customers can choose either one depending on the PCB stack of their products.
• The RF trace must be isolated with aground beneath it. Other signal traces should be isolated from the RF trace either by ground plane or ground vias to avoid coupling.
• To minimize the parasitic capacitance related to the corner of the RF trace, the right angle corner is not recommended.

If the customers have any problem in the calculation of trace impedance, please contact AzureWave.

Incorrect RF trace
AW-XM553 RF trace should follow the rules as below

• The line length of the Antenna trace is about 88.7mi and 68.5 mil
• Line width of Antenna trace about 10 mil
• The air gap between the RF trace and the ground is about 4.5 mil
• RF PAD TOP layer: The air gap between RF PAD and the ground is 4.5 mil
• Inner Layer(L2): The length and width of keep out under RF PAD is 32.6 and 52.8 mil.
• Inner Layer(L3): Must be continuous reference ground plane
• Bot Layer: Must be continuous reference ground plane

Antenna
All the high-speed traces should be moved far away from the antenna. For the best radiation performance, check the antenna chip vendor for the layout guidelines and clearance.

Antenna Matching
PCB designer should reserve an antenna matching network for post-tuning to ensure the antenna performance in different environments. Matching components should be close to each other. Stubs should also be avoided to reduce parasites while no shunt component is necessary after tuning.

SHIELDING CASE

Magnetic shielding, ferrite drum shielding, or magnetic-resin-coated shielding is highly recommended to prevent EMI issues.

GENERAL LAYOUT GUIDELINES

Follow these guidelines to obtain good signal integrity and avoid EMI:

1. Place components and route signals using the following design practices:
   • Keep analog and digital circuits in separate areas.
   • Identify all high-bandwidth signals and their return paths. Treat all critical signals as current loops. Check each critical loop area before the board is built. A small loop area is more important than short trace lengths.
   • Orient adjacent-layer traces so that they are perpendicular to one another to reduce crosstalk.
   • Keep critical traces on internal layers, where possible, to reduce emissions and improve immunity to external noise. However, RF traces should be routed on outside layers to avoid the use of vias on these traces.
   • Keep all trace lengths to a practical minimum. Keep traces, especially RF traces, straight wherever possible. Where turns are necessary, use curved traces or two 45-degree turns. Never use 90-degree turns.
2. Consider the following concerning ground and power supply planes:
   • Route all supply voltages to minimize capacitive coupling to other supplies. Capacitive coupling can occur if supply traces on adjacent layers overlap. Supplies should be separated from each other in the stack-up by a ground plane, or they should be coplanar (routed on different areas of the same layer).
   • Provide an effective ground plane. Keep ground impedance as low as possible. Provide as much ground plane as possible and avoid discontinuities. Use as many ground vias as possible to connect all ground layers together.
   • Maximize the width of power traces. Verify that they are wide enough to support target currents and that they can do so with margin. Verify that there are enough vias if the traces need to change layers.
3. Consider these power supply decoupling practices:
   • Place decoupling capacitors near target power pins. If possible, keep them on the same side as the IC they decouple to avoid vias that add inductance. If a filter component cannot be directly connected to a given power pin with a very short and fat etch, do not connect it by a copper trace. Instead, make the connection directly to the associated planes using vias.
   • Use appropriate capacitance values for the target circuit, and consider each capacitor’s self-resonant frequency.

Module stencil and Pad opening Suggestion

• Stencil thickness： 0.10~0.12mm

• Function Pad opening size suggestion: Max. 1:1
  PS: This opening suggestion just for customer reference, please discuss with AzureWave’s Engineer before you start SMT.

• Solder Printer Opening and Customer PCB Footprint suggestion.

• Example:

The other layout guide Information

• Make sure every power trace have a good return path (ground path).
• Connect the input pins of unused internal regulators to the ground.
• Leave the output pins of unused internal regulators floating.
• High-speed interface (i.e. UART/SDIO/HSIC) shall have equal electrical length. Keep them away from noise-sensitive blocks.
• Good power integrity of VDDIO will improve the signal integrity of digital interfaces.
• A good return path and well-shielded signal can reduce crosstalk, and EMI emission and improve signal integrity.
• RF IO is around 50 ohms, reserve Pi or T matching network to have better signal transition from port to port.
• Smooth RF trace help to reduce insertion loss. Do not use 90 90-degree turn (use two 45-degree turns or one mitre bend instead).
• Well-arranged ground plane near the antenna and the antenna itself will help to reduce near-field coupling between other RF sources (e.g. GSM/CDMA … antennas).
• Discuss with the AzureWave Engineer after you finish the schematic and layout job.

Mechanical Drawing

Package Outline Drawing

Top View of PCB Layout Foot Print

The information contained herein is the exclusive property of AzureWave and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of AzureWave.

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