PSoC 62S1 Wi-Fi BT Pioneer Kit

Product Information

Specifications

• Product Name: CYW9P62S1-43438EVB-01 PSoC 62S1 Wi-Fi BT Pioneer
  Kit

• Manufacturer: Cypress Semiconductor

• Model Number: CYW9P62S1-43438EVB-01

• Product Type: Development Kit

Introduction

The CYW9P62S1-43438EVB-01 PSoC 62S1 Wi-Fi BT Pioneer Kit is a
development kit provided by Cypress Semiconductor. It is designed
to enable users to evaluate and prototype applications using the
PSoC 62S1 Wi-Fi BT module.

Kit Operation

Board Details

The kit includes a board with various components and interfaces
for development purposes. Refer to the user manual for detailed
information on the board layout and components.

KitProg3: On-Board Programmer/Debugger

The kit features an on-board programmer/debugger called
KitProg3. It allows programming and debugging of the PSoC 62S1
Wi-Fi BT module. The user manual provides instructions on how to
use KitProg3 with ModusToolbox, as well as how to utilize the
USB-UART and USB-I2C bridges for communication.

Hardware

Schematics

The user manual includes schematics that provide detailed
information on the electrical connections and circuit design of the
board.

Hardware Functional Description

The user manual provides a functional description of the
hardware components and their interactions. This information helps
users understand the capabilities and limitations of the kit.

Safety and Regulatory Compliance Information

The PSoC 62S1 Wi-Fi BT Pioneer Boards contain electrostatic
discharge (ESD)-sensitive devices. To avoid performance degradation
or loss of functionality, it is recommended to follow proper ESD
precautions. Store unused boards in the protective shipping
package.

End-of-Life/Product Recycling

The end-of-life cycle for this kit is five years from the date
of manufacture. To discard the kit, contact your nearest recycler
for proper recycling.

General Safety Instructions

ESD Protection

ESD can damage boards and associated components. It is
recommended to perform procedures at an ESD workstation. If
unavailable, use appropriate ESD protection by wearing an
anti-static wrist strap attached to a grounded metal object.

Handling Boards

The CYW9P62S1-43438EVB-01 PSoC 62S1 Wi-Fi BT Pioneer Kit is
sensitive to ESD. When handling the board, hold it only by its
edges. After removing the board from its box, place it on a
grounded, static-free surface. If available, use a conductive foam
pad to prevent sliding the board over any surface.

FAQ

Q: What is the lifespan of the CYW9P62S1-43438EVB-01 PSoC 62S1

Wi-Fi BT Pioneer Kit?

A: The kit has a lifespan of five years from the date of
manufacture.

Q: How should I handle the board to prevent ESD damage?

A: Hold the board only by its edges and place it on a grounded,
static-free surface. It is recommended to use an anti-static wrist
strap attached to a grounded metal object for ESD protection.

CYW9P62S1-43438EVB-01
PSoC 62S1 Wi-Fi BT Pioneer Kit Guide
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Cypress Semiconductor 198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810 Phone (Intnl): +1.408.943.2600
www.cypress.com

Copyrights
Copyrights
© Cypress Semiconductor Corporation, 2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, FRAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

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Contents

Safety and Regulatory Compliance Information

4

1. Introduction

6

1.1 Kit Contents …………………………………………………………………………………………………..7 1.2 Getting Started……………………………………………………………………………………………….8 1.3 Board Overview ……………………………………………………………………………………………..8 1.4 Additional Learning Resources…………………………………………………………………………9 1.5 Technical Support…………………………………………………………………………………………..9 1.6 Documentation Conventions…………………………………………………………………………….9 1.7 Acronyms………………………………………………………………………………………………………9

2. Kit Operation

11

2.1 Board Details ……………………………………………………………………………………………….11 2.2 KitProg3: On- Board Programmer/Debugger……………………………………………………..21
2.2.1 Programming and Debugging using ModusToolbox ………………………………..21 2.2.2 USB- UART Bridge………………………………………………………………………………25 2.2.3 USB-I2C Bridge………………………………………………………………………………….26

3. Hardware

27

3.1 Schematics ………………………………………………………………………………………………….27 3.2 Hardware Functional Description…………………………………………………………………….27
3.2.1 CYW9P62S1-43438CAR-01 (MOD1) ……………………………………………………27 3.2.2 PSoC 5LP-based KitProg3 (U2)……………………………………………………………31 3.2.3 Serial Interconnection between PSoC 5LP and PSoC 6 MCU ………………….32 3.2.4 Serial Interconnection Between PSoC 5LP and CYW43438 …………………….33 3.2.5 Power Supply System …………………………………………………………………………33 3.2.6 I/O Headers……………………………………………………………………………………….37 3.2.7 CapSense Circuit ……………………………………………………………………………….38 3.2.8 LEDs ………………………………………………………………………………………………..39 3.2.9 Push Buttons……………………………………………………………………………………..40 3.2.10 Cypress Quad SPI NOR Flash……………………………………………………………..40 3.2.11 Cypress Quad SPI F-RAM …………………………………………………………………..41 3.2.12 PSoC 6 USB ……………………………………………………………………………………..42 3.2.13 Potentiometer…………………………………………………………………………………….42 3.3 PSoC 62S1 Wi-Fi BT Pioneer Kit Rework ………………………………………………………..43 3.3.1 ETM Trace Header……………………………………………………………………………..43 3.4 Bill of Materials …………………………………………………………………………………………….43 3.5 Frequently Asked Questions…………………………………………………………………………..44

Revision History

46

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Safety and Regulatory Compliance Information
The CYW9P62S1-43438EVB-01 PSoC® 62S1 Wi-Fi BT Pioneer Kit is intended for development purposes only. Users are advised to test and evaluate this kit in an RF development environment. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required authorizations are first obtained. Contact support@cypress.com for details. The CYW9P62S1-43438EVB-01, as shipped from the factory, has been verified to meet with the requirements of CE as a Class A product.
PSoC 62S1 Wi-Fi BT Pioneer Boards contain electrostatic discharge (ESD)- sensitive devices. Electrostatic charges readily accumulate on the human body and any equipment, which can cause a discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused PSoC 62S1 Wi-Fi BT Pioneer Boards in the protective shipping package.
End-of-Life/Product Recycling The end-of-life cycle for this kit is five years from the date of manufacture mentioned on the back of the box. Contact your nearest recycler to discard the kit.

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General Safety Instructions
ESD Protection
ESD can damage boards and associated components. Cypress recommends that you perform procedures only at an ESD workstation. If an ESD workstation is unavailable, use appropriate ESD protection by wearing an anti-static wrist strap attached to a grounded metal object.
Handling Boards
CYW9P62S1-43438EVB-01 PSoC 62S1 Wi-Fi BT Pioneer Kit is sensitive to ESD. Hold the board only by its edges. After removing the board from its box, place it on a grounded, static-free surface. Use a conductive foam pad, if available. Do not slide the board over any surface.

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1. Introduction
Thank you for your interest in the CYW9P62S1-43438EVB-01 PSoC 62S1 Wi-Fi BT Pioneer Kit. The PSoC 62S1 Wi-Fi BT Pioneer Kit enables you to evaluate and develop your applications using the PSoC 62 Series MCU (hereafter called “PSoC 6 MCU”) and CYW43438 Wi-Fi/BT combo device.
PSoC 6 MCU is Cypress’ latest, ultra-low-power PSoC specifically designed for wearables and IoT products. PSoC 6 MCU is a true programmable embedded system- on-chip, integrating a 150-MHz Arm® Cortex®-M4 as the primary application processor, a 100-MHz Arm Cortex-M0+ that supports low-power operations, up to 2 MB Flash and 1 MB SRAM, CapSense® touch-sensing, and programmable analog and digital peripherals that allow higher flexibility, in-field tuning of the design, and faster time-to-market. The PSoC 6 MCU on this kit, CY8C6247BZI-D54 has 1 MB Flash and 288 KB SRAM.
The PSoC 62S1 Wi-Fi BT Pioneer Board offers compatibility with ArduinoTM shields. The board features a PSoC 6 MCU, and a CYW43438 Wi-Fi/Bluetooth combo module. Cypress CYW43438 is a highly integrated single-chip solution and offers the lowest BOM in the industry for smartphones, tablets, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio, and Bluetooth 4.2. The WLAN section supports SDIO interface to the host MCU (PSoC 6 MCU), and the Bluetooth section supports high-speed 4-wire UART interface to the host MCU. In addition, the board features an onboard programmer/debugger (KitProg3), a 512Mbit Quad SPI NOR flash, a 4-Mbit Quad SPI F-RAM, a micro-B connector for USB device interface, a 5-segment CapSense slider, two CapSense buttons, an RGB LED, two user LEDs, one potentiometer, and two push buttons.
You can use ModusToolboxTM to develop and debug your PSoC 6 MCU projects. ModusToolbox software is a set of tools that enable you to integrate Cypress devices into your existing development methodology.
If you are new to PSoC 6 MCU and ModusToolbox IDE, refer to the application note AN228571 Getting Started with PSoC 6 MCU on ModusToolbox to help you familiarize with the PSoC 6 MCU and help you create your own design using the ModusToolbox IDE.

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Introduction

1.1

Kit Contents

The CYW9P62S1-43438EVB-01 PSoC 62S1 Wi-Fi BT Pioneer Kit has the following contents, as shown in Figure 1-1. PSoC 62S1 Wi-Fi BT Pioneer Board USB Type-A to Micro-B cable Four jumper wires (4 inches each) Two jumper wires (5 inches each) Quick Start Guide
Figure 1-1. Kit Contents

Inspect the contents of the kit; if you find any part missing, contact your nearest Cypress sales office for help: www.cypress.com/support.

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Introduction

1.2

Getting Started

This guide will help you get acquainted with the PSoC 62S1 Wi-Fi BT Pioneer Kit:
The Kit Operation chapter on page 11 describes the major features of the PSoC 62S1 Wi-Fi BT Pioneer Kit and functionalities such as programming, debugging, and the USB-UART and USBI2C bridges.
The Hardware chapter on page 27 provides a detailed hardware description, methods to use the onboard NOR flash, kit schematics, and the bill of materials (BOM).
Application development using PSoC 62S1 Wi-Fi BT Pioneer Kit is supported in various development ecosystems such as ModusToolbox and Mbed OS. For the latest software support for this development kit including the different development ecosystems, refer to the kit webpage.
ModusToolbox software is a free development ecosystem that includes the ModusToolbox IDE. Using ModusToolbox IDE, you can enable and configure device resources, middleware libraries, and program and debug the device. You can download the software from the ModusToolbox home page. See the ModusToolbox User Guide for additional information.
Mbed OS: Visit Cypress’ Mbed OS page on instructions to develop applications on Cypress’ target board on the Mbed OS platform.
There is a wide range of code examples to evaluate the PSoC 62S1 Wi-Fi BT Pioneer Board. These examples help you familiarize yourself with the PSoC 6 MCU and create your own design. These examples are available in various development ecosystems such as ModusToolbox IDE and Mbed OS. Visit Cypress’ code example page to access examples for the following development ecosystems:
ModusToolbox based examples
Mbed OS based examples

1.3

Board Overview

The PSoC 62S1 Wi-Fi BT Pioneer Board has the following features: CYW9P62S1-43438CAR-01 carrier module that contains AW-CU427-01H System in Package
(SiP) module by AzureWave, which has PSoC 6 MCU (CY8C6247BZI-D54) CYW43438KUBG, 2.4 GHz WLAN and Bluetooth 4.2 compliant device supporting Dual- mode
Bluetooth Classic and Bluetooth Low Energy (BT and BLE) operation 512-Mbit external Quad SPI NOR Flash that provides a fast, expandable memory for data and
code 4-Mbit Quad SPI ferroelectric random-access memory (F-RAM) KitProg3 onboard SWD programmer/debugger with USB-UART and USB-I2C bridge functionality CapSense touch-sensing slider (5 elements), two buttons, based on self- capacitance (CSD) and
mutual-capacitance (CSX) sensing A micro-B connector for USB device interface for PSoC 6 MCU 3.3 V operation of PSoC 6 MCU is supported Two user LEDs, an RGB LED, two user buttons, and a reset button for the PSoC 6 MCU A potentiometer One Mode selection button and one Status LED for KitProg3

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1.4 1.5 1.6
1.7

Introduction

Additional Learning Resources
Cypress provides a wealth of data at www.cypress.com/psoc6 to help you to select the right PSoC device for your design and to help you to quickly and effectively integrate the device into your design.

Technical Support
For assistance, visit Cypress Support or contact customer support at +1(800) 541-4736 Ext. 3 (in the USA) or +1 408-943-2600 Ext. 3 (International).
You can also use the following support resources if you need quick assistance: Self-help (Technical Documents). Local Sales Office Locations.

Documentation Conventions

Table 1-1. Document Conventions for Guides

Convention Courier New

Usage
Displays file locations, user entered text, and source code: C:…cdicc

Italics File > Open Bold Times New Roman Text in gray boxes

Displays file names and reference documentation: Read about the sourcefile.hex file in the PSoC Creator User Guide.
Represents menu paths: File > Open > New Project
Displays commands, menu paths, and icon names in procedures: Click the File icon and then click Open.
Displays an equation: 2 + 2 = 4
Describes cautions or unique functionality of the product.

Acronyms

Table 1-2. Acronyms Used in this Document

Acronym

ADC

Analog-to-Digital Converter

BLE

Bluetooth Low Energy

BOM

Bill of Materials

BT

Bluetooth

CINT

Integration Capacitor

CMOD

Modulator Capacitor

CPU

Central Processing Unit

CSD

CapSense Sigma Delta

CSX

CapSense Crosspoint

DC

Direct Current

Del-Sig

Delta-Sigma

Definition

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Table 1-2. Acronyms Used in this Document (continued)

Acronym

Definition

DMA

Direct Memory Access

ECO

External Crystal Oscillator

ESD

Electrostatic Discharge

GPIO

General-Purpose Input/Output

HID

Human Interface Device

I2C

Inter-Integrated Circuit

I2S

Inter-IC Sound

IC

Integrated Circuit

IDE

Integrated Development Environment

IoT

Internet of Things

LED

Light-emitting Diode

LPO

Low Power Oscillator

MAC

Medium Access Control

OOB

Out-of Box

PC

Personal Computer

PDM

Pulse Density Modulation

PSoC

Programmable System-on-Chip

PWM

Pulse Width Modulation

QSPI

Quad Serial Peripheral Interface

SAR

Successive Approximation Register

SDIO

Secure Digital Input Output

SiP

System in Package

SPI

Serial Peripheral Interface

SRAM

Serial Random Access Memory

SWD

Serial Wire Debug

UART

Universal Asynchronous Receiver Transmitter

USB

Universal Serial Bus

WCO

Watch Crystal Oscillator

WLAN

Wireless Local Area Network

Introduction

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2. Kit Operation

2.1

This chapter introduces you to various features of the PSoC 62S1 Wi-Fi BT Pioneer Board, including the theory of operation and the onboard KitProg3 programming and debugging functionality, USB-UART and USB-I2C bridges.

Board Details

The PSoC 62S1 Wi-Fi BT Pioneer Board is built around a PSoC 6 MCU. Figure 2-1 shows the block diagram of the PSoC 6 MCU device used on the board. For details of device features, see the device datasheet.
Figure 2-1. PSoC 6 MCU Block Diagram

Energy Profiler EFUSE (1024 bits) Serial Memory I/F (QSPI with OTF Encryption/Decryption))
USB-FS Host + Device

PSoC 62

System Resources
Power Sleep Control POR BOD OVP LVD
REF
PWRSYS-LP/ULP
Buck

Clock

Clock Control

ILO

WDT

IMO ECO

FLL

1xPLL

Reset Reset Control
XRES
Test TestMode Entry
Digital DFT Analog DFT

Backup

Backup Control

RTC

BREG WCO

Power Modes Active/Sleep
LowePowerActive/Sleep DeepSleep Hibernate Backup

CPU Subsystem
SWJ/ETM/ITM/CTI
Cortex M4 150 MHz (1.1V) 50 MHz (0.9V)
FPU, NVIC, MPU, BB 8KB Cache

FLASH 1024+32 KB
FLASH Controller

IOSS GPIO

PCLK

Programmable Analog

SAR ADC (12-bit)

DAC (12-bit)

x1

x1

SARMUX

CTB/CTBm 2x OpAmp x1

IO Subsystem

SRAM 9x 32 KB
SRAM Controller

ROM 128 KB
ROM Controller

SWJ/MTB/CTI
Cortex M0+ 100 MHz (1.1V) 25 MHz (0.9V)
MUL, NVIC, MPU 8KB Cache

DataWire/ DMA
2x 16 Ch
Initiator/MMIO

System Interconnect (Multi Layer AHB, MPU/SMPU, IPC)

Peripheral Interconnect (MMIO, PPU)

Programmable Digital
UDB … UDB

Audio Subsystem

x12

LP Comparator CapSense
32x TCPWM
(TIMER,CTR,QD, PWM)
8x Serial Comm
(I2C,SPI,UART,LIN,SMC)
1x Serial Comm
(I2C,SPI, Deep Sleep)
LCD I2S Master/Slave
PDM/PCM

Port Interface & Digital System Interconnect (DSI) High Speed I/O Matrix, Smart I/O, Boundary Scan 104 GPIOs (6 of these are OVT Pins)

CRYPTO
DES/TDES, AES,SHA,CRC, TRNG,RSA/ECC
Accelerator
Initiator/MMIO

FS/LS PHY

DMA MMIO

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Kit Operation

Figure 2-2 shows the block diagram of the CYW9-BASE-01 Pioneer Board (modified for CYW9P62S1-43438EVB-01). Figure 2-3 shows the block diagram of the CYW9P62S1-43438CAR01 Carrier Board.

Figure 2-2. Block Diagram of Pioneer Board (modified for CYW9P62S1-43438EVB-01)

CYW9-BASE-01 Architecture Block Diagram

KitProg3 Mode Switch & LED

10-pin SWD/ JTAG Header

20-pin ETM Header

Reset Button

VDDA

Potentiometer

Cypress Device No Load

P5LP_VDD

USB (Micro-B)
VTARG Monitoring

KitProg3 (PSoC 5LP)

1.8~3.3V VTARG_REF
SWD

SWD JTAG 1.8~3.3V
VTARG_REF

I2C/UART_RX/UART_TX

SWD JTAG TRACE

P5LP_VDD

Level Translator

VTARG UART_RTS UART_CTS

P5LP_VDD

Level Translator

VDDIO_WL
BT_UART TX, RX, CTS, RTS WL_UART TX, RX, KP_GPIO_0

I2C EEPROM
2 x CapSense Buttons, 1 x 5-segment CapSense Slider
USB Device & Host

VBACKUP VDDD
VDDIO0

2 x User Buttons
User LEDs (RGB, Red,
Orange)
QSPI NOR Flash

Carrier Module

VDDIO0

QSPI F-RAM

VDDIO0

microSD Card Slot

3.3V, VTARG KP_VBUS

PSoC 6 MCU I/O Headers
(Arduino)

I/O Headers (Non Arduino)

Loaded Device

Figure 2-3. Block Diagram of CYW9P62S1-43438CAR-01 Carrier Module

Carrier Module Footprint

PSoC 6 MCU GPIOs (66 I/Os)
XRES USB BT UART (4 I/Os)
Control (2 I/Os) WL GPIO (1 I/O) BT I2S (4 I/Os) SDIO (6 I/Os)
Note: Inside AZW module, SDIO interface is connected only to PSoC 6 MCU, not connected to carrier module footprint
VDDA (1.8V ­ 3.3V) VDDD (1.8V ­ 3.3V) VDDIO2 (1.8V) VDD_NS (1.8V ­ 3.3V) VBACKUP (1.8V ­ 3.3V) VDDUSB (2.7V – 3.3V)

AZW PCB Module

VBAT (3.2V ­ 4.2V) VDDIO_WL (1.8V)

Crystal 17.2032 MHz

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Kit Operation

Figure 2-4 shows the pinout of the PSoC 62S1 Wi-Fi BT Pioneer Board. Figure 2-4. PSoC 62S1 Wi-Fi BT Pioneer Board Pinout

NC VTARG/IOREF XRES/RESET
V 3.3/3.3V V 5.0/5V GND/GND GND/GND VIN/Vin

P10_0/A0 P10_1/A1 P10_2/A2 P10_3/A3 P10_4/A4 P10_5/A5 P10_6 NC
BT_UART_RXD BT_UART_TXD BT_UART_CTS BT_UART_RTS
NC NC NC WL_GPIO_2

P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 NC
BT_I2S_CLK BT_I2S_WS BT_I2S_DO BT_I2S_DI NC NC NC NC

LEGEND Arduino Uno R3 PSoC 6 I/Os WL/BT I/Os

P7_3 P0_5 P1_1

P6_0/SCL P6_1/SDA VREF/AREF GND/GND P12_2/D13 P12_1/D12 P12_0/D11 P12_3/D10 P7_4/D9 P7_5/D8
P1_4 P0_4 NC NC NC NC NC NC NC NC
NC P12_5 P12_4 P8_0 NC P1_3 P0_3 P0_2
P5_7/D7 P5_6/D6 P5_5/D5 P5_4/D4 P5_3/D3 P5_2/D2 P5_1/D1 P5_0/D0
NC P11_1 P1_5

Table 2-1. PSoC 62S1 Wi-Fi BT Pioneer Board Pinout

Pin

Primary On-board Secondary On-board

Function

Function

PSoC 6 MCU Pins

XRES

Hardware Reset

­

­

P0[2]

GPIO on non-Arduino header IO0 (J22.1)

­

­

P0[3]

GPIO on non-Arduino header IO1 (J22.2)

­

­

P0[4]

User button with Hibernate wakeup
capability

GPIO on non-Arduino header (J21.9)

­

P0[5]

RGB green LED (LED5)

GPIO on non-Arduino header (J24.3)

­

Connection details

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Kit Operation

Table 2-1. PSoC 62S1 Wi-Fi BT Pioneer Board Pinout (continued)

Pin

Primary On-board Secondary On-board

Function

Function

Connection details

P1[0]

CapSense RX for buttons and
CapSense TX for sliders

GPIO on non-Arduino Remove R33 to disconnect from CapSense.

header IO7 (J22.8)

Populate R145 to connect to GPIO on nonArduino header.

P1[1]

RGB red LED (LED5)

GPIO on non-Arduino header (J24.1)

­

P1[2]

USB Host Enable

­

­

P1[3]

GPIO on non-Arduino header J22.3

­

­

P1[4]

User button with Hibernate wakeup
capability

GPIO on non-Arduino header (J21.10)

­

P1[5]

Orange user LED (LED8)

GPIO on non-Arduino header (J24.2)

­

P5[0]

UART_RX

Arduino D0 (J4.1) Remove R21 to disconnect from KitProg3.

P5[1]

UART_TX

Arduino D1 (J4.2) Remove R61 to disconnect from KitProg3.

P5[2]

UART_RTS

Arduino D2 (J4.3) Remove R19 to disconnect from KitProg3.

P5[3]

UART_CTS

Arduino D3 (J4.4) Remove R18 to disconnect from KitProg3.

P5[4]

Arduino D4 (J4.5)

­

­

P5[5]

Arduino D5 (J4.6)

­

­

P5[6]

Arduino D6 (J4.7)

­

­

P5[7]

Arduino D7 (J4.8)

­

­

P6[0]

I2C SCL

Arduino (J3.10) Remove R58 to disconnect from KitProg3.

P6[1]

I2C SDA

Arduino (J3.9) Remove R59 to disconnect from KitProg3.

P6[2]

USB VBUS Detect

­

­

P6[3]

USB Interrupt

­

­

P6[4]

PSoC 6 MCU JTAG TDO/SWD SWO

­

­

P6[5]

PSoC 6 MCU JTAG TDI

­

­

P6[6]

PSoC 6 MCU JTAG TMS/SWD SWDIO

­

­

P6[7]

PSoC 6 MCU JTAG TCK/SWD SWCLK

­

­

P7[0]

ETM Clock

­

­

P7[1]

CapSense CINTA

­

­

P7[2]

CapSense CINTB

­

­

P7[3]

RGB blue LED (LED5)

GPIO on non-Arduino header (J24.5)

­

P7[4]

Arduino D9 (J3.2)

­

­

P7[5]

Arduino D8 (J3.1)

­

­

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Table 2-1. PSoC 62S1 Wi-Fi BT Pioneer Board Pinout (continued)

Pin

Primary On-board Secondary On-board

Function

Function

Connection details

P7[7]

CapSense CMOD

­

­

P8[0]

GPIO on non-Arduino header (J22.5)

­

­

P8[1]

CapSense Button0 TX

Remove R24 to disconnect from CapSense. GPIO on non-Arduino
header IO8 (J21.1) Populate R144 to connect to GPIO on nonArduino header.

P8[2]

CapSense Button1 TX

Remove R25 to disconnect from CapSense. GPIO on non-Arduino
header IO9 (J21.2) Populate R143 to connect to GPIO on nonArduino header.

P8[3]

CapSense Slider0 RX

GPIO on non-Arduino Remove R28 to disconnect from CapSense.

header IO10 (J21.3)

Populate R142 to connect to GPIO on nonArduino header.

P8[4]

CapSense Slider1 RX

GPIO on non-Arduino Remove R29 to disconnect from CapSense.

header IO11 (J21.4)

Populate R152 to connect to GPIO on nonArduino header.

P8[5]

CapSense Slider2 RX

GPIO on non-Arduino Remove R30 to disconnect from CapSense.

header IO12 (J21.5)

Populate R153 to connect to GPIO on nonArduino header.

P8[6]

CapSense Slider3 RX

Remove R31 to disconnect from CapSense. GPIO on non-Arduino header IO13 (J21.6) Populate R151 to connect to GPIO on non-
Arduino header.

P8[7]

CapSense Slider4 RX

Remove R32 to disconnect from CapSense.

GPIO on non-Arduino header IO14 (J21.7)

Populate R149 to connect to GPIO on non-

Arduino header.

P9[0]

Extended Arduino A8 (J2.2)

ETM TRACEDATA[3]

Remove R125 to disconnect from J2 header.
Populate R126 to connect to ETM Trace header.

P9[1]

Extended Arduino A9 (J2.4)

ETM TRACEDATA[2]

Remove R124 to disconnect from J2 header.
Populate R127 to connect to ETM Trace header.

P9[2]

Extended Arduino A10 (J2.6)

ETM TRACEDATA[1]

Remove R123 to disconnect from J2 header.
Populate R128 to connect to ETM Trace header.

P9[3]

Extended Arduino A11 (J2.8)

Remove R117 to disconnect from J2 header.
ETM TRACEDATA[0] Populate R129 to connect to ETM Trace header.

P9[4]

Extended Arduino A12 (J2.10)

­

­

P9[5]

Extended Arduino A13 (J2.12)

­

­

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Table 2-1. PSoC 62S1 Wi-Fi BT Pioneer Board Pinout (continued)

Pin

Primary On-board Secondary On-board

Function

Function

Connection details

P9[6]

Extended Arduino A14 (J2.14)

­

­

P10[0]

Arduino A0 (J2.1)

­

­

P10[1]

Arduino A1 (J2.3)

­

­

P10[2]

Arduino A2 (J2.5)

­

­

P10[3]

Arduino A3 (J2.7)

­

­

P10[4]

Arduino A4 (J2.9)

­

­

P10[5]

Arduino A5 (J2.11)

­

­

P10[6]

Potentiometer output

Extended Arduino A6 (J2.13)

Remove R51 to disconnect from potentiometer.

P11[0]

QSPI F-RAM CS

­

­

P11[1]

Red user LED (LED9)

GPIO on non-Arduino header (J24.4)

­

P11[2]

QSPI Flash CS

­

­

P11[3:6]

QSPI Flash IO[3:0]

­

­

P11[7]

QSPI Flash CLK

­

­

P12[0]

Arduino header D11 (J3.4)

­

­

P12[1]

Arduino header D12 (J3.5)

­

­

P12[2]

Arduino header D13 (J3.6)

­

­

P12[3]

Arduino header D10 (J3.3)

­

­

P12[4]

GPIO on non-Arduino header IO5 (J22.6)

­

­

P12[5]

GPIO on non-Arduino header IO6 (J22.7)

­

­

P12[6]

ECO Crystal XIN

­

­

P12[7]

ECO Crystal XOUT

­

­

CYW43438 Pins

UART interface with BT_UART_TXD Host MCU (PSoC 6
MCU)

­

­

UART interface with BT_UART_RXD Host MCU (PSoC 6
MCU)

­

­

UART interface with BT_UART_CTS Host MCU (PSoC 6
MCU)

­

­

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Table 2-1. PSoC 62S1 Wi-Fi BT Pioneer Board Pinout (continued)

Pin

Primary On-board Secondary On-board

Function

Function

UART interface with BT_UART_RTS Host MCU (PSoC 6
MCU)

­

­

BT_I2S_CLK

I2S serial clock

­

­

BT_I2S_WS I2S serial word select

­

­

BT_I2S_DO I2S serial data out

­

­

BT_I2S_DI

I2S serial data in

­

­

WL_GPIO_2 Programable GPIO

­

­

Connection details

The CYW9P62S1-43438EVB-01 PSoC 62S1 Wi-Fi BT Pioneer Kit comes with the PSoC 62S1 Wi-Fi BT Pioneer Board. Figure 2-5 and Figure 2-6 show the markup of the Pioneer Board.
Figure 2-5. PSoC 62S1 Wi-Fi BT Pioneer Board – Top View

34 33 16

28

28

32 16 31

30

27 29

1

28

27 2
26
25 24

3

23

4 22

5

21

20

6

19

18

7

8

9

10

9

11 12 13 14

15 16

17

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Figure 2-6. PSoC 62S1 Wi-Fi BT Pioneer Board – Bottom View

Kit Operation

The PSoC 62S1 Wi-Fi BT Pioneer Board has the following components:
1. Power LED (LED1): This Yellow LED indicates the status of power supplied to board.
2. KitProg3 USB connector (J6): The USB cable provided along with the PSoC 62S1 Wi-Fi BT Pioneer Board connects between this USB connector and the PC to use the KitProg3 onboard programmer and debugger and to provide power to the board.
3. PSoC 6 MCU VDD power selection jumper (J14): This jumper is used to select the PSoC 6 MCU VDD supply voltage between 1.8 V and 3.3 V. J14 is not loaded for this kit and R83 is loaded, due to which only 3.3 V operation is supported.
4. KitProg3 programming mode selection button (SW3): This button can be used to switch between various modes of operation of KitProg3 (CMSIS-DAP BULK, CMSIS-DAP HID or DAPLink modes). For more details, see the KitProg3 User Guide.
5. PSoC 6 MCU VDD current measurement jumper (J15): An ammeter can be connected to this jumper to measure the current consumed by the PSoC 6 MCU VDD power domain. Please refer to Power Supply System on page 33 for details on power domains that are monitored by current measurement jumpers.
6. PSoC 6 MCU VDDIO2 and CYW43438 VDDIO power selection jumper (J16): This jumper is used to select the PSoC 6 MCU VDDIO2 and CYW43438 VDDIO supply voltage between 1.8 V and 3.3 V. This is not loaded by default. This board supports operation of VDDIO at 1.8 V.
7. PSoC 6 MCU VDDIO0 current measurement jumper (J19): An ammeter can be connected to this jumper to measure the current consumed by the PSoC 6 MCU VDDIO0 power domain. This is not loaded by default. Before populating the jumper for making current measurements, ensure that R97 is removed.
8. External power supply VIN connector (J5): This connector connects an external DC power supply input to the onboard regulators.

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9. PSoC 6 MCU user buttons (SW2 and SW4): These buttons can be used to provide an input to the PSoC 6 MCU. Note that by default these buttons connect the PSoC 6 MCU pin to ground when pressed, so you need to configure the PSoC 6 MCU pin as a digital input with resistive pullup for detecting the button press. These buttons also provide a wake-up source from low-power modes of the device.
10. Potentiometer connection jumper (J25): This jumper connects the PSoC 6 MCU VDDA to the potentiometer.
11. Potentiometer (R1): This is a 10K potentiometer connected to PSoC 6 MCU pin P10[6]. It can be used to simulate a sensor output to the PSoC 6 MCU.
12. Arduino-compatible power header (J1): This header powers the Arduino shields. It also has a provision to power the kit though the VIN input.
13. PSoC 6 MCU reset button (SW1): This button is used to reset the PSoC 6 MCU. It connects the PSoC 6 MCU reset (XRES) pin to ground.
14. PSoC 6 MCU debug and trace header (J12): This header can be connected to an Embedded Trace Macrocell (ETM)-compatible programmer/debugger. This is not loaded by default.
15. PSoC 6 MCU program and debug header (J11): This 10-pin header allows you to program and debug the PSoC 6 MCU using an external programmer such as MiniProg4.
16. Arduino Uno R3-compatible I/O headers (J2, J3, and J4): These I/O headers bring out pins from the PSoC 6 MCU to interface with Arduino shields. Some of these pins are multiplexed with onboard peripherals and are not connected to the PSoC 6 MCU by default. For a detailed information on how to rework the kit to access these pins, see Table 2-1 on page 13.
17. CapSense slider (SLIDER) and buttons (BTN0 and BTN1): The CapSense touch- sensing slider and two buttons, all of which are capable of both self- capacitance (CSD) and mutualcapacitance (CSX) operation, allow you to evaluate Cypress’ fourth-generation CapSense technology. The slider and buttons have a 1-mm acrylic overlay for smooth touch sensing.
18. PSoC 6 MCU VDDIO2 current measurement jumper (J18): An ammeter can be connected to this jumper to measure the current consumed by the PSoC 6 MCU VDDIO2 power domain. This jumper is not loaded by default on the board. Before populating the jumper for current measurements, ensure that R94 is removed.
19. CYW43438 VDDIO current measurement jumper(J17): An ammeter can be connected to this jumper to measure the current consumed by the CYW43438 VDDIO power domain.
20. Cypress serial NOR flash memory (S25FL512S, U3): A S25HL512S NOR flash of 512-Mbit capacity is connected to the Quad SPI interface of the PSoC 6 MCU. The NOR device can be used for both data and code memory with execute-in-place (XIP) support and encryption.
21. AzureWave AW-CU427-01H SiP module: AW-CU427-01H is an SiP module that contains the PSoC 6 MCU (CY8C6247BZI-D54) and the CYW43438 (Wi-Fi + Bluetooth combo device). The CYW43438 includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio, and Bluetooth 4.2. In addition, it integrates a power amplifier (PA) that meets the output power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area.
22. Cypress PSoC 6 (1M) with CYW43438 AzureWave PCB MOD Carrier Module (CYW9P62S1-43438CAR-01, MOD1): This kit is designed to highlight the features of the PSoC 6 MCU on the CYW9P62S1-43438CAR-01. For details, see CYW9P62S1-43438CAR-01 (MOD1) on page 27. This kit is designed to highlight the features of the PSoC 6 MCU. For details on PSoC 6 MCU pin mapping, refer to Table 2-1 on page 13.
23. Wi-Fi/BT antenna: This is an onboard antenna connected to the Wi-Fi and Bluetooth module.

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24. Cypress Quad SPI Ferroelectric-RAM (CY15B104QSN, U4): The CY15B104QSN is a 4-Mbit nonvolatile memory employing an advanced ferroelectric process. F-RAM is nonvolatile and performs reads and writes similar to a RAM. It provides reliable data retention for 151 years and is connected to the Quad SPI interface of the PSoC 6 MCU.
25. CYW43438 VBAT current measurement jumper (J8): An ammeter can be connected to this jumper to measure the current consumed by the CYW43438 VBAT power domain.
26. CYW43438 VBAT power selection jumper (J9): This jumper is used to select the CYW43438 VBAT supply voltage between 1.8 V, 3.3 V and 3.6 V. This board supports VBAT voltages of 3.3 V and 3.6 V. VBAT is 3.3 V when the jumper is not inserted and 3.6 V when the jumper is inserted.
27. PSoC 6 MCU user LEDs (LED8 and LED9): These two user LEDs can operate at the entire operating voltage range of the PSoC 6 MCU. The LEDs are active LOW, so the pins must be driven to logic LOW to turn ON the LEDs.
28. PSoC 6 I/O header (J21, J22, J24): These headers provide connectivity to PSoC 6 MCU GPIOs that are not connected to the Arduino compatible headers. Some of these I/Os are also connected to on-board peripherals see Table 2-1 on page 13 for pin mapping.
29. RGB LED (LED5): This onboard RGB LED can be controlled by the PSoC 6 MCU. The LEDs are active LOW, so the pins must be driven to ground to turn ON the LEDs.
30. Wi-Fi/BT GPIO header (J23): This header brings out a few IOs of the CYW43438 for general purpose applications.
31. PSoC 6 USB device connector (J7): The USB cable provided with the PSoC 62S1 Wi-Fi BT Pioneer Kit can also be connected between this USB connector and the PC to use the PSoC 6 MCU USB device applications.
32. Optional USB Host power supply header (J10): This header provides an option to supply external power to the PSoC 6 USB when used as a USB Host. This is not loaded by default.
33. KitProg3 status LED (LED2): This Yellow LED indicates the status of KitProg3. For details on the KitProg3 status, see the KitProg3 User Guide.
34. KitProg3 (PSoC 5LP) programmer and debugger (CY8C5868LTI-LP039, U2): The PSoC 5LP device (CY8C5868LTI-LP039) serving as KitProg3, is a multi-functional system, which includes a SWD programmer, debugger, USB-I2C bridge and USB-UART bridge. For more details, see the KitProg3 User Guide.
See Hardware Functional Description on page 27 for details on various hardware blocks.

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2.2
2.2.1

KitProg3: On-Board Programmer/Debugger
The PSoC 62S1 Wi-Fi BT Pioneer Board can be programmed and debugged using the onboard KitProg3. KitProg3 is an onboard programmer/debugger with additional USB-UART and USB-I2C functionality. A Cypress PSoC 5LP device is used to implement the KitProg3. For more details on the KitProg3 functionality, see the KitProg3 User Guide.
Programming and Debugging using ModusToolbox
This section presents a quick overview of programming and debugging using ModusToolbox. For detailed instructions, see Help > ModusToolbox IDE Documentation > User Guide. 1. Connect the board to the PC using the USB cable, as shown in Figure 2-7. It enumerates as a
USB Composite Device. KitProg3 can operate either in CMSIS-DAP Bulk mode (default), CMSIS-DAP HID mode or DAPLink mode (DAPLink mode is required for programing using Mbed CLI). KitProg3 also supports CMSIS-DAP Bulk with two UARTs. Programming is faster with the Bulk mode. The status LED (Yellow) is always ON in Bulk mode, ramping at a 1 Hz rate in HID mode, and ramping at a 2 Hz rate in DAPLink mode. Press and release the Mode select button (SW3) to switch between these modes. If you do not see the desired LED status, see the KitProg3 User Guide for details on the KitProg3 status and troubleshooting instructions.
Figure 2-7. Connect USB Cable to USB Connector on the Board

2. In the ModusToolbox IDE, import the desired code example (application) into a new workspace. a. Click on New Application from Quick Panel.
Figure 2-8. Create New Application

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Kit Operation b. Select the CYW9P62S1-43438EVB-01 in the Choose Board Support Package (BSP)
window and click Next, as shown in Figure 2-9. Figure 2-9. New Application Creation: Choose Board Support Package (BSP)
c. Select the application in the Choose Starter Application window and click Next, as shown in Figure 2-10. You may optionally change the application name in this window before clicking Next.
Figure 2-10. New Application Creation: Choose Starter Application
d. Click Finish in the Summary window, as shown in Figure 2-11. Figure 2-11. New Application Creation: Summary

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Kit Operation 3. To build and program a PSoC 6 MCU application, in the Project Explorer, select
project. In the Quick Panel, scroll to the Launches section and click the