NXP LPC55S1x Development Board Instructions

: June 4, 2024
: NXP

Table of Contents

**Document information
Product identification
Errata overview
Functional problems detail
AC/DC deviations detail
Documents / Resources

LPC55S1x/LPC551x Board
Instructions

**Document information

**

Info	Content
Keywords	LPC55S16JBD100, LPC55S16JEV98, LPC55S16JBD64,

LPC55S14JBD100, LPC55S14JBD64, LPC5516JBD100,
LPC5516JEV98, LPC5516JBD64, LPC5514JBD100, LPC5514JBD64,
LPC5512JBD100, LPC5512JBD64
Abstract| LPC55S1x/LPC551x errata

NXP Semiconductors
Revision history

Rev	Date	Description
1.6	20211028	Added CAN-FD.1 note in Section 3.9 “CAN-FD.1: Bus transaction

abort could occur when CAN-FD peripheral is using secure alias.”.
1.5| 20210810| Added VBAT_DCDC.1: Section 3.8 “VBAT_DCDC.1: The minimum rise time of the power supply must be 2.6 ms or slower for Tamb = -40 C, and 0.5 ms or slower for Tamb = 0 C to +105 C”
1.4| 20210423| Added USB.5, Section 3.6 “USB.5: In USB high-speed device mode, when device isochronous IN endpoint sends a packet of MaxPacketSize of 1024 bytes in response to IN token from host, the isochronous IN endpoint interrupt is not set and the endpoint command/status list entry for the isochronous IN endpoint is not updated”. Added USB.6, Section 3.7 “USB.6: In USB high-speed host mode, only one transaction per micro-frame is allowed for isochronous IN endpoints”.
1.3| 20210225| Added USB.4, Section 3.5 “USB.4: In USB high-speed device mode, the device writes extra byte(s) to the buffer if the NBytes is not multiple of 8 for OUT transfer”.Corrected Typo, Revision identifier as A for USB.3 in Table 1.
1.2| 20201214| Includes Section 3.4 “USB.3: For the USB high-speed device controller, the detection handshaking fails when certain full-speed hubs are connected”.
1.1| 20200827| Adds Section 5.1 “CAN-FD peripheral cannot access secure alias address”.
1.0| 20191204| Initial version.

Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

Product identification

The LPC55S1x/LPC55 1x VFBGA98 package has the following top-side marking:

First line: LPC55S1x/LPC551x
Second line: JEV98
Third line: xxxxxxxx
Fourth line: zzzyywwxR
– yyww: Date code with yy = year and ww = week.
– xR: Device revision A

The LPC55S1x/LPC551x HLQFP100 package has the following top-side marking:

First line: LPC55S1x/LPC551x
Second line: xxxxxxxx
Third line: zzzyywwxR
– yyww: Date code with yy = year and ww = week.
– xR: Device revision A

The LPC55S1x/LPC551x HTQFP64 package has the following top-side marking:

First line: LPC55S1x/LPC551x
Second line: JBD64
Third line: xxxx
Fourth line: xxxx
Fifth line: zzzyywwxR
– yyww: Date code with yy = year and ww = week.
– xR: Device revision A

Errata overview

Functional problems table

Functional problems| Short description| Revision identifier| Detailed description
---|---|---|---
ROM.1| ROM fails to enter ISP mode when image is corrupted with flash pages in an erased or unprogrammed state.| A| Section 3.1
USB.1| USB HS host fails when connecting to an LS device (mouse).| A| Section 3.2
USB.2| Automatic USB rate adjustment not functional when using multiple hubs.| A| Section 3.3
USB.3| For the USB high-speed device controller, the detection handshaking fails when certain full-speed hubs are connected.| A| Section 3.4
USB.4| In USB high-speed device mode, device writes extra byte(s) to the buffer if the NBytes is not multiple of 8 for OUT transfer.| A| Section 3.5

Functional problems table

problems| Short description| Revision identifier| Detailed description
---|---|---|---
USB.5| In USB high-speed device mode, when device| A| Section 3.6
USB.6| In USB high-speed host mode, only one transaction per| A| Section 3.7
VBAT_DCDC.1| The minimum rise time of the power supply must be 2.6| A| Section 3.8
CAN-FD.1| Bus transaction abort could occur when CAN-FD| A| Section 3.9

AC/DC deviations table

AC/DC deviations| Short description| Product version(s)| Detailed description
---|---|---|---
n/a| n/a| n/a| n/a

Functional problems detail

3.1 ROM.1: ROM fails to enter ISP mode when the image is corrupted with flash pages in an erased or unprogrammed state
Introduction
On the LPC55S1x/LPC551x, if the image is corrupted with flash pages in an erased or unprogrammed state, the ROM may fail to automatically enter ISP mode.
Problem
When secure boot is enabled in CMPA, and the flash memory contains an erased or unprogrammed memory page inside the memory region specified by the image size field in the image header, the device does not automatically enter into ISP mode using the fallback mechanism, as in the case of a failed boot for an invalid image. This problem occurs when the application image is only partially written or erased but a valid image header is still present in memory.
Work-around
Perform a mass-erase to remove the incomplete and corrupted image using one of the following methods:

Execute the erase command using Debug Mailbox. The device will enter directly into ISP mode after exiting the mailbox.
Enter into ISP mode using the Debug Mailbox command and use the flash-erase command.
Reset the device and enter into ISP mode using the ISP pin. Use the flash-erase command to erase the corrupted (incomplete) image.

3.2 USB.1: HS host fails when connecting with the LS device (mouse)
Introduction
The USB1 high-speed controller is available on select LPC55S1x/LPC551x devices and provides a plug-and-play connection of peripheral devices to a host with three different data speeds:

high-speed with a data rate of 480Mbps.
full-speed with a data rate of 12 Mbps.
low-speed with a data rate of 1.5 Mbps.

Many portable devices can benefit from the ability to communicate with each other over the USB interface without the intervention of a host PC. Problem USB HS host fails when connecting with an LS device (mouse).
Work-around
To support Full-Speed and Low-Speed applications, it is recommended to use the USB0 Full-Speed port and the USB1 High-speed port for the Device or Host. In addition, should an application require support of Low-Speed USB devices with a USB High-Speed Host, this can be accomplished by inserting a USB Hub between the USB1 High-speed port and external USB devices.
3.3 USB. 2: Automatic USB rate adjustment is not functional when using multiple hubs
Introduction:
Full-speed and low-speed signaling use bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit of stuffing error has occurred, and the packet should be ignored. The time interval just before an End of Packet (EOP) is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as a dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit of stuff. Therefore, the receiver must accept a packet where there are up to six full bit times at the port with no transitions prior to the EOP.
Problem:
The LPC55S1x/LPC551x devices use the start of an EOP for frequency measurements. This is not functional when going through multiple hubs that introduce a dribble bit because of hub switching skews. For this reason, the start of the EOP cannot be used for frequency measurements for automatic USB rate adjustment (by setting USBCLKADJ in the FRO192M_CTRL register). The problem does not occur when a single hub is used.
Work-around:
Use the FRO calibration library provided in technical note TNxxxxx. This library allows the application to have a crystal-less USB device operation in full-speed mode.
3.4 USB.3: For the USB high-speed device controller, the detection handshaking fails when certain full-speed hubs are connected
Introduction
See the USB2.0 specification for details regarding the USB High-speed Detection Handshake protocol.
Problem
As a high-speed device, when certain full-speed hubs are connected, the USB device does not detect the HOST KJ sequence correctly and, as a result, does not recognize the speed of the connected host. In this case, the USB device can act erratically due to the wrong speed detection.
Work-around
There are two workarounds:

The software workaround below can be implemented in usb_dev_hid_mouse where API is called “USB_DeviceHsPhyChirpIssueWorkaround()”. An event handler in USB_DeviceCallback(),
– On “kUSB_DeviceEventBusReset” event, USB_DeviceHsPhyChirpIssueWorkaround() should be called to identify the speed of the host connected. If the full- speed host is connected or “isConnectedToFsHostFlag” is set, FORCE_FS (bit 21) of the DEVCMDSTAT register should be set to force the device to operate in full-speed mode.
– On the “kUSB_DeviceEventDetach” event, FORCE_FS (bit 21) of DEVCMDSTAT the register should be cleared.
The software workaround below is available in tech note (TN00071) In the event handler in USB_DeviceCallback(),
– On the “kUSB_DeviceEventAttach” event, set PHY_RX register trip-level voltage to the highest. USB PHY->RX &= ~(USBPHY_RX_ENVADJ_MASK);USBPHY->RX |= 2;.
– On the “kUSB_DeviceEventBusReset” event, check the DEVCMDSTAT[SPEED] to determine the connected bus speed. (SPEED are bits 22 and 23). If DEVCMDSTAT[SPEED]=FS, FORCE_FS (bit 21) of DEVCMDSTAT should be set to force the device to operate in full-speed mode.
– On the “kUSB_DeviceEventGetDeviceDescriptor” event, or the first SETUP packet has arrived, Set the USBPHY_RX[ENVADJ] field back to default 0. Otherwise, USBPHY_RX[ENVADJ] field will remains as 2 unless a disconnect event occurs.
– On “kUSB_DeviceEventDetach” event, Clear FORCE_FS (bit 21) of DEVCMDSTAT register to zero. Reset USBPHY_RX[ENVADJ] field back to default 0.

3.5 USB.4: In USB high-speed device mode, the device writes extra byte(s) to the buffer if the NBytes is not multiple of 8 for OUT transfer
Introduction
The LPC55S1x/LPC551x device family includes a USB high-speed interface (USB1) that can operate in device mode at high-speed. The bytes value represents the number of bytes that can be received in the buffer.
Problem
The LPC55S1x/LPC551x USB device controller writes extra bytes to the receive data buffer if the size of the transfer is not a multiple of 8 bytes since the USB device controller always writes 8 bytes. For example, if the transfer length is 1 byte, 7 extra bytes will be written to the receive data buffer. If the transfer length is 7 bytes, 1 extra byte will be written to the receive data buffer.
Work-around
Reserve an additional, intermediary buffer along with the buffer used by the application for USB data. After the USB data transfer into the intermediary buffer has been completed, use memcpy to move the data from the intermediary buffer into the application buffer, skipping the extraneous extra byte. This software workaround is implemented on the
3.6 USB.5: In USB high-speed device mode, when the device isochronous IN the endpoint sends a packet of MaxPacketSize of 1024 bytes in response to IN token from host, the isochronous IN endpoint interrupt is not set and the endpoint command/status list entry for the isochronous IN endpoint is not updated
Introduction
The LPC55S1x/LPC551x device family includes a USB high-speed interface (USB1) that can operate in device mode at high-speed. The isochronous IN endpoint supports a MaxPacketSize of 1024 bytes.
Problem
When the device isochronous IN endpoint sends a packet of MaxPacketSize of 1024 bytes in response to IN token from host, the isochronous IN endpoint interrupt is not set and the endpoint command/status list entry for the isochronous IN endpoint is not updated.
Work-around
Restrict the isochronous IN endpoint MaxPacketSize to 1023 bytes in the device descriptor.
3.7 USB.6: In USB high-speed host mode, only one transaction per micro- frame is allowed for isochronous IN endpoints
Introduction
The LPC55S1x/LPC551x device family includes a USB high-speed interface that can operate in host mode. Up to three high-speed transactions are allowed in a single micro-frame to support high-bandwidth endpoints. This mode is enabled by setting the Mult (Multiple) fields in the Proprietary Transfer Descriptor (PTD) and is used to indicate to the host controller the number of transactions that should be executed per micro-frame. The allowed bit settings are:
00b Reserved. A zero in this field yields undefined results.
01b One transaction to be issued for this endpoint per micro-frame.
10b Two transactions to be issued for this endpoint per micro-frame.
11b Three transactions are to be issued for this endpoint per micro-frame.
Problem
For High-bandwidth mode, using multiple packets (MULT = 10b or 11b) in a frame causes unreliable operation. Only one transaction (MULT = 01b) can be issued per micro-frame.
Work-around
There is no software workaround. Only one transaction can be issued per micro- frame.
3.8 VBAT_DCDC.1: The minimum rise time of the power supply must be 2.6 ms or slower for Tamb = -40 C, and 0.5 ms or slower for Tamb = 0 C to +105 C
Introduction
The datasheet specifies no power-up requirements for the power supply on the VBAT_DCDC pin.
Problem
The device might not always start-up if the minimum rise time of the power supply ramp is 2.6 ms or faster for Tamb = -40 C, and 0.5 ms or faster for Tamb = 0 C to +105 C.
Work-around
None.
3.9 CAN-FD.1: Bus transaction abort could occur when CAN-FD peripheral is using secure alias.
Introduction
Unlike CM33, for other AHB masters (CAN-FD, USB-FS, DMA), the security level of the transaction is fixed based on the level assigned for the master in SEC_AHB->MASTER_SEC_LEVEL register. So, if the application needs to restrict the CAN-FD to secure, the following steps are required:
– Set the security level of CAN-FD to secure-user (0x2) or secure privilege (0x3) in SEC_AHB->MASTER_SEC_LEVEL register.
– Assign secure-user or secure-privilege level for CAN-FD register space in SEC_AHB-> SEC_CTRL_AHB_PORT8_SLAVE1 Register.
– Assign secure-user or secure-privilege level for message RAM.
Example: If 16KB of SRAM 2 (0x2000_C000) bank is used for CAN message RAM. Then set rules in SEC_AHB-> SEC_CTRL_RAM2_MEM_RULE0 register to secure- user (0x2) or secure privilege (0x3).
Problem
The shared memory used by the CAN-FD controller and CPU should be accessible using secure alias with address bit 28 set (example 0x3000_C000). However, when CAN-FD makes a bus transaction using secure alias (address bit 28 set), the transaction is aborted.
Work-around
– When the CPU is accessing the CAN-FD register or message RAM it should always use secure alias i.e., 0x3000_C000 for message RAM manipulation.
– For any structure the CAN-FD peripheral uses to fetch or write, memory should be set to use 0x2000_C000 in order for bus transactions to work. CAN-FD software driver should set “Message RAM base address register (MRBA, offset 0x200)” with the physical address of RAM instead of secure alias.

AC/DC deviations detail

Errata notes detail

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Document identifier: LPC55S1x/LPC551x