3PEAK TPV706 Low Voltage Supervisory Circuits with Power Fail Detector Owner’s Manual
- September 17, 2024
- 3PEAK
Table of Contents
- Features
- Applications
- Description
- Typical Application Circuit
- Product Family Table
- Revision History
- Pin Configuration and Functions
- Specifications
- Detailed Description
- Application and Implementation
- Tape and Reel Information
- Package Outline Dimensions
- Order Information
- IMPORTANT NOTICE AND DISCLAIMER
- References
- Read User Manual Online (PDF format)
- Download This Manual (PDF format)
TPV706
Low-Voltage Supervisory Circuits
with Power-Fail Detector
Features
- Precision Low-Voltage Monitoring and Power-Fail Detector
- 200-ms (typical) Reset Timeout
- Manual Reset Input
- Independent Watchdog Timer
- Reset Output Stage
- Push-pull Active-low Output (TPV706)
- Low Power Consumption: 4-μA
- Guaranteed Reset Output Valid to VCC = 1 V
- Power Supply Glitch Immunity
- Temperature Range: −40°C to 125°C
- SOP8 Package
Applications
- Microprocessor Systems
- Computers
- Controllers
- Intelligent Instruments
- Portable Equipment
Description
The TPV706 is a supervisory circuit to monitor power supply voltage levels and
provides a power-on reset signal.
A watchdog monitor is provided, which is activated if the watchdog input
doesn’t toggle within 1.6 sec.
A reset signal can be asserted by an external manual reset input.
In addition, there is a power-fail detector with a 1.25-V threshold, which can
be used to monitor an additional power supply.
The reset periods are fixed at 200-ms (typical). The TPV706 is available in an
8-pin SOP package and typically consumes only 4-μA, which is suitable for low-
power and portable applications.
Typical Application Circuit
Product Family Table
Order Number| Threshold Voltage (V TH )| Package
Marking| Package
---|---|---|---
TPV706VL1-SR (1)| 1.58| V6V| SOP8
TPV706WL1-SR (1)| 1.67| V6W| SOP8
TPV706YL1-SR (1)| 2.19| V6Y| SOP8
TPV706ZL1-SR (1)| 2.32| V6Z| SOP8
TPV706RL1-SR| 2.63| V6R| SOP8
TPV706SL1-SR| 2.93| V6S| SOP8
TPV706TL1-SR| 3.08| V6T| SOP8
TPV706ML1-SR| 4.38| V6M| SOP8
TPV706LL1-SR| 4.63| V6L| SOP8
(1) For future products, contact the 3PEAK factory for more information and samples.
Revision History
Date | Revision | Notes |
---|---|---|
2019-01-01 | Rev.A.1 | Initial version. |
2019-05-28 | Rev.A.2 | Added WDI pulse interval spec. |
**** 2022-06-25 | **** Rev.A.3 | Updated note for MR input pulse width, update |
to latest datasheet format and add WDI to /WDO time information.
2022-08-29| Rev.A.4| Added WDI pulse interval spec.
2023-08-15| Rev.A.5| Added package tape and reel information, and updated
datasheet format.
2024-07-09| Rev.A.6| Corrected typo in order information, corrected typo in
typical application circuit.
Pin Configuration and Functions
Table 1. Pin Functions: TPV706
Pin | **I/O** | **Description** |
---|---|---|
No. | Name | |
**** 1 | **** MR | **** I |
features an internal pull-up current.
2| VCC| P| Power supply voltage being monitored.
3| GND| G| Ground. This pin should be connected to ground reference.
4| PFI| I| Power fail input. When PFI is less than 1.25-V,
PFO goes low. If unused, connect PFI to GND.
5| PFO| O| Power fail output. It goes low when PFI is less
than 1.25-V, otherwise stays high.
6| WDI| **** I| Watchdog Input. Generates a reset if the
voltage on the pin remains low or high for the duration of the watchdog
timeout. The timer is cleared if a logic transition occurs on this pin or if a
reset is generated. Floating WDI disables the watchdog function.
7| RESET| O| Active-Low Reset Push-Pull Output Stage.
Asserted whenever VCC is below the reset threshold or by a low signal on the
MR input. It remains low for 200-ms after VCC goes above the reset threshold
or MR goes from low to high. A watchdog timeout does not trigger RESET.
8| WDO| O| Watchdog Output. Pulls low if WDI remains low or
high for the duration of the watchdog timeout, and does not go high again
until the watchdog is cleared. Whenever VCC is below the reset threshold, WDO
stays low. As soon as VCC rises above the reset threshold, WDO goes high with
no delay.
Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Unit |
---|---|---|---|
VCC | Power Supply | −0.3 | 6 |
Output Current | 20 | mA | |
TJ | Maximum Junction Temperature | 150 | |
TA | Operating Temperature Range | −40 | 125 |
TSTG | Storage Temperature Range | −65 | 150 |
TL | Lead Temperature (Soldering 10 sec) | 260 |
- Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
- This data was taken with the JEDEC low effective thermal conductivity test board.
- This data was taken with the JEDEC standard multilayer test boards.
ESD, Electrostatic Discharge Protection
Parameter | Condition | Minimum Level | Unit |
---|---|---|---|
HBM | Human Body Model ESD | ANSI/ESDA/JEDEC JS-001 (1) | 4 |
CDM | Charged Device Model ESD | ANSI/ESDA/JEDEC JS-002 (2) | 2 |
- JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
- JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Thermal Information
Package Type | θ JA | θ JC | Unit |
---|---|---|---|
SOP8 | 143 | 60 | °C/W |
Electrical Characteristics
All test conditions: VCC = 1.53 V to 5.5 V, TA = −40°C to 125°C, unless
otherwise noted.
Parameter | Conditions | Min | Typ | Max | Unit |
---|
Supply Voltage and Current
VCC| Operating Supply Voltage| | 1| | 5.5| V
ICC| Supply Current| WDI and MR unconnected (VCC = 1.8 V)| | 4| 15| μA
WDI and MR unconnected (VCC = 5 V)| | 6| 20| μA
VTH| Reset Threshold Voltage| TPV706V| 1.51| 1.58| 1.63| V
TPV706W| 1.62| 1.67| 1.71| V
TPV706Y| 2.12| 2.19| 2.25| V
TPV706Z| 2.25| 2.32| 2.38| V
TPV706R| 2.55| 2.63| 2.70| V
TPV706S| 2.82| 2.93| 3.00| V
TPV706T| 3.00| 3.08| 3.15| V
TPV706M| 4.25| 4.38| 4.5| V
TPV706L| 4.5| 4.63| 4.75| V
| Reset Threshold Temperature Coefficient| | | 80| | ppm/°C
VHYS| Reset Threshold Hysteresis| | | 2 × __V TH 1000| | mV
tRD| VCC to Reset Delay| | | 20| | μs
tRP| Reset Timeout Period| | 140| 200| 280| ms
VOL| Reset Output Voltage Low (Push- Pull)| VCC ≥ 1 V, ISINK = 50 μA| | | 0.3|
V
ISINK = 1.2 mA @ Vcc ≥ 2 V| | | 0.4| V
VOH| Reset Output Voltage High (Push-Pull)| ISOURCE = 800 μA, @ VCC≥ 5 V| 0.7
× VCC| | | V
MR Pin
VIL_MR| MR Input Threshold VIL| | | | 0.3 × VCC| V
VIH_MR| MR Input Threshold VIH| | 0.7 × VCC| | | V
tPW_MR| MR Input Pulse Width (1)| | 6| | | μs
tGR_MR| MR Glitch Rejection| | | 100| | ns
td_MR| MR to Reset Delay| | | 1| 6| μs
IMR_V0| MR Pull-up Current| VCC = 3V| | 80| | μA
tWD| Watchdog Timeout Period| | 1| 1.6| 2.4| sec
Parameter| Conditions| Min| Typ| Max| Unit
---|---|---|---|---|---
tPW_WD| WDI Pulse Width 50 ns| | 50| | | ns
Parameter| Conditions| Min| Typ| Max| Unit
VIL_WDI| WDI input threshold VIL| | | | 0.3 × VCC| V
VIH_WDI| WDI input threshold VIH| | 0.7 × VCC| | | V
IWDI| WDI input current| VWDI = VCC| | 20| | μA
VWDI = 0| | -15| | μA
VOL_WDO| WDO VOL| ISINK = 1.2 mA @ VCC ≥ 5 V| | | 0.4| V
VOH_WDO| WDO VOH| ISOURCE = 800 μA @ Vcc≥ 5 V| 0.7 x VCC| | | V
PFI and PFO
VTH_PFI| Power fail input threshold| PFI falling| 1.18| 1.25| 1.32| V
VOL_PFO| PFO VOL| ISINK = 1.6 mA @ VCC ≥ 5 V| | | 0.4| V
VOH_PFO| PFO VOH| ISOURCE = 800 μA @ VCC ≥ 5 V| 0.7 x VCC| | | V
(1) MR pulse width given by customer in application should be longer than minimum value of MR input pulse width requirement.
Typical Performance Characteristics
All test conditions: VCC = 5 V, TA = + 25°C, unless otherwise noted.
Detailed Description
Overview
The TPV706 provides supply voltage supervision, watchdog function, manual
reset function, as well as a 1.25-V power-fail comparator.
Functional Block Diagram
Feature Description
RESET Output
The TPV706 features an active-low push-pull output. The reset signal is
guaranteed to be logic low for VCC down to 1-V. The reset output is asserted
when VCC is below the reset threshold (VTH), or when MR is driven low. Reset
remains asserted for the duration of the reset active timeout period (tRP)
after VCC rises above the reset threshold, or after MR transitions from low to
high. Figure 13 shows the reset (active low) outputs.
Manual RESET Input
The TPV706 features a manual reset input (MR), which, when driven low, asserts
the reset output. When MR transitions from low to high, reset remains asserted
for the duration of the reset active timeout period before de-asserting.
The MR input has an internal pull-up current so that the input is always high
when unconnected. Noise immunity is provided on the MR input, and the fast and
negative-going transients are ignored. A 0.1-μF capacitor between MR and
ground provides additional noise immunity.
Watchdog Input
The TPV706 features a watchdog timer, which monitors microprocessor activity.
A timer circuit is cleared with every low-tohigh or high-to-low logic
transition on the watchdog input pin (WDI). If the timer counts through the
preset watchdog timeout period (tWD), the watchdog output (WDO) goes low, a
low to high or high to low transition on the WDI pin clears the watchdog
timer. The delay time from WDI toggling to WDO going high is within 35-ms. The
microprocessor is required to toggle the WDI pin to avoid being reset.
Whenever VCC is below the reset threshold, WDO stays low. As soon as VCC rises
above the reset threshold, WDO goes high with no delay. Figure 14 shows the
watchdog timing.
Power-Fail Detector
The power-fail detector is a 1.25-V comparator, which can monitor an external
power supply through a resistive divider. When the voltage on the PFI is lower
than 1.25-V, the comparator output goes low, indicating a power fail, which
can be used as an early warning of the power fail.
Application and Implementation
Note
Information in the following application sections is not part of the 3PEAK’s
component specification and 3PEAK does not warrant its accuracy or
completeness. 3PEAK’s customers are responsible for determining suitability of
components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
Application Information
Figure 15 shows the typical application circuit of TPV706. Microprocessor
activity is monitored using WDI. When the WDI remains low or high for the
duration of the watchdog timeout, the WDO will trigger a manual reset to MCU.
The MCU can drive the MR from high to low and trigger the RESET.
Tape and Reel Information
Order Number| Package| Di (mm)| WI (mm)| AO (mm)| BO (mm)| KO (mm)| PO (mm)|
WO (mm)| Pint Quadrant
---|---|---|---|---|---|---|---|---|---
TPV706xx-SR| SOPS| 330| 18.| 7.| 5.| 2| 8| 12| 1
Package Outline Dimensions
SOP8
Package Outline Dimensions SO1(SOP08-A)
Order Information
**Order Number| Operating Temperature Range| ****Package|
****Marking Information| ****MSL| ****Transport Media, Quantity|
****Eco Plan**
---|---|---|---|---|---|---
TPV706VL1-SR (1)| −40 to 125°C| SOP8| V6V| 1| Tape and Reel, 4000| Green
TPV706WL1-SR (1)| −40 to 125°C| SOP8| V6W| 1| Tape and Reel, 4000| Green
TPV706YL1-SR (1)| −40 to 125°C| SOP8| V6Y| 1| Tape and Reel, 4000| Green
TPV706ZL1-SR (1)| −40 to 125°C| SOP8| V6Z| 1| Tape and Reel, 4000| Green
TPV706RL1-SR| −40 to 125°C| SOP8| V6R| 1| Tape and Reel, 4000| Green
TPV706SL1-SR| −40 to 125°C| SOP8| V6S| 1| Tape and Reel, 4000| Green
TPV706TL1-SR| −40 to 125°C| SOP8| V6T| 1| Tape and Reel, 4000| Green
TPV706ML1-SR| −40 to 125°C| SOP8| V6M| 1| Tape and Reel, 4000| Green
TPV706LL1-SR| −40 to 125°C| SOP8| V6L| 1| Tape and Reel, 4000| Green
(1) For future products, contact the 3PEAK factory for more information and
samples.
Green: 3PEAK defines “Green” to mean RoHS compatible and free of halogen
substances.
IMPORTANT NOTICE AND DISCLAIMER
Copyright© 3PEAK 2012-2024. All rights reserved.
Trademarks. Any of the or 3PEAK trade names, trademarks, graphic marks, and
domain names contained in this document /material are the property of 3PEAK.
You may NOT reproduce, modify, publish, transmit or distribute any Trademark
without the prior written consent of 3PEAK.
Performance Information. Performance tests or performance range contained in
this document/material are either results of design simulation or actual tests
conducted under designated testing environment. Any variation in testing
environment or simulation environment, including but not limited to testing
method, testing process or testing temperature, may affect actual performance
of the product.
Disclaimer. 3PEAK provides technical and reliability data (including data
sheets), design resources (including reference designs), application or other
design recommendations, networking tools, security information and other
resources “As Is”.
3PEAK makes no warranty as to the absence of defects, and makes no warranties
of any kind, express or implied, including without limitation, implied
warranties as to merchantability, fitness for a particular purpose or non-
infringement of any thirdparty’s intellectual property rights. Unless
otherwise specified in writing, products supplied by 3PEAK are not designed to
be used in any life-threatening scenarios, including critical medical
applications, automotive safety-critical systems, aviation, aerospace, or any
situations where failure could result in bodily harm, loss of life, or
significant property damage. 3PEAK disclaims all liability for any such
unauthorized use.
www.3peak.com
GA20230801A6
References
Read User Manual Online (PDF format)
Read User Manual Online (PDF format) >>