LTC DC3122A Buck Regulator User Manual
- June 16, 2024
- LTC
Table of Contents
LTC DC3122A Buck Regulator User Manual
DESCRIPTION
Demonstration circuit 3122A features the LTC®3307A 5V, 3A synchronous step-
down Silent Switcher® operating as a 2MHz, 3.3V to 1.2V 3A buck regulator. The
LTC3307A supports adjustable output voltages from 0.5V to VIN with operating
frequencies from 1MHz up to 3MHz. The LTC3307A is a compact, ultralow
emission, high efficiency, and high speed synchronous monolithic step-down
switching regulator. A minimum on-time of 22ns enables high VIN to low VOUT
conversion ratios at high frequencies.
The DC3122A operating mode may be selected as Burst, Skip or forced continuous
(FC) mode. Setting JP1 to the FC/SYNC position will allow the LTC3307A to sync
to a clock frequency from 1MHz to 3MHz. The LTC3307A operates in forced
continuous mode when syncing to an external clock. The DC3122A is set to a
fixed 2MHz frequency by connecting RT to VIN through a 0 resistor, R9. The
frequency can be easily changed by removing R9 and setting an appropriate
resistor in the R4 location to obtain the desired frequency. Refer to the
LTC3307A data sheet for the proper RT value for a desired switching frequency.
The DC3122A also has an Electromagnetic interference (EMI) filter to reduce
conducted EMI. This EMI filter can be included by applying the input voltage
at the VIN EMI terminal. The EMI performance of the board is shown in the EMI
Test Results section. The red lines in the EMI performance graphs illustrate
the CISPR25 Class 5 peak limits for the conducted and radiated emission tests.
The LTC3307A data sheet gives a complete description of the device, operation
and application information. The data sheet must be read in conjunction with
this demo manual. The LTC3307A is assembled in a 1.6mm × 1.6mm Wafer Level
Chip Scale Package (WLCSP) with exposed pads for low thermal resistance. The
layout recommendations for low EMI operation and maximum thermal performance
are available in the data sheet section Low EMI Printed Circuit Board (PCB)
Layout.
The Efficiency vs Load graph shows the efficiency and the power loss of the
circuit with a 3.3V input in Burst Mode® operation.
Design files for this circuit board are available.
All registered trademarks and trademarks are the property of their respective
owners.
PERFORMANCE SUMMARY
Specifications are at TA = 25°C
BOARD PHOTO
CIRCUIT SCHEMATIC
EMI TEST RESULTS
QUICK START PROCEDURE
Demonstration circuit 3122A is easy to set up and evaluate the performance of
the LTC3307A. See Figure 1 for proper measurement equipment setup and follow
the procedure below.
NOTE: For accurate VIN, VOUT and efficiency measurements, measure VIN at the
VIN SNSE and GND SNSE turrets and VOUT at the VOUT SNSE and GND SNSE turrets
as illustrated as VM1 and VM2 in Figure 1. When measuring the input or output
voltage ripple, care must be taken to avoid a long ground lead on the
oscilloscope probe.
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Set the JP1 jumper to the SKIP position and JP2 to the HI position.
-
With power off, connect the input power supply to VIN and GND. If the input EMI filter is desired, connect the input power supply to VIN EMI.
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Slowly increase PS1 to 1V. If AM1 reads less than 20mA, increase PS1 to 3.3V. Verify that VM1 reads 3.3V and VM2 reads 1.2V.
-
Connect an oscilloscope voltage probe, as shown in Figure 2, in parallel with VM2. Set the channel to AC-coupled, voltage scale to 20mV and time base to 10s. Observe the VOUT ripple voltage.
NOTE: Measure the output voltage ripple by touching the probe tip directly across the output turrets or to TP1, as shown in Figure 2. TP1 is designed for a 50 coax cable to reduce any high-frequency noise that might couple into the oscilloscope probes. -
Verify that the PGOOD turret is high.
-
Increasing the load by 1A intervals up to 4A and record VM1, VM2, AM1 and AM2 for each interval.
-
Repeat Step 6 for PS1 set to 2.5V and again for PS1 set to 5V.
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Set the load to a constant 1.5A. Remove the oscilloscope voltage probe from VOUT. Place a ground clip on the PGND terminal and set the voltage scale to 1V and the time scale to 500ns/division. Trigger on the rising edge of the voltage probe. Using a tip on the voltage probe, contact the SW node on the pad of L1. Observe the duty cycle and the period of the switching waveform (~500ns).
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Set the load current to 0.2A and repeat Step 8. Observe that the switching waveform operates in pulse-skipping mode.
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Move the jumper on JP2 to LO. Verify that VOUT reads 0V and verify that PGOOD is low. Return jumper on JP2 to HI and verify VM2 is 1.2V and verify PGOOD2 is high.
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If forced continuous or Burst Mode operation is desired, set PS1 to 0V. Move JP1 to FC/SYNC or BURST. Repeat Steps 3 through 9. In Step 9, observe that the switching waveform operates in forced continuous or Burst Mode operation.
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To change the frequency, remove R9 if installed. Install the desired RT resistor in the R4 location. Size the inductor and output capacitors to provide the desired inductor ripple and a stable output. Refer to the LTC3307A data sheet and LTpowerCAD for more information on choosing the required components.
-
To test the transient response with a base load, add the desired resistor to produce a minimum load between VOUT and RSNS turrets (RL shown in Figure 1). Note that the total load resistance will be RL plus R11 (100m).
-
Adjust a signal generator with a 10ms period, 10% duty cycle and an amplitude from 1V to 2V to start.
-
Measure the RSNS voltage to observe the current, RSNS/100m. Adjust the amplitude of the pulse to provide the desired transient. Adjust the rising and falling edge of the pulse to provide the desired ramp rate. Refer to the following equations and the optional transient response circuit.
IOUT = VRSNS/100m
Where:
VRSNS = VSG_INPUT – VGS -
When done, turn off PS1 and Load. Remove all connections to the demo board.
THEORY OF OPERATION
Introduction to the DC3122A
The DC3122A features the LTC3307A, a low-voltage synchronous step-down Silent
Switcher. The LTC3307A is a monolithic, constant frequency, current mode
stepdown DC/DC converter. An oscillator, with frequency set using a resistor
on the RT pin, turns on the internal top power switch at the beginning of each
clock cycle. Current in the inductor then increases until the top switch
comparator trips and turns off the top power switch. If the EN pin is low, the
LTC3307A is in shutdown and in a low quiescent current state. When the EN pin
is above its threshold, the switching regulator will be enabled.
The MODE/SYNC pin sets the switching mode to pulseskipping, forced continuous,
or Burst Mode operation. If an external 1MHz to 3MHz clock is connected to the
MODE/SYNC turret while the JP1 is set to the FC/SYNC position, the LTC3307A
switching frequency will sync to the external clock while operating in forced
continuous mode. See the LTC3307A data sheet for more detailed information.
The maximum allowable operating frequency is influenced by the minimum on-time
of the top switch, the ratio of
VOUT to VIN and the available inductor values. The maximum permissible
operating frequency may be calculated
using a minimum tON of 42ns in Equation 1.
(1)
Select an operating switching frequency below fSW(MAX). The recommended ripple
current in the output inductor is
0.9A peak-to-peak for the LTC3307A. This determines the recommended inductor
value for the application.
THEORY OF OPERATION
Accurately Measuring Output Ripple of the LTC3307A
With the fast edge rates of the circuit, high-frequency noise can be observed
when measuring the output voltage with 1M terminated oscilloscope probes. To
better view the output ripple with oscilloscopes of 400MHz bandwidth and above
a 50 coax cable connected as close to the output capacitor as possible should
be used with the oscilloscope channel terminated to 50 at the scope. This will
help to reduce the noise coupling onto and displaying on the scope. The demo
board is set up to solder an U.FL, RECEPT, ST SMD, 0Hz to 6GHz 50 connector
(TP1) near the output capacitor C13. These pads can also be used to solder a
coax cable or other oscilloscope probe connector if desired.
The high-frequency spikes are partially attributed to the interwinding capacitance of the inductor, and the voltage step is partially attributed to the inductance in the output capacitors. This can be reduced by choosing low ESL capacitors or adding small low ESL capacitors in parallel to the output capacitors as close to the inductor as possible. Figure 5 shows the output ripple with only the 0603 output capacitors using 500MHz scope, 50 probe on TP1. Figure 6 shows the output ripple with the added C13 and C14 1nF X2Y capacitors using a 500MHz scope, 50 probe on TP1. The 0201 capacitors, C8 and C9, made little improvement on the ripple with this layout.
PARTS LIST
SCHEMATIC DIAGRAM
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REVISION HISTORY
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit
boards can discharge without detection. Although this product features
patented or proprietary protection circuitry, damage may occur on devices
subjected to high energy ESD. Therefore, proper ESD precautions should be
taken to avoid performance degradation or loss of functionality.
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