Zilog Z80182 Intelligent Peripheral User Guide
- June 16, 2024
- Zilog
Table of Contents
- Z80182 Intelligent Peripheral
- Product Information
- Specifications
- General Description
- Block Diagram
- Pin Assignments
- Product Usage Instructions
- Internal Applications
- External Applications
- FAQ
- Q: What are the available package styles for the
- Q: Can the Z80182/Z8L182 be used for modem applications?
- Q: Does the Z80182/Z8L182 support data compression and error
Z80182 Intelligent Peripheral
Product Information
Specifications
-
Z80182/Z8L182 Zilog Intelligent Peripheral Controller
(ZIP) -
Two ESCC Channels with 32-Bit CRC
-
Three 8-Bit Parallel I/O Ports
-
16550 Compatible MIMIC Interface for Direct Connection to PC,
XT, AT Bus -
100-Pin Package Styles (QFP, VQFP) (0.8 Micron CMOS 5120
Technology) -
Individual WSG for RAMCS and ROMCS
General Description
The Z80182/Z8L182 is a smart peripheral controller IC designed
for modem (especially V. Fast applications), fax, voice messaging,
and other communications applications. It features the Z80180
microprocessor (Z8S180 MPU core) connected with two channels of the
industry-standard Z85230 ESCC (Enhanced Serial Communications
Controller), 24 bits of parallel I/O, and a 16550 MIMIC for direct
connection to the IBM PC, XT, AT bus.
The Z80182/Z8L182 offers flexibility for both internal PC and
external applications. It maintains compatibility with current PC
modem software through its ability to mimic the 16550 UART chip.
The Z80180 acts as an interface between the ESCC and 16550 MIMIC
interface in internal applications, and between the two ESCC
channels in external applications. This interface enables data
compression and error correction on outgoing and incoming data. In
external applications, three 8-bit parallel ports are available for
driving LEDs or other devices.
Block Diagram
Pin Assignments
-
QFP Package: Refer to Pin
Assignments QFP -
VQFP Package: Refer to Pin
Assignments VQFP
Product Usage Instructions
Internal Applications
When using the Z80182/Z8L182 in internal applications, follow
these steps:
-
Connect the Z80182/Z8L182 to the ESCC and 16550 MIMIC
interfaces according to the block diagram and pin assignments. -
Ensure proper power connections by connecting VCC, VDD, GND,
and VSS as described in the manual. -
Configure the Z80180 microprocessor for the desired
functionality. -
Utilize the three 8-bit parallel ports for driving LEDs or
other devices. -
Follow the ESCC and 16550 MIMIC interface specifications for
data transmission and reception.
External Applications
When using the Z80182/Z8L182 in external applications, follow
these steps:
-
Connect the Z80182/Z8L182 to the two ESCC channels according to
the block diagram and pin assignments. -
Ensure proper power connections by connecting VCC, VDD, GND,
and VSS as described in the manual. -
Configure the Z80180 microprocessor for the desired
functionality. -
Utilize the three 8-bit parallel ports for driving LEDs or
other devices. -
Follow the ESCC interface specifications for data transmission
and reception.
FAQ
Q: What are the available package styles for the
Z80182/Z8L182?
A: The Z80182/Z8L182 is available in 100-pin QFP and VQFP
package styles.
Q: Can the Z80182/Z8L182 be used for modem applications?
A: Yes, the Z80182/Z8L182 is designed for modem applications,
including V. Fast applications.
Q: Does the Z80182/Z8L182 support data compression and error
correction?
A: Yes, the Z80182/Z8L182 supports data compression and error
correction on outgoing and incoming data.
Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
PRELIMINARY P RODUCT S PECIFICATION
FEATURES
Z8S180 MPU – Code Compatible with Zilog Z80®/Z180TM CPU – Extended
Instructions – Operating Frequency: 33 MHz/5V or 20 MHz/3.3V – Two DMA
Channels – On-Chip Wait State Generators – Two UART Channels – Two 16-Bit
Timer Counters – On-Chip Interrupt Controller – On-Chip Clock
Oscillator/Generator – Clocked Serial I/O Port – Fully Static – Low EMI Option
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIPTM)
Two ESCCTM Channels with 32-Bit CRC
Three 8-Bit Parallel I/O Ports
16550 Compatible MIMIC Interface for Direct Connection to PC, XT, AT Bus
100-Pin Package Styles (QFP, VQFP) (0.8 Micron CMOS 5120 Technology)
Individual WSG for RAMCS and ROMCS
GENERAL DESCRIPTION
The Z80182/Z8L182 is a smart peripheral controller IC for modem (in particular
V. Fast applications), fax, voice messaging and other communications
applications. It uses the Z80180 microprocessor (Z8S180 MPU core) linked with
two channels of the industry standard Z85230 ESCC (Enhanced Serial
Communications Controller), 24 bits of parallel I/O, and a 16550 MIMIC for
direct connection to the IBM PC, XT, AT bus.
The Z80182/Z8L182 allows complete flexibility for both internal PC and
external applications. Also current PC modem software compatibility can be
maintained with the Z80182/Z8L182 ability to mimic the 16550 UART chip. The
Z80180 acts as an interface between the ESCCTM and 16550 MIMIC interface when
used in internal applications, and between the two ESCC channels in the
external applications. This interface allows data compression and
error correction on outgoing and incoming data. In external applications, three 8-bit parallel ports are available for driving LEDs or other devices. Figure 1 shows the Z80182/ Z8L182 block diagram, while the pin assignments for the QFP and the VQFP packages are shown in Figures 2 and 3, respectively. All references in this document to the Z80182, or Z182 refer to both the Z80182 and Z8L182.
Notes: All Signals with a preceding front slash, “/”, are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
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PRELIM INARY
GENERAL DESCRIPTION (Continued)
D7-D0
Control
GLU
A19-A0
Logic
Bus Transceiver
Tx Data
Rx Data
ESCC Control
85230 ESCC
Channel
A
Z8S180 (Static Z80180)
MPU Core
/TRxCB
85230 ESCC
Channel
B
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
EV1 EV2
/ROMCS /RAMCS
Address Decode
16550 MIMIC Interface
8-Bit Parallel Port C
8-Bit Parallel Port B
8-Bit Parallel Port A
85230 ESCC Ch. A
or Port C
Z180 Signals or Port B
MUX
MUX
MUX
16550 MIMIC or ESCC 85230 Ch. B and Port A
Note: Conventional use of the term “MPU side” refers to all interface through
the Z180 MPU core and “PC side” refers to all interface through the16550 MIMIC
interface.
Figure 1. Z80182/Z8L182 Functional Block Diagram
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
/NMI /RESET /BUSREQ /BUSACK /WAIT EXTAL XTAL VSS PHI /RD /WR /M1 E /MRD//MREQ /IORQ /RFSH /HALT /SYNCB//HCS /RTXCB/HA2 RXDB/HA1
/INT0 /INT1/PC6 /INT2/PC7
ST A0 A1 A2 A3 A4
A5 A6 A7 A8 A9 A10 A11 A12 VSS A13 A14 A15 A16 A17
A18/TOUT VDD A19 D0 D1 D2 D3
100
1
95
90
85
80
5 75
10 70
15
Z80182/Z8L182
100-Pin QFP
65
20 60
25 55
30
35
40
45
50
/TRXCB/HA0 TXDB//HDDIS /CTSB//HWR /DCDB//HRD TXDA /TRXCA RXDA VDD IEI /IOCS/IEO VSS /RTXCA /SYNCA/PC4 /DCDA/PC0 /CTSA/PC1 /MWR/PC2//RTSA /DTR//REQA/PC3 /W//REQA/PC5 PA7/HD7 PA6/HD6 PA5/HD5 PA4/HD4 PA3/HD3 PA2/HD2 PA1/HD1 PA0/HD0 EV2 EV1 /ROMCS /RAMCS
D4 D5 D6 D7 /RTS0/PB0 /CTS0/PB1 /DCD0/PB2 TXA0/PB3 RXA0/PB4 TXA1/PB5 RXA1/PB6 RXS//CTS1/PB7 CKA0//DREQ0 VSS CKA1//TEND0 TXS//DTR//REQB//HINTR CKS//W//REQB//HTXRDY /DREQ1 VDD /TEND1//RTSB//HRXRDY
Figure 2. Z80182/Z8L182 100-Pin QFP Pin Configuration
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PRELIM INARY
GENERAL DESCRIPTION (Continued)
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
/CTSB//HWR /DCDB//HRD TXDA /TRXCA RXDA VDD IEI /IOCS/IEO VSS /RTXCA /SYNCA/PC4 /DCDA/PC0 /CTSA/PC1 /MWR/PC2//RTSA /DTR//REQA/PC3 /W//REQA/PC5 PA7/HD7 PA6/HD6 PA5/HD5 PA4/HD4 PA3/HD3 PA2/HD2 PA1/HD1 PA0/HD0 EV2
TXDB//HDDIS /TRXCB/HA0
RXDB/HA1 /RTXCB/HA2 /SYNCB//HCS
/HALT /RFSH /IORQ /MRD//MREQ
E /M1 /WR /RD PHI VSS XTAL EXTAL /WAIT /BUSACK /BUSREQ /RESET /NMI /INT0
/INT1/PC6 /INT2/PC7
75 76 80
85
90
95
100 1
70
65
60
Z80182/Z8L182 100-Pin VQFP
5
10
15
55 20
51 50
45
40
35
30 26 25
EV1 /ROMCS /RAMCS /TEND1//RTSB//HRXRDY VDD /DREQ1 CKS//W//REQB//HTXRDY TXS//DTR//REQB/HINTR CKA1//TEND0 VSS CKA0//DREQ0 RXS//CTS1/PB7 RXA1/PB6 TXA1/PB5 RXA0/PB4 TXA0/PB3 /DCD0/PB2 /CTS0/PB1 /RTS0/PB0 D7 D6 D5 D4 D3 D2
ST A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VSS A13 A14 A15 A16 A17 A18/TOUT VDD A19 D0 D1
Figure 3. Z80182/Z8L182 100-Pin VQFP Pin Configuration
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z180 CPU SIGNALS
A19-A0. Address Bus (input/output, active High, tri-state). A19-A0 form a
20-bit address bus. The Address Bus provides the address for memory data bus
exchanges up to 1 Mbyte, and I/O data bus exchanges up to 64K. The address bus
enters a high impedance state during reset and external bus acknowledge
cycles, as well as during SLEEP and HALT states. This bus is an input when the
external bus master is accessing the on-chip peripherals. Address line A18 is
multiplexed with the output of PRT channel 1 (TOUT, selected as address output
on reset).
D7-D0. Data Bus (bi-directional, active High, tri-state). D7D0 constitute an
8-bit bi-directional data bus, used for the transfer of information to and
from I/O and memory devices. The data bus enters the high impedance state
during reset and external bus acknowledge cycles, as well as during SLEEP and
HALT states.
/MRD. Memory Read (input/output, active Low, tri-state). /MRD is active when
both the internal /MREQ and /RD are active. /MRD is multiplexed with /MREQ on
the /MRD //MREQ pin. The /MRD//MREQ pin is an input during adapter modes; is
tri-state during bus acknowledge if /MREQ function is selected; and is
inactive High if /MRD function is selected. The default function on power up
is /MRD and may be changed by programming bit 3 of the Interrupt Edge/Pin MUX
Register (xxDFH).
/MWR. Memory Write (input/output, active Low, tri-state). /MWR is active when
both the internal /MREQ and /WR are active. This /RTSA or PC2 combination is
pin multiplexed with /MWR on the /MWR/PC2//RTSA pin. The default function of
this pin on power up is /MWR, which may be changed by programming bit 3 in the
Interrupt Edge/Pin MUX Register (xxDFH).
/RD. Read (input/output, active Low, tri-state). /RD indicates that the CPU
wants to read data from memory or an I/O device. The addressed I/O or memory
device should use this signal to gate data onto the CPU data bus.
/WR. Write (input/output, active Low, tri-state). /WR indicates that the CPU
data bus holds valid data to be stored at the addressed I/O or memory
location.
/WAIT. (input/output active Low). /WAIT indicates to the MPU that the addressed memory or I/O devices are not ready for a data transfer. This input is used to induce additional clock cycles into the current machine cycle. The /WAIT input is sampled on the falling edge of T2 (and subsequent wait states). If the input is sampled Low, then additional wait states are inserted until the /WAIT input is sampled High, at which time execution will continue.
/IORQ. I/O Request (input/output, active Low, tri-state). /IORQ indicates that
the address bus contains a valid I/O address for an I/O read or I/O write
operation. /IORQ is also generated, along with /M1, during the acknowledgment
of the /INT0 input signal to indicate that an interrupt response vector can be
placed onto the data bus. This signal is analogous to the IOE signal of the
Z64180.
/M1. Machine Cycle 1 (input/output, active Low). Together with /MREQ, /M1
indicates that the current cycle is the opcode fetch cycle of an instruction
execution; unless /M1E bit in the OMCR is cleared to 0. Together with /IORQ,
/M1 indicates that the current cycle is for an interrupt acknowledge. It is
also used with the /HALT and ST signals to decode status of the CPU machine
cycle. This signal is analogous to the /LIR signal of the Z64180.
/MREQ. Memory Request (input/output, active Low, tristate). /MREQ indicates
that the address bus holds a valid address for a memory read or memory write
operation. This signal is analogous to the /ME signal of the Z64180. /MREQ is
multiplexed with /MRD on the /MRD//MREQ pin. The /MRD//MREQ pin is an input
during adapter modes; is tri-state during bus acknowledge if the /MREQ
function is selected; and is inactive High if /MRD function is selected.
/HALT. Halt/Sleep Status (input/output, active Low). This output is asserted
after the CPU has executed either the HALT or SLEEP instruction, and is
waiting for either nonmaskable or maskable interrupts before operation can
resume. It is also used with the /M1 and ST signals to decode status of the
CPU machine cycle. On exit of HALT/ SLEEP mode, the first instruction fetch
can be delayed by 16 clock cycles after the /HALT pin goes High, if HALT 16
feature is selected.
/BUSACK. Bus Acknowledge (input/output, active Low). /BUSACK indicates to the
requesting device, the MPU address and data bus, and some control signals,
have entered their high impedance state.
/BUSREQ. Bus Request (input, active Low). This input is used by external
devices (such as DMA controllers) to request access to the system bus. This
request has a higher priority than /NMI and is always recognized at the end of
the current machine cycle. This signal will stop the CPU from executing
further instructions and places the address/data buses and other control
signals, into the high impedance state.
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z180 CPU SIGNALS (Continued)
/NMI. Non-maskable interrupt (input, negative edge triggered). /NMI has a
higher priority than /INT and is always recognized at the end of an
instruction, regardless of the state of the interrupt enable flip-flops. This
signal forces CPU execution to continue at location 0066H.
/INT0. Maskable Interrupt Request 0 (input/output active Low). This signal is
generated by external I/O devices. The CPU will honor this request at the end
of the current instruction cycle as long as the /NMI and /BUSREQ signals are
inactive. The CPU acknowledges this interrupt request with an interrupt
acknowledge cycle. During this cycle, both the /M1 and /IORQ signals become
active. The internal Z180 MPU’s /INT0 source is: /INT0 or ESCC or the MIMIC.
This input is level triggered. /INT0 is an open-drain output, so you can
connect other open-drain interrupts onto the circuit in addition to haveing a
pull-up to VCC.
/INT1, /INT2. Maskable Interrupt Requests 1 and 2 (inputs, active Low). This
signal is generated by external I/O devices. The CPU will honor these requests
at the end of the current instruction cycle as long as the /NMI, /BUSREQ, and
/INT0 signals are inactive. The CPU acknowledges these interrupt requests with
an interrupt acknowledge cycle. Unlike the acknowledgment for /INT0, during
this cycle neither the /M1 or /IORQ signals become active. These pins may be
programmed to provide an active Low level on rising or falling edge
interrupts. The level of the external /INT1 and /INT2 pins may be read through
bits PC6 and PC7 of parallel Port C. Pin /INT1/PC6 multiplexes /INT1 and PC6.
Pin /INT2/PC7 multiplexes /INT2 and PC7.
/RFSH. Refresh (input/output, active Low, tri-state). Together with /MREQ,
/RFSH indicates that the current CPU machine cycle and the contents of the
address bus should be used for refresh of dynamic memories. The low order 8
bits of the address bus (A7-A0) contain the refresh address. This signal is
analogous to the /REF signal of the Z64180.
Z180 MPU UART AND SIO SIGNALS
CKA0, CKA1. Asynchronous Clocks 0 and 1 (bi-directional, active High). These
pins are the transmit and receive clocks for the synchronous channels. CKA0 is
multiplexed with /DREQ0 on the CKA0//DREQ0 pin. CKA1 is multiplexed with
/TEND0 on the CKA1//TEND0 pin.
CKS. Serial Clock (bi-directional, active High). This line is clock for the
CSIO channel and is multiplexed with the ESCC signal (/W//REQB) and the 16550
MIMIC interface signal /HTxRDY on the CKS//W//REQB//HTxRDY pin.
TxA0. Transmit Data 0 (output, active High). This signal is the transmitted
data from the ASCI channel 0. This pin is multiplexed with PB3 (parallel Port
B, bit 3) on the TxA0/PB3 pin.
TxS. Clocked Serial Transmit Data (output, active High). This line is the
transmitted data from the CSIO channel. TxS is multiplexed with the ESCC
signal (/DTR//REQB) and the 16550 MIMIC interface signal HINTR on the TxS//DTR
//REQB//HINTR pin.
/DCD0. Data Carrier Detect 0 (input, active Low). This is a programmable modem
control signal for ASCI channel 0. /DCD0 is multiplexed with the PB2 (parallel
Port B, bit 2) on the /DCD0/PB2 pin.
/RTS0. Request to Send 0 (output, active Low). This is a programmable modem
control signal for ASCI channel 0. This pin is multiplexed with PB0 (parallel
Port B, bit 0) on the /RTS0/PB0 pin.
/CTS0. Clear to Send 0 (input, active Low). This line is a modem control
signal for the ASCI channel 0. This pin is multiplexed with PB1 (parallel Port
B, bit 1) on the /CTS0 /PB1 pin.
RxA0. Receive Data 0 (input, active High). This signal is the receive data to
ASCI channel 0. This pin is multiplexed with PB4 (parallel Port B, bit 4) on
the RxA0/PB4.
RxS. Clocked Serial Receive Data (input, active High). This line is the
receive data for the CSIO channel. RxS is multiplexed with the /CTS1 signal
for ASCI channel 1 and with PB7 (parallel Port B, bit 7) on the RxS//CTS1/PB7
pin.
RxA1. Received Data ASCI channel 1 (input, active High). This pin is
multiplexed with PB6 (parallel Port B, bit 6) on the RxA1/PB6 pin.
TxA1. Transmitted Data ASCI Channel 1 (output, active High). This pin is
multiplexed with PB5 (parallel Port B, bit 5) on the TxA1/PB5 pin.
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z180 MPU DMA SIGNALS
/TEND0. Transfer End 0 (output, active Low). This output is asserted active
during the last write cycle of a DMA operation. It is used to indicate the end
of the block transfer. /TEND0 is multiplexed with CKA1 on the CKA1//TEND0 pin.
/TEND1. Transfer End 1 (output, active Low). This output is asserted active
during the last write cycle of a DMA operation. It is used to indicate the end
of the block transfer. /TEND1 is multiplexed with the ESCC signal /RTSB and
the 16550 MIMIC interface signal /HRxRDY on the /TEND1//RTSB//HRxRDY pin.
/DREQ0. DMA request 0 (input, active Low). /DREQ0 is used to request a DMA
transfer from DMA channel 0. The DMA channel monitors the input to determine
when an external device is ready for a read or write operation. This input can
be programmed to be either level or edge sensed. /DREQ0 is multiplexed with
CKA0 on the CKA0//DREQ0 pin.
/DREQ1. DMA request 1 (input, active Low). /DREQ1 is used to request a DMA
transfer from DMA channel 1. The DMA channel monitors the input to determine
when an external device is ready for a read or write operation. This input can
be programmed to be either level or edge sensed.
Z180TM MPU TIMER SIGNALS
TOUT.
Timer
Out
(output,
active
High).
T OUT
is
the
pulse
output from PRT channel 1. This line is multiplexed with
A18 of the address bus on the A18/TOUT pin.
Z85230 ESCCTM SIGNALS
TxDA. Transmit Data (output, active High). This output signal transmits
channel A’s serial data at standard TTL levels. This output can be tri-stated
during power down modes.
TxDB. Transmit Data (output, active High). This output signal transmits
channel B’s serial data at standard TTL levels. In Z80182/Z8L182 mode 1, TxDB
is multiplexed with the 16550 MIMIC interface /HDDIS signal on the TxDB//HDDIS
pin.
RxDA. Receive Data (inputs, active High). These inputs receive channel A’s
serial data at standard TTL levels.
RxDB. Receive Data (input, active High). These inputs receive channel B’s
serial data at standard TTL levels. In Z80182/Z8L182 mode 1 RxDB is
multiplexed with the 16550 MIMIC HA1 input on the RxDB/HA1 pin.
/TRxCA. Transmit/Receive Clock (input or output, active Low). The functions of
this pin are under channel A program control. /TRxCA may supply the receive
clock or the transmit clock in the Input mode or supply the output of the
digital phase-locked loop, the crystal oscillator, the baud rate generator, or
the transmit clock in the output mode.
/TRxCB. Transmit/Receive Clock (input or output, active Low). The functions of
this pin are under channel B program
control. /TRxCB may supply the receive clock or the transmit clock in the
input mode or supply the output of the Digital Phase-Locked Loop (DPLL), the
crystal oscillator, the baud rate generator, or the transmit clock in output
mode. In Z80182/Z8L182 mode 1 /TRxCB is multiplexed with the 16550 MIMIC
interface HA0 input on the /TRxCB/HA0 pin.
/RTxCA. Receive/Transmit Clock (input, active Low). The functions of this pin
are under channel A program control. In channel A, /RTxCA may supply the
receive clock, the transmit clock, the clock for the baud rate generator, or
the clock for the DPLL. This pin can also be programmed for use by the /SYNCA
pin as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times
the data rate in asynchronous mode.
/RTxCB. Receive/Transmit Clock (input, active Low). The functions of this pin
are under channel B program control. In channel B, /RTxCB may supply the
receive clock, the transmit clock, the clock for the baud rate generator, or
the clock for the DPLL. This pin can also be programmed for use by the /SYNCB
pin as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times
the data rate in asynchronous mode. In Z80182/Z8L182 mode 1 the /RTxCB signal
is multiplexed with 16550 MIMIC interface HA2 input on the /RTxCB/HA2 pin.
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z85230 ESCC SIGNALS (Continued)
/SYNCA, /SYNCB. Synchronization (inputs/outputs, active Low). These pins can
act as either inputs, outputs, or as part of the crystal oscillator circuit.
In the Asynchronous Receive mode (crystal oscillator option not selected),
these pins are inputs similar to /CTS and /DCD. In this mode, transitions on
these lines affect the state of the Sync /Hunt status bits in Read Register 0,
but have no other function. /SYNCA is also multiplexed with PC4 (parallel Port
C, bit 4) on the /SYNCA/PC4 pin.
In External Synchronization mode with the crystal oscillator not selected,
these lines also act as inputs. In this mode /SYNC must be driven Low two
receive clock cycles after the last bit in the sync character is received.
Character assembly begins on the rising edge of the receive clock immediately
preceding the activation of /SYNC.
In the Internal Synchronization mode, (Monosync and Bisync) with the crystal
oscillator not selected, these pins act as outputs and are active only during
the part of the receive clock cycle in which sync characters are recognized.
The sync condition is not latched, so these outputs are active each time a
sync character is recognized (regardless of the character boundaries). In SDLC
mode, these pins act as outputs and are valid on receipt of a flag. In
Z80182/Z8L182 mode 1 the /SYNCB signal is multiplexed with the 16550 MIMIC
interface /HCS input on the /SYNCB //HCS pin.
/CTSA. Clear To Send (input, active Low). If this pin is programmed as auto
enable, a Low on this input enables the channel A transmitter. If not
programmed as auto enable, it may be used as a general-purpose input. The
input is Schmitt-trigger buffered to accommodate slow rise-time input. The
ESCCTM detects transitions on this input and can interrupt the Z180TM MPU on
either logic level transitions. /CTSA is multiplexed with PC1 (parallel Port
C, bit 1) on the /CTSA/PC1 pin.
/CTSB. Clear To Send (input, active Low). This pin is similar to /CTSA’s
functionality but is applicable to the channel B transmitter. In Z80182/Z8L182
mode, the /CTSB signal is multiplexed with the 16550 MIMIC interface /HWR
input on the /CTSB //HWR pin.
/DCDB. Data Carrier Detect (input, active Low). This pin’s functionality is
similar to /DCDA but applicable to the channel B receiver. In Z80182/Z8L182
mode 1, /DCDB is multiplexed with the 16550 MIMIC interface /HRD input on the
/DCDB//HRD pin.
/RTSA. Request to Send (output, active Low). When the Request to Send (RTS)
bit in Write Register 5 channel A is set, the /RTSA signal goes Low. When the
RTS bit is reset in the Asynchronous mode and auto enables is on, the signal
goes High after the transmitter is empty. In Synchronous mode or in
Asynchronous mode with auto enables off, the /RTSA pin strictly follows the
state of the RTS bit. The pin can be used as general-purpose output. /RTSA is
multiplexed with PC2 (parallel Port C bit 2). This /RTSA or PC2 combination is
pin multiplexed with /MWR (active when both the internal /MREQ and /WR are
active) on the /MWR/PC2//RTSA pin. The default function of this pin on power-
up is /MWR which may be changed by programming bit 3 in the Interrupt Edge/Pin
MUX Register (xxDFH).
/RTSB. Request to Send (output, active Low). This pin is similar in
functionality as /RTSA but is applicable on channel B. The /RTSB signal is
multiplexed with the Z180 MPU /TEND1 signal and the 16550 MIMIC interface
/HRxRDY signal on the /TEND1//RTSB//HRxRDY pin.
/DTR//REQA. Data Terminal Ready (output, active Low). This pin functions as it
is programmed into the DTR bit. It can also be used as general-purpose output
(transmit) or as request lines for the DMA controller. The ESCC allows full
duplex DMA transfers. /DTR//REQA is also multiplexed with PC3 (parallel Port
C, bit 3) on the /DTR//REQA /PC3 pin.
/DTR//REQB. Data Terminal Ready (output, active Low). This pin functions as it
is programmed into the DTR bit. It can also be used as general-purpose output
(transmit) or as request lines for the DMA controller. The ESCC allows full
duplex DMA transfers. The /DTR//REQB signal is multiplexed with the Z180 MPU
TxS signal and the 16550 MIMIC interface HINTR signal on the /TxS//DTR//REQB
//HINTR pin.
/DCDA. Data Carrier Detect (input, active Low). This pin functions as receiver enables if it is programmed as an auto enable bit; otherwise, it may be used as a generalpurpose input pin. The pin is Schmitt-trigger buffered to accommodate slow rise-time signals. The ESCC detects transitions on this pin and can interrupt the Z180 MPU on either logic level transitions. /DCDA is also multiplexed with PC0 (parallel Port C, bit 0) on the /DCDA/PC0 pin.
/W//REQA. Wait/Request (output, open drain when programmed for the Wait function, driven High or Low when programmed for a Request function). This dualpurpose output can be programmed as Request (receive) lines for a DMA controller or as Wait lines to synchronize the Z180 MPU to the ESCC data rate. The reset state is Wait. The ESCC allows full duplex DMA transfers. /W//REQA is also multiplexed with PC5 (parallel Port C, bit 5) on the /W//REQA/PC5 pin.
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PS009801-0301
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
/W//REQB. Wait/Request (output, open drain when programmed for the Wait function, driven High or Low when programmed for a Request function). This pin is similar in functionality to /W//REQA but is applicable on
channel B. The /W//REQB signal is multiplexed with the Z180 MPU CKS signal and the 16550 MIMIC interface /HTxRDY signal on the CKS//W//REQB//HTxRDY pin.
16550 MIMIC INTERFACE SIGNALS
HD7-HD0. Host Data Bus (input/output, tri-state). In Z80182/ Z8L182 mode 1,
the host data bus is used to communicate between the 16550 MIMIC interface and
the PC/XT/AT. It is multiplexed with the PA7-PA0 of parallel Port A when the
Z80182/Z8L182 is in mode 0.
/HDDIS. Host Driver Disable (output, active Low). In Z80182/ Z8L182 mode 1,
this signal goes Low whenever the PC/XT/AT is reading data from the 16550
MIMIC interface. In Z80182/Z8L182 mode 0, this pin is multiplexed with the
ESCCTM TxDB signal on the TxDB//HDDIS pin.
HA2-HA0. Host Address (input). In Z80182/Z8L182 mode 1, these pins are the
address inputs to the 16550 MIMIC interface. This address determines which
register the PC/XT/AT accesses. HA0 is multiplexed with /TRxCB on the
/TRxCB/HA0 pin; HA1 is multiplexed with RxDB on the RxDB/HA1 pin; HA2 is
multiplexed with /RTxCB on the /RTxCB/HA2 pin.
/HCS. Host Chip Select (input, active Low). In Z80182/ Z8L182 mode 1, this
input is used by the PC/XT/AT to select the 16550 MIMIC interface for an
access. In Z80182/ Z8L182 mode 0, it is multiplexed with the ESCC /SYNCB
signal on the SYNCB//HCS pin.
/HWR. Host Write (Input, active Low). In Z80182/Z8L182 mode 1, this input is
used by the PC/XT/AT to signal the 16550 MIMIC interface that a write
operation is taking place. In Z80182/Z8L182 mode 0, this input is multiplexed
with the ESCC /CTSB signal on the /CTSB//HWR pin.
/HRD. Host Read (input, active Low). In Z80182/Z8L182 mode 1, this input is
used by the PC/XT/AT to signal the 16550 MIMIC interface that a read operation
is taking place. In Z80182/Z8L182 mode 0, this pin is multiplexed with the
ESCC /DCDB signal on the /DCDB//HRD pin.
HINTR. Host Interrupt (output, active High). In Z80182/ Z8L182 mode 1, this
output is used by the 16550 MIMIC interface to signal the PC/XT/AT that an
interrupt is pending. In Z80182/Z8L182 mode 0, this pin is multiplexed with
the ESCC (/DTR//REQB) signal and the Z180 MPU TxS signal on the
TxS//DTR//REQB//HINTR pin.
/HTxRDY. Host Transmit Ready (output, active Low). In Z80182/Z8L182 mode 1,
this output is used by the 16550 MIMIC in DMA mode to signal the PC/XT/AT that
the Transmit Holding Register is empty. In Z80182/Z8L182 mode 0, this pin is
multiplexed with the ESCC (/W//REQB) signal and the Z180 MPU CKS signal on the
CKS//W// REQB//HTxRDY pin.
/HRxRDY. Host Receive Ready (output, active Low). In Z80182/Z8L182 mode 1,
this output is used by the 16550 MIMIC interface in DMA mode to signal the
PC/XT/AT that a data byte is ready in the Receive Buffer. In Z80182/ Z8L182
mode 0, this pin is multiplexed with the ESCC /RTSB signal and the Z180 MPU
/TEND1 signal on the /TEND1/RTSB /HRxRDY pin.
PARALLEL PORTS
PA7-PA0. Parallel Port A (input/output). These lines can be configured as
inputs or outputs on a bit-by-bit basis when the Z80182/Z8L182 is operated in
mode 0. These pins are multiplexed with the HD7-HD0 when the Z80182/Z8L182 is
in mode 1.
PB7-PB0. Parallel Port B (input/output). These lines can be configured as
inputs or outputs on a bit-by-bit basis when the Port function is selected in
the System Configuration register. The pins are multiplexed with the following
Z180 peripheral functions: /RTS0, /CTS0, /DCD0, TxA0, RxA0, TxA1, RxA1,
(RxS//CTS1).
PC7-PC0. Parallel Port C (input/output). These lines can be configured as inputs or outputs on a bit-by-bit basis for bits PC5-PC0. Bits PC7 and PC6 are input only and read the level of the external /INT2 and /INT1 pins. When /INT2 and/or /INT1 are in edge capture mode, writing a 1 to the respective PC7, PC6 bit clears the interrupt capture latch; writing a 0 has no effect. Bits PC5-PC0 are multiplexed with the following pins from ESCC channel A: (/W//REQA), /SYNCA, (/DTR//REQA), /RTSA, /MWR, /CTSA, /DCDA. The Port function is selected through a bit in the System Configuration Register.
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
EMULATION SIGNALS
EV1, EV2. Emulation Select (input). These two pins determine the emulation mode of the Z180 MPU (Table 1).
Mode
0 1 2 3
Table 1. Evaluation Modes
EV2
EV1
Description
0
0
0
1
1
0
1
1
Normal mode, on-chip Z180 bus master Emulation Adapter Mode Emulator Probe Mode Reserved for Test
SYSTEM CONTROL SIGNALS
ST. Status (output, active High). This signal is used with the /M1 and /HALT
output to decode the status of the CPU machine cycle. If unused, this pin
should be pulled to VDD.
/RESET. Reset Signal (input, active Low). /RESET signal is used for
initializing the MPU and other devices in the system. It must be kept in the
active state for a period of at least three system clock cycles.
IEI. Interrupt Enable Signal (input, active High). IEI is used with the IEO to
form a priority daisy chain when there is more than one interrupt-driven
peripheral.
IEO. Interrupt Enable Output Signal (output, active High). In the daisy-chain
interrupt control, IEO controls the interrupt of external peripherals. IEO is
active when IEI is 1 and the CPU is not servicing an interrupt from the on-
chip peripherals. This pin is multiplexed with /IOCS on the /IOCS/IEO pin. The
/IOCS function is the default on Power On or Reset conditions and is changed
by programming bit 2 in the Interrupt Edge/Pin MUX Register.
/IOCS. Auxiliary Chip Select Output Signal (output, active Low). This pin is
multiplexed with /IEO on the /IOCS/IEO pin. /IOCS is an auxiliary chip select
that decodes A7, A6, /IORQ, /M1 and effectively decodes the address space
xx80H to xxBFH for I/O transactions. A15 through A8 are not decoded so that
the chip select is active in all pages of I/O address space. The /IOCS
function is the default on the /IOCS/IEO pin after Power On or Reset
conditions and is changed by programming bit 2 in the Interrupt Edge/Pin MUX
Register.
/RAMCS. RAM Chip Select (output, active Low). Signal used to access RAM based
upon the Address and the RAMLBR and RAMUBR registers and /MREQ.
/ROMCS. ROM Chip Select (output, active Low). Signal used to access ROM based
upon the address and the ROMBR register and /MREQ.
E. Enable Clock (output, active High). Synchronous machine cycle clock output
during bus transactions.
XTAL. Crystal (input, active High). Crystal oscillator connection. This pin
should be left open if an external clock is used instead of a crystal. The
oscillator input is not a TTL level (reference DC characteristics).
EXTAL. External Clock/Crystal (input, active High). Crystal oscillator
connections to an external clock can be input to the Z80180 on this pin when a
crystal is not used. This input is Schmitt triggered.
PHI. System Clock (output, active High). The output is used as a reference
clock for the MPU and the external system. The frequency of this output is
reflective of the functional speed of the processor. In clock divide-by-two
mode, the pHI frequency is half that of the crystal or input clock. If divide-
by-one mode is enabled, the PHI frequency is equivalent to that of crystal or
input frequency. The PHI frequency is also fed to the ESCC core. If running
over 20 MHz (5V) or 10 MHz (3V) the PHI-ESCC frequency divider should be
enabled to divide the PHI clock by two prior to feeding into the ESCC core.
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PS009801-0301
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
MULTIPLEXED PIN DESCRIPTIONS
A18/T During Reset, this pin is initialized as an A18 pin. OUT.
If either TOC1 or TOC0 bit of the Timer Control Register (TCR) is set to 1,
The TOUT function is selected. If TOC1 and TOC0 bits are cleared to 0, the A18
function is selected.
In normal user mode (on-chip bus master), the A18 signal for the chip select
logic is obtained from the CPU before the external pin is muxed as A18/TOUT.
Therefore, the selection of T will not affect the operation of the 182 chip
OUT
select logic. However, in adapter mode (off-chip bus master), the A18 signal
MUST be provided by the external bus master.
CKA0//DREQ0. During Reset, this pin is initialized as CKA0 pin. If either DM1
or SM1 in the DMA Mode Register (DMODE) is set to 1, /DREQ0 function is always
selected.
Bit 1
0 0 1 1
Table 2. Triple Multiplexed Pins
Bit 2
Master Configuration Register
0
/TEND1,TxS,CKS
1
/RTSB,/DTR//REQB,/W//REQB
0
/TEND1,TxS,CKS
1
/HRxRDY,//HTxRDY,HINTR
The pins below are multiplexed based upon the value of bit 1 of the System Configuration register. If bit 1 is 0, then the Z80182/Z8L182 Mode 0 (non-16550 MIMIC mode) signals are selected; if bit 1 is 1, then Z80182/Z8L182 Mode 1 (16550 MIMIC mode) signals are selected. On Reset, Z80182/Z8L182 Mode 0 is always selected as shown in Table 3.
CKA1//TEND0. During Reset, this pin is initialized as CKA1 pin. If CKA1D bit
in the ASCI control register Ch1(CNTLA1) is set to 1, /TEND0 function is
selected. If CKA1D bit is set to 0, CKA1 function is selected.
RxS//CTS1. During Reset, this pin is initialized as the RxS pin. If CTS1E bit
in the ASCI status register Ch1 (STAT1) is set to 1, /CTS1 function is
selected. If CTS1E bit is set to 0, RxS function is selected. This pin is also
multiplexed with PB7 based on bit 6 in the System Configuration Register.
The pins below are triple-multiplexed based upon the values of bit 1 and bit 2
of the System Configuration Register. The pins are configured as Table 2
specifies. On Reset, both bits 1 and 2 are 0, so /TEND1,TxS,CKS are selected.
Table 3. Mode 0 and Mode 1 Multiplexed Pins
Z80182/Z8L182 Mode 0
Z80182/Z8L182 Mode 1
TxDB RxDB /TRxCB /RTxCB /SYNCB /CTSB /DCDB PA7-PA0
/HDDIS HA1 HA0 HA2 /HCS /HWR /HRD HD7-HD0
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Zilog
PRELIM INARY
Ports B and C Multiplexed Pin Descriptions
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Ports B and C are pin multiplexed with the Z180 ASCI functions and part of ESCC channel A. The MUX function is controlled by bits 7-5 in the System Configuration Register. The MUX is organized as shown in Table 4.
Note 1: When the Port function (PB1) is selected, the internal Z180/ CTS0 is always driven Low. This ensures that the ASCI channel 0 of the Z180TM MPU is enabled to transmit data.
Table 4. Multiplexed Port Pins
Port Mode Function
ASCI/ESCC Mode Function
PB7 PB6 Select with bit 6=1 PB5 System Config Reg. PB4 PB3 PB2 Select with bit
5=1 PB1 System Config Reg. PB0 PC7
PC6
PC5 PC4 PC3 Select with bit 7=1 PC2 System Config Reg. PC1 PC0
RxS,/CTS1 RxA1 TxA1 RxA0 TxA0 /DCD0 /CTS0 (Note 1) /RTS0 Always Reads /INT2 Ext. Status Always Reads /INT1 Ext. Status /W//REQA /SYNCA /DTR//REQA /RTSA (Note 2) /CTSA /DCDA
Note 2: Interrupt Edge /Pin MUX register, bit 3 chooses between the /MWR or
PC2//RTSA combination; the System Configuration Register bit 7 chooses between
PC2 and /RTSA.
Refer to Table 5 for the 1st, 2nd and 3rd pin functions.
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Zilog
Pin Number VQFP QFP
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
10
13
11
14
12
15
13
16
14
17
15
18
16
19
17
20
18
21
19
22
20
23
21
24
22
25
23
26
24
27
25
28
26
29
27
30
28
31
29
32
30
33
31
34
32
35
33
36
34
37
35
38
36
39
37
40
38
41
39
42
40
43
PRELIM INARY
Table 5. Primary, Secondary and Tertiary Pin Functions
1st Function
2nd Function
3rd Function
ST A0 A1 A2 A3
A4 A5 A6 A7 A8
A9 A10 A11 A12 VSS
A13 A14 A15 A16 A17
A18/T OUT
VDD A19 D0 D1
D2 D3 D4 D5 D6
D7
/RTS0
PB0
/CTS0
PB1
/DCD0
PB2
TxA0
PB3
RxA0
PB4
TxA1
PB5
RxA1
PB6
RxS//CTS1
PB7
CKA0//DREQ0
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL MUX Control
SYS CONF REG Bit 5 SYS CONF REG Bit 5 SYS CONF REG Bit 5 SYS CONF REG Bit 5
SYS CONF REG Bit 5 SYS CONF REG Bit 6 SYS CONF REG Bit 6 SYS CONF REG Bit 6
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Zilog
PRELIM INARY
MULTIPLEXED PIN DESCRIPTIONS (Continued)
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Pin Number VQFP QFP
41
44
42
45
43
46
44
47
45
48
46
49
47
50
48
51
49
52
50
53
51
54
52
55
53
56
54
57
55
58
56
59
57
60
58
61
59
62
60
63
61
64
62
65
63
66
64
67
65
68
66
69
67
70
68
71
69
72
70
73
Table 5. Primary, Secondary and Tertiary Pin Functions (Continued)
1st Function
2nd Function
3rd Function
MUX Control
VSS CKA1//TEND0 TxS CKS /DREQ1
/DTR//REQB /W//REQB
HINTR /HTxRDY
SYS CONF REG Bit 1,2 SYS CONF REG Bit 1,2
V DD
/TEND1 /RAMCS /ROMCS EV1
/RTSB
/HRxRDY
SYS CONF REG Bit 1,2
EV2
PA0
HD0
PA1
HD1
PA2
HD2
PA3
HD3
SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1
PA4 PA5 PA6 PA7 /W//REQA
HD4 HD5 HD6 HD7 PC5
SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 7
/DTR//REQA
PC3
/MWR
PC2
/CTSA
PC1
/DCDA
PC0
/SYNCA
PC4
RTSA
SYS CONF REG Bit 7 SYS CONF REG Bit 7 * SYS CONF REG Bit 7 SYS CONF REG Bit 7 SYS CONF REG Bit 7
/RTxCA
VSS
/IOCS
IEO
IEI
VDD
INT EDG/PIN REG Bit 2
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PS009801-0301
DS971820600
Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Table 5. Primary, Secondary and Tertiary Pin Functions (Continued)
Pin Number VQFP QFP
1st Function
2nd Function
3rd Function
MUX Control
71
74
72
75
73
76
74
77
75
78
RxDA /TRxCA TxDA /DCDB /CTSB
/HRD /HWR
SYS CONF REG Bit 1 SYS CONF REG Bit 1
76
79
77
80
78
81
79
82
80
83
TxDB /TRxCB RxDB /RTxCB /SYNCB
/HDDIS HA0 HA1 HA2 /HCS
SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1 SYS CONF REG Bit 1
81
84
82
85
83
86
84
87
85
88
/HALT /RFSH /IORQ /MRD E
/MREQ
INT EDG/PIN REG Bit 3
86
89
87
90
88
91
89
92
90
93
91
94
92
95
93
96
94
97
95
98
/M1 /WR /RD PHI V
SS
XTAL EXTAL /WAIT /BUSACK /BUSREQ
96
99
97
100
98
1
99
2
100
3
/RESET /NMI /INT0 /INT1 /INT2
PC6 PC7
Notes: * Also controlled by Interrupt Edge/Pin MUX Register ** PC7 and PC6 are inputs only and can read values of /INT1 and /INT2.
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z80182/Z8L182 FUNCTIONAL DESCRIPTION
Functionally, the on-chip Z182 MPU and ESCCTM are the same as the discrete devices (Figure 1). Therefore, for a detailed description of each individual unit, refer to the
Product Specification/Technical Manuals of each discrete product. The following subsections describe each of the individual units of the Z182.
Z182 MPU FUNCTIONAL DESCRIPTION
This unit provides all the capabilities and pins of the Zilog Z8S180 MPU
(Static Z80180 MPU). Figure 4 shows the S180 MPU Block Diagram of the Z182.
This allows 100%
software compatibility with existing Z180TM (and Z80®) software. The following is an overview of the major functional units of the Z182.
XTAL EXTAL /RESET /RD /WR /M1 /MREQ /IORQ /HALT /WAIT /BUSREQ /BUSACK /RFSH ST E /NMI /INT0 /INT1 /INT2
Timing &
Ø
Clock
Generator
A18 /TOUT
16-Bit Programmable Reload Timers
(2)
TxS RxS//CTS
CKS
Clocked Serial I/O
Port
MMU
Address Bus (16-Bit) Data Bus (8-Bit)
Bus State Control CPU
DMACs (2)
Interrupt
/DREQ1 /TEND
Asynchronous SCI
(Channel 0)
Asynchronous SCI
(Channel 1)
TxA0 CKA0 /DREQ0 RxA0 /RTS0 /CTS0 /DCD0
TxA1 CKA1 /TEND0 RxA1
A19-A0
D7-D0
Figure 4. S180 MPU Block Diagram of Z182
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PS009801-0301
DS971820600
Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z182 CPU The Z182 CPU is 100% software compatible with the Z80® CPU and has
the following additional features:
Faster Execution Speed. The Z182 CPU is “fine tuned,” making execution speed,
on average, 10% to 20% faster than the Z80 CPU.
Enhanced DRAM Refresh Circuit. Z182 CPU’s DRAM refresh circuit does periodic
refresh and generates an 8-bit refresh address. It can be disabled or the
refresh period adjusted, through software control.
Enhanced Instruction Set. The Z182 CPU has seven additional instructions to
those of the Z80 CPU, which include the MLT (Multiply) instruction.
HALT and Low Power Modes of Operation. The Z182 CPU has HALT and Low Power
modes of operation, which are ideal for the applications requiring low power
consumption like battery operated portable terminals.
System Stop Mode. When the Z182 is in System Stop mode, it is only the Z180
MPU that is in STOP mode.
Standby and Idle Mode. Please refer to the Z8S180 Product Specification for
additional information on these two additional Low Power modes.
Instruction Set. The instruction set of the Z182 CPU is identical to the Z180.
For more details about each transaction, please refer to the Product
Specification/ Technical Manual for the Z180/Z80 CPU.
Z182 CPU Basic Operation Z182 CPU’s basic operation consists of the following
events. These are identical to the Z180 MPU. For more details about each
operation, please refer to the Product Specification/Technical Manual for the
Z180.
Operation Code Fetch Cycle
Memory Read/Write Operation
Input/Output Operation
Bus Request/Acknowledge Operation
Maskable Interrupt Request Operation
Memory Management Unit (MMU) The Memory Management Unit (MMU) allows the user
to map the memory used by the CPU (64 Kbytes of logical addressing space) into
1 Mbyte of physical addressing space. The organization of the MMU allows
object code compatibility with the Z80 CPU while offering access to an
extended memory space. This is accomplished by using an effective common area-
banked area scheme.
DMA Controller The Z182 MPU has two DMA controllers. Each DMA controller
provides high-speed data transfers between memory and I/O devices. Transfer
operations supported are memory-to-memory, memory-to/from-I/O, and I/O-toI/O.
Transfer modes supported are request, burst, and cycle steal. The DMA can
access the full 1 Mbytes addressing range with a block length up to 64 Kbytes
and can cross over 64K boundaries.
Asynchronous Serial Communication Interface (ASCI) This unit provides two
individual full-duplex UARTs. Each channel includes a programmable baud rate
generator and modem control signals. The ASCI channels also support a
multiprocessor communication format.
Programmable Reload Timer (PRT) The Z182 MPU has two separate Programmable
Reload Timers, each containing a 16-bit counter (timer) and count reload
register. The time base for the counters is system clock divided by 20. PRT
channel 1 provides an optional output to allow for waveform generation.
Clocked Serial I/O (CSI/O) The CSI/O channel provides a half-duplex serial
transmitter and receiver. This channel can be used for simple highspeed data
connection to another CPU or MPU.
Programmable Wait State Generator To ease interfacing with slow memory and I/O
devices, the Z182 MPU unit has a programmable wait state generator. By
programming the DMA/WAIT Control Register (DCNTL), up to three wait states are
automatically inserted in memory and I/O cycles. This unit also inserts wait
states during onchip DMA transactions. When using RAMCS and ROMCS wait state
generators, the wait state controller with the most programmed wait states
will determine the number of wait states inserted.
Trap and Non-Maskable Interrupt Request Operation
HALT and Low Power Modes of Operation
Reset Operation
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Zilog
PRELIM INARY
Z85230 ESCCTM FUNCTIONAL DESCRIPTION
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
The Zilog Enhanced Serial Communication Controller ESCCTMis a dual channel,
multiprotocol data communication peripheral. The ESCC functions as a serial-
to-parallel, parallel-to-serial converter/controller. The ESCC can be
software-configured to satisfy a wide variety of serial communications
applications. The device contains a variety of new, sophisticated internal
functions including on-chip baud rate generators, digital phase-lock loops,
and crystal oscillators, which dramatically reduce the need for external
logic.
The ESCC handles asynchronous formats, synchronous byte-oriented protocols
such as IBM® Bisync, and synchronous bit-oriented protocols such as HDLC and
IBM SDLC. This versatile device supports virtually any serial data transfer
application (telecommunication, LAN, etc.)
The device can generate and check CRC codes in any synchronous mode and can be
programmed to check data integrity in various modes. The ESCC also has
facilities for modem control in both channels in applications where these
controls are not needed, the modem controls can be used for general-purpose
I/O.
With access to 14 Write registers and 7 Read registers per channel (number of
the registers varies depending on the version), the user can configure the
ESCC to handle all synchronous formats regardless of data size, number of stop
bits, or parity requirements. The ESCC also accommodates all synchronous
formats including character, byte, and bit-oriented protocols.
The ESCC (Enhanced SCC) is pin and software compatible to the CMOS SCC
version. The following enhancements were made to the CMOS SCC:
Deeper Transmit FIFO (4 bytes)
Deeper Receive FIFO (8 bytes)
Programmable FIFO interrupt and DMA request level
Seven enhancements to improve SDLC link layer supports: – Automatic
transmission of the opening flag – Automatic reset of Tx Underrun/EOM latch –
Deactivation of /RTS pin after closing flag – Automatic CRC generator preset –
Complete CRC reception – TxD pin automatically forced High with NRZI encoding
when using mark idle – Status FIFO handles better frames with an ABORT –
Receive FIFO automatically unlocked for special receive interrupts when using
the SDLC status FIFO
Delayed bus latching for easier microprocessor interface
New programmable features added with Write Register 7′ (WR seven prime)
Write registers, 3, 4, 5 and 10 are now readable
Read register 0 latched during access
Within each operating mode, the ESCC also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.
DPLL counter output available as jitter-free transmitter clock source
Enhanced /DTR, /RTS deactivation timing
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
The following features are common to both the ESCC and NRZ, NRZI or FM encoding/decoding. Manchester
the CMOS SCC:
Code Decoding (Encoding with External Logic).
Two independent full-duplex channels
Baud Rate Generator in each Channel
Synchronous/Isochronous data rates: – Up to 1/4 of the PCLK using external clock source – Up to 5 Mbits/sec at 20 MHz PCLK (ESCC).
Digital Phase-Locked Loop (DPLL) for Clock Recovery Crystal Oscillator
Asynchronous capabilities – 5, 6, 7 or 8 bits/character (capable of handling 4
bits/character or less) – 1, 1.5, or 2 stop bits – Odd or even parity – Times
1, 16, 32 or 64 clock modes – Break generation and detection – Parity, overrun
and framing error detection
Byte oriented synchronous capabilities: – Internal or external character
synchronization – One or two sync characters (6 or 8 bits/sync character) in
separate registers – Automatic Cyclic Redundancy Check (CRC)
generation/detection
The following features are implemented in the ESCCTM for the Z80182/Z8L182
only:
New 32-bit CRC-32 (Ethernet Polynomial)
ESCC Programmable Clock – programmed to be equal to system clock divided by
one or two – programmed by Z80182 Enhancement Register
Note: The ESCCTM programmable clock must be programmed to divide-by-two mode
when operating above the following conditions:
PHI > 20 MHz at 5.0V
SDLC/HDLC capabilities: – Abort sequence generation and checking – Automatic zero insertion and detection – Automatic flag insertion between messages – Address field recognition – I-field residue handling – CRC generation/detection – SDLC loop mode with EOP recognition/loop entry and exit
PHI > 10 MHz at 3.0V
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PRELIM INARY
Z85230 ESCCTM BLOCK DIAGRAM
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
For a detailed description of the Z85230 ESCC, refer to the ESCC Technical Manual. The following figure is the block diagram of the discrete ESCC, which was integrated into the Z182. The /INT line is internally connected to “INTO of the Z182.
Channel A
Exploded View
Transmit Logic
Transmit FIFO 4 Bytes
Transmit MUX
Data Encoding & CRC Generation
Receive and Transmit Clock Multipexer
Digital Phase-Locked
Loop
Baud Rate Generator
Crystal Oscillator Am plif ier
TxDA
/TRxCA /RTxCA
Modem/Control Logic
Receive Logic
Rec. Status Rec. Data
FIFO
FIFO
Receive MUX
/CTSA /DCDA /SYNCA /RTSA /DTRA//REQA
RxDA
SDLC Frame Status FIFO 10 x 19
CRC Checker, Data Decode & Sync Character
Detection
- 8 bytes each
Databus Control
CPU & DMA Bus Interface
Interrupt Control
/INT /INTACK
IEI IEO
Internal Control Logic
Interrupt Control Logic
Channel A Register
Channel B Register
Figure 5. ESCC Block Diagram
Channel A Channel B
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
16550 MIMIC INTERFACE FUNCTIONAL DESCRIPTION
The Z80182/Z8L182 has a 16550 MIMIC interface that allows it to mimic the
16550 device. It has all the interface pins necessary to connect to the
PC/XT/AT bus. It contains the complete register set of the part with the same
interrupt structure. The data path allows parallel transfer of data to and
from the register set by the internal Z80180 of the Z80182/Z8L182. There is no
shift register associated with the mimic of the 16550 UART. This interface
saves the application from doing a serial transfer before performing data
compression or error correction on the data.
Control of the register set is maintained by six priority encoded interrupts
to the Z80182/Z8L182. When the PC/ XT/AT writes to THR, MCR, LCR, DLL, DLM,
FCR or reads the RBR, an interrupt to the Z80182/Z8L182 is generated. Each
interrupt can be individually masked off or all interrupts can be disabled by
writing a single bit. Both mode 0 and mode 2 interrupts are supported by the
16550 MIMIC interface.
Two eight-bit timers are also available to control the data transfer rate of
the 16550 MIMIC interface. Their input is tied to the ESCC channel B divide
clock, so a down count of 24 bits is possible. An additional two eight bit
timers are available for programming the FIFO timeout feature (Four Character
Time Emulation) for both Receive and Transmit FIFO’s.
The 16550 MIMIC interface supports the PC/XT/AT interrupt structure as well as
an additional mode that allows for a wired Logic AND interrupt structure.
The 16550 MIMIC interface is also capable of high speed parallel DMA transfers
by using two control lines and the transmit and receive registers of the 16550
MIMIC interface.
All registers of the 16550 MIMIC interface are accessible in any page of I/O
space since only the lowest eight address lines are decoded. See Figure 6 for
a block diagram of the 16550 MIMIC interface.
16550 MIMIC Side or PC Side Interface
MPU Side Interface
4 PC Addr/Decode
8 PC Databus
2 PC DMA CNTL
1 PC IRQ
Receive Timer
16550 MIMIC Register Set
Transmit Timer
6
Z80180
IRQ
Control
Databus
PC IRQ
DMA Control
Figure 6. 16550 MIMIC Block Diagram
Control/ Config Register
Z80180 Address
8
Z80180 Databus
2
Z80180 DMA Control
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
16550 MIMIC FIFO DESCRIPTION
The receiver FIFO consists of a 16-word FIFO capable of storing eight data bits and three error bits for each character stored (Figure 7). Parity error, Framing error and Break detect bits are stored along with the data bits by copying their value from three shadow bits that are Write Only bits for the Z80180 MPU LSR address. The three shadow bits are cleared after they are copied to the FIFO memory. In FIFO mode, to write error bits into the receiver FIFO, the MPU must first write the Parity, Framing and Break detect status to the Line Status Register (shadow bits) and then write the character associated into the receiver buffer. The data and error bits will then move into the same address in
the FIFO. The error bits become available to the PC side of the interface when that particular location becomes the next address to read (top of FIFO). At that time, they may either be read by the PC by accessing them in the LSR, or they may cause an interrupt to the PC interface if so enabled. The error bits are set by the error status of the byte at the top of the FIFO, but may only be cleared by reading the LSR. If successive reads of the receiver FIFO are performed without reading the LSR, the status bits will be set if any of the bytes read have the respective error bit set. See Table 6 for the setting and clearing of the Line Status Register bits.
MPU Write LSR Shadow B2-B4
error
3
3
PC Read LSR B2-B4
MPU CNTL Line
Internal Clock Sync
MPU
8
Databus
(MPU Side Write)
Internal Clock
W R I T E
B U F F E R
Write Pointer
16×8 Data Bits
ALU
MPU IRQ
16×3 R Error E Bits A
D
B U F F E R
Read Pointer
Internal Clock
PC Cntrl Line Sync
8 PC Side Databus
(PC Side Read) 5
FIFO Control Register
PC IRQ
MPU Side Interface
Figure 7. 16550 MIMIC Receiver FIFO Block Diagram
16550 MIMIC or PC Side Interface
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PRELIM INARY
Table 6. 16550 Line Status Register
Error
Description
How to Set
Error in RCVR FIFO
At least one data byte available in FIFO with one error
At least one error in receiver FIFO
*TEMT
Transmitter empty
MPU writes a 1
*THRE
Transmitter holding register is empty
When MPU has read or emptied the holding register
Break Detect
Break occurs when received data input is held in logic-0 for longer than a full word transmission
MPU writes 1
Framing Error
Received character did not have a valid stop bit
MPU writes 1
Parity Error
Received character did not have correct even or odd parity
MPU writes 1
Overrun Error
Overlapping received characters, thereby destroying the previous character
MPU makes two writes to receiver buffer register
Data Ready
Indicates complete incoming data has been received
Notes: * The TEMT and THRE bits take on different functions when
TEMT/Double Buffer mode is enabled. These signals are delayed to HOST when
using character
emulation delay.
MPU writes to RCVR FIFO or receiver buffer register
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
How to Clear When there are no more errors
MPU writes a 0 When holding register is not empty
There is a PC-side read of the LSR
There is a PC-side read of the LSR There is a PC-side read of the LSR There is
a PC-side read of the LSR
Empty Receiver or Receiver FIFO
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
16550 MIMIC FIFO DESCRIPTION (Continued)
The PC interface may be interrupted when 1, 4, 8 or 14 bytes are available in
the receiver FIFO by setting bits 6 and 7 in the FCR (FIFO Control Register,
PC address 02H) to the appropriate value. If the FIFO is not empty, but below
the above trigger value, a timeout interrupt is available if the receiver FIFO
is not written by the MPU or read by the PC from an interval determined by the
Character Timeout Timer. This is an additional Timer with MPU access only that
is used to emulate the 16550 4 character timeout delay.
The Receive FIFO timeout timers are designed to reload and begin countdown
after every read or write of the Rx FIFO, regardless of the Rx trigger level
or number of bytes in the FIFO. Therefore, it is possible to get Timeout
interrupts more often than Receive data interrupts. In order to closely
emulate a 16550, a receive timeout timer enhancement is provided. When
enabling this feature, the timeout timer will not begin counting down until
the character emulation timer for each byte of data in the Rx FIFO has
expired. Note: Enabling this feature will facilitate increased 16550
compatibility but may impede throughput. If the Receive Timeout interrupt
occurs, the PC HOST will only be allowed to read up to 4-5 consecutive
characters before the Data Ready bit is forced to zero (even if there is still
more data in FIFO). This is required to maintain character pacing.
The timer receives the ESCC /TRxCB as its input clock. Software must determine
the correct values to program into the Receiver Timeout register and the ESCC
TRxCB to achieve the correct delay interval for timeout. These interrupts are
cleared by the FIFO reaching the trigger point or by resetting the Timeout
Interval Timer by FIFO MPU write or PC read access.
With FIFO mode enabled, the MPU is interrupted when the receiver FIFO is
empty, corresponding to bit 5 being set in the IUS/IP register (MPU access
only). This bit corresponds to a PC read of the receive buffer in non-FIFO
(16450) mode. The interrupt source is cleared when the FIFO becomes non-empty
or the MPU reads the IUS/IP register.
The transmitter FIFO is 16-byte FIFO with PC write and MPU read access (Figure
8). In FIFO mode, the PC receives an interrupt when the transmitter becomes
empty corresponding to bit 5 being set in the LSR. This bit and the interrupt
source are cleared when the transmit FIFO becomes non-empty or the Interrupt
Identification Register (IIR) register is read by the PC.
MPU CNTL
Line
MPU Databus (MPU Side Read)
FIFO Control Register
Internal Clock
R
E
A
Sync
D
B
U
F
F
8
E
R
5
Read
Pointer
16×8 Data Bits
ALU
Internal Clock
W
R
I
T
Sync
E
B
U
F
F
8
E
R
Write Pointer
PC Cntrl Line
PC Side Databus (PC Side Write)
Internal Clock
MPU IRQ
MPU Side Interface
Figure 8. 16550 MIMIC Transmitter FIFO Block Diagram
PC IRQ
16550 MIMIC or PC Side Interface
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
On the MPU interface, the transmitted data available can be programmed to interrupt the MPU on 1, 4, 8 or 14 bytes of available data by seeing the appropriate value in the MPU FSCR control register (MPU write only xxECH) bits 6 and 7. A timeout feature exists, Transmit Timeout Timer,
which is an additional 8-bit timer with SCC TxRCB as the input source. If the transmitter FIFO is non-empty and no PC write or MPU read of the FIFO has taken place within the timer interval, a timeout occurs causing a corresponding interrupt to the MPU.
Z80182/Z8L182 MIMIC SYNCHRONIZATION CONSIDERATIONS
Because of the asynchronous nature of the FIFO’s on the MIMIC, some
synchronization plan must be provided to prevent conflict from the dual port
accesses of the MPU and the PC.
To solve this problem, I/O to the FIFO is buffered and the buffers allow both
PC and MPU to access the FIFO asynchronously. Read and Write requests are then
synchronized by means of the MPU clock. Incoming signals are buffered in such
a way that metastable input levels are stabilized to valid 1 or 0 levels.
Actual transfers to and from the buffers, from and to the FIFO memory, are
timed by the MPU clock. ALU evaluation is performed on a different phase than
the transfer to ensure stable pointer values.
Another potential problem is that of simultaneous access of the MPU and PC to any of the various `mailbox’ type registers. This is solved by dual buffering of the various read/write registers. During a read access by either the MPU or PC to a mailbox register, the data in the output or slave portion of the buffered register is not permitted to change. Any write that might take place during this time will be stored in the input of master part of the register. The corresponding status/interrupt is reset appropriately based on the write having followed the read to the register. For example, the IUS/IP bit for the LCR write will not be cleared by the MPU read of the LCR if a simultaneous write to the LCR by the PC takes place. Instead the LSR data will change after the read access and IUS/IP bit 3 remains at logic 1.
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z80182 MIMIC DOUBLE BUFFERING FOR THE TRANSMITTER
The Z80182 Rev DA implements double buffering for the transmitter in 16450
mode and sets the TEMT bit in the LSR Register automatically.
When this feature is enabled and character delay emulation is being used (see
Figure 9):
1. The PC THRE bit in the LSR Register is set when the THR Register is empty;
6. MPU reads TSR buffer;
7. TEMT bit in LSR Register for MPU is set with no delay whenever the TSR
buffer is empty;
8. When the TSR buffer is read by MPU and THR Register is empty and one
character delay timer reaches zero, the TEMT bit in the LSR Register for Host
is set from 0 to 1.
2. PC Host writes to the 16450 THR Register;
3. Whenever the Z80182 TSR buffer is empty and one character delay timer is
in a timed-out state, the byte from the THR Register is transferred to the TSR
buffer; the timer is in timed-out state after FIFO Reset or after Host TEMT is
set. This allows a dual write to THR when Host TEMT is set.
4. Restart character delay timer (timer reloads and counts down) with byte
transfer from THR Register to the TSR buffer;
The PC THRE bit in the LSR Register is reset whenever the THR Register is full
and set whenever THR Register is empty.
MPU IREQ and DMA Request for the transmit data is trigger whenever TSR buffer
is full and cleared whenever TSR buffer is empty.
If character delay emulation is not used the TEMT bit in the LSR Register is
set whenever both the THR Register and the TSR buffer are both empty. The Host
TEMT bit is clear if there is data in either the TSR buffer of THR Register.
5. Whenever the TSR buffer is full, the TEMT bit in MPU LSR Register is reset with no delay;
Host Write
Empty/Full Host & MPU THRE = 1 0
16450 THR Register
Empty/Full (MPU TEMT) TSRE = 1 0
THR to TSR delay
transfer
Byte Transfer if: – THRE=0; – TSR = 1; – Character delay timer is timed out.
TSR Transmit Shift Reg. Emulation
Note: Timer reloads and counts down whenever data is transferred from THR to
TSR.
Added TSR Buffer for the transmit data
Host TEMT = 1 if – THRE = 1 – TSRE = 1 – Emulation delay timer is timed out
Note: MPU sees TSR bit in the LSR Register as TEMT bit
Figure 9. TEMT Emulation Logic Implementation
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
PARALLEL PORTS FUNCTIONAL DESCRIPTION
The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output (with the exception of PC6 and PC7 which are inputs only).
The Ports are controlled through two registers: the Port Direction Control Register and the Port Data Register. (Please see register description for Ports A, B and C).
PROGRAMMING
The following subsections explain and define the parameters for I/O Address
assignments. The three tables in this section describe the mapping of the
common registers shared by the MPU and the 16550 MIMIC. The MPU address refers
to the I/O address as accessed from the MPU side (the Z180TM MPU interface
side of the 16550 MIMIC). Note that only the lowest eight address lines are
decoded for Z182 peripheral access. The full sixteen
address lines are decoded for on-chip Z180 MPU access. The PC address (coined because the UART is common in PCs) is the address needed to access the MIMIC registers through the MIMIC interface signals. The MIMIC interface signals are multiplexed with the ESCC channel B and the Port A signals, and must be activated through the System Configuration Register and the Interrupt Edge/Pin MUX Register.
Table 7. Z80182/Z8L182 MPU Registers
Register Name
MPU Addr
Z80182/Z8L182 MPU Control Registers
Note: “x” indicates don’t care condition
0000H to 00x3FH (Relocatable to 0040H to 007FH or 0080H to 00BFH)
PC Addr None
Table 8. Z80182/Z8L182 MIMIC Register MAP
Register Name
MPU Addr/Access
PC Addr/Access
MMC MIMIC Master Control Register IUS/IP Interrupt Pending IE Interrupt Enable IVEC Interrupt Vector TTCR Transmit Time Constant RTCR Receive Time Constant FSCR FIFO Status and Control RTTC Receive Timeout Time Constant TTTC Transmit Timeout Time Constant RBR Receive Buffer Register THR Transmit Holding Register IER Interrupt Enable Register IIR Interrupt Identification FCR FIFO Control Register MM REGISTER LCR Line Control Register MCR Modem Control Register LSR Line Status Register MSR Modem Status Register SCR Scratch Register DLL Divisor Latch (LSByte) DLM Divisor Latch (MSByte)
xxFFH xxFEH xxFDH xxFCH xxFAH xxFBH xxECH xxEAH xxEBH xxF0H xxF0H xxF1H None xxE9H XXE9H xxF3H xxF4H xxF5H xxF6H xxF7H xxF8H xxF9H
R/W R/Wb7 R/W R/W R/W R/W R/W7-4 R/W R/W W only R only R only
R only W only R only R only R/Wb6432 R/Wb7-4 R only R only R only
None None None None None None None None None 00H 00H 01H 02H 02H None 03H 04H 05H 06H 07H 00H 01H
DLAB=0 R only DLAB=0 W only DLAB=0 R/W R only W only
R/W R/W R only R only R/W DLAB=1 R/W DLAB=1 R/W
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PRELIM INARY
PROGRAMMING (Continued)
Table 9. Z80182/Z8L182 ESCC, PIA and MISC Registers
Register Name
MPU Addr/Access
WSG Chip Select Register Z80182 Enhancements Register PC Data Direction Register PC Data Register Interrupt Edge/Pin MUX Control ESCC Chan A Control Register ESCC Chan A Data Register ESCC Chan B Control Register ESCC Chan B Data Register PB Data Direction Register PB Data Register RAMUBR RAM Upper Boundary Register RAMLBR RAM Lower Boundary Register ROM Address Boundary Register PA Data Direction Register PA Data Register System Configuration Register
xxD8H R/W
xxD9H R/W
xxDDH R/W
xxDEH R/W
xxDFH R/W
xxE0H
R/W
xxE1H
R/W
xxE2H
R/W
xxE3H
R/W
xxE4H
R/W
xxE5H
R/W
xxE6H
R/W
xxE7H
R/W
xxE8H
R/W
xxEDH R/W
xxEEH R/W
xxEFH
R/W
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
PC Addr/Access
None None None None None None None None None None None None None None None
None None
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PRELIM INARY
Z182 MPU CONTROL REGISTERS
Figures 10 through 50 refer to the Z80182/Z8L182 MPU Control registers. For additional information, refer to the Z8S180 Product Specification and Technical Manual.
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
ASCI CHANNELS CONTROL REGISTERS
CNTLA0
Bit MPE RE
Upon RESET R/W
0
0
R/W R/W
Addr 00H
TE
/RTS0
MPBR/ EFR
MOD2
MOD1
MOD0
0
1
x
0
0
0
R/W R/W R/W R/W R/W R/W
MODE Selection
0
0
0 Start + 7-Bit Data + 1 Stop
0
0
1 Start + 7-Bit Data + 2 Stop
0
1
0 Start + 7-Bit Data + Parity + 1 Stop
0
1
1 Start + 7-Bit Data + Parity + 2 Stop
1
0
0 Start + 8-Bit Data + 1 Stop
1
0
1 Start + 8-Bit Data + 2 Stop
1
1
0 Start + 8-Bit Data + Parity + 1 Stop
1
1
1 Start + 8-Bit Data + Parity + 2 Stop
Read – Multiprocessor Bit Receive Write – Error Flag Reset Request To Send
Transmit Enable Receive Enable
Multiprocessor Enable
Figure 10a. ASCI Control Register A (Ch. 0)
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PRELIM INARY
ASCI CHANNELS CONTROL REGISTERS (Continued)
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Bit Upon RESET
R/W
CNTLA1
MPE RE
0
0
R/W R/W
TE 0 R/W
Addr 01H
CKA1D
MPBR/ EFR
MOD2
MOD1
MOD0
1
x
0
0
0
R/W R/W R/W R/W R/W
MODE Selection
0
0
0 Start + 7-Bit Data + 1 Stop
0
0
1 Start + 7-Bit Data + 2 Stop
0
1
0 Start + 7-Bit Data + Parity + 1 Stop
0
1
1 Start + 7-Bit Data + Parity + 2 Stop
1
0
0 Start + 8-Bit Data + 1 Stop
1
0
1 Start + 8-Bit Data + 2 Stop
1
1
0 Start + 8-Bit Data + Parity + 1 Stop
1
1
1 Start + 8-Bit Data + Parity + 2 Stop
Read – Multiprocessor Bit Receive Write – Error Flag Reset CKA1 Disable
Transmit Enable
Receive Enable Multiprocessor Enable
Figure 10b. ASCI Control Register A (Ch. 1)
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Bit Upon Reset
R/W
CNTLB0 MPBT MP Invalid 0 R/W R/W
/CTS/ PS
R/W
PE0 0
R/W
Addr 02H
DR SS2 SS1 SS0
0
1
1
1
R/W R/W R/W R/W
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
General Divide Ratio
SS, 2, 1, 0
000 001 010 011 100 101 110 111
/CTS – Depending on the condition of /CTS pin. PS – Cleared to 0.
PS = 0 (Divide Ratio = 10)
DR = 0 (x16)
DR = 1 (x64)
Ø ÷ 160
Ø ÷ 640
Ø ÷ 320
Ø ÷ 1280
Ø ÷ 640
Ø ÷ 2580
Ø ÷ 1280
Ø ÷ 5120
Ø ÷ 2560
Ø ÷ 10240
Ø ÷ 5120
Ø ÷ 20480
Ø ÷ 10240
Ø ÷ 40960
External Clock (Frequency < Ø ÷ 40)
Clock Source and Speed Select Divide Ratio Parity Even or Odd Clear To Send/Prescale Multiprocessor Multiprocessor Bit Transmit
PS = 1 (Divide Ratio = 30)
DR = 0 (x16)
Ø ÷ 480 Ø ÷ 960 Ø ÷ 1920 Ø ÷ 3840 Ø ÷ 7680 Ø ÷ 15360 Ø ÷ 30720
DR = 1 (x64)
Ø ÷ 1920 Ø ÷ 3840 Ø ÷ 7680 Ø ÷ 15360 Ø ÷ 30720 Ø ÷ 61440 Ø ÷ 122880
Figure 11. ASCI Control Register B (Ch. 0)
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PRELIM INARY
ASCI CHANNELS CONTROL REGISTERS (Continued)
Bit Upon Reset
R/W
CNTLB1 MPBT MP Invalid 0 R/W R/W
/CTS/ PS 0
R/W
PE0 0
R/W
Addr 03H
DR SS2 SS1 SS0
0
1
1
1
R/W R/W R/W R/W
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Clock Source and Speed Select Divide Ratio
Parity Even or Odd Read – Status of /CTS pin Write – Select PS Multiprocessor
Multiprocessor Bit Transmit
General Divide Ratio
SS, 2, 1, 0
PS = 0 (Divide Ratio = 10)
DR = 0 (x16)
DR = 1 (x64)
000 001 010 011 100 101 110 *111
Ø ÷ 160
Ø ÷ 640
Ø ÷ 320
Ø ÷ 1280
Ø ÷ 640
Ø ÷ 2580
Ø ÷ 1280
Ø ÷ 5120
Ø ÷ 2560
Ø ÷ 10240
Ø ÷ 5120
Ø ÷ 20480
Ø ÷ 10240
Ø ÷ 40960
External Clock (Frequency < Ø ÷ 40)
Note: * Baud rate is external clock rate ÷ 16; therefore, Ø ÷ (40 x 16)
is maximum baud rate using external clocking.
PS = 1 (Divide Ratio = 30)
DR = 0 (x16)
Ø ÷ 480 Ø ÷ 960 Ø ÷ 1920 Ø ÷ 3840 Ø ÷ 7680 Ø ÷ 15360 Ø ÷ 30720
Figure 12. ASCI Control Register B (Ch. 1)
DR = 1 (x64)
Ø ÷ 1920 Ø ÷ 3840 Ø ÷ 7680 Ø ÷ 15360 Ø ÷ 30720 Ø ÷ 61440 Ø ÷ 122880
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
STAT0
Bit RDRF OVRN PE
Upon Reset
0
0
0
R/W
R
R
R
Addr 04H
FE RIE /DCD0 TDRE TIE
0
0
0
R R/W R
R R/W
Transmit Interrupt Enable Transmit Data Register Empty Data Carrier Detect
Receive Interrupt Enable
Framing Error Parity Error
Over Run Error Receive Data Register Full
/DCD0 – Depending on the condition of /DCD0 Pin. /CTS0 Pin TDRE
L
1
H
0
Figure 13. ASCI Status Register
STAT1
Addr 05H
Bit RDRF OVRN PE FE RIE CTS1E TDRE TIE
Upon Reset
0
0
0
00
0
1
0
R/W
R
R
R
R R/W R/W R R/W
Transmit Interrupt Enable Transmit Data Register Empty /CTS1 Enable Receive
Interrupt Enable Framing Error Parity Error
Over Run Error Receive Data Register Full
Figure 14. ASCI Status Register (Ch. 1)
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Zilog
PRELIM INARY
ASCI CHANNELS CONTROL REGISTERS (Continued)
TDR0 Write Only
Addr 06H
7 6 5 4 32 1 0
TSR1 Read Only
Addr 09H
xxxxxxxx
Transmit Data
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Received Data
Figure 15. ASCI Transmit Data Register (Ch. 0)
Figure 18. ASCI Receive Data Register (Ch. 1)
TDR1 Write Only
Addr 07H
7 6 5 4 3 2 10
Transmit Data
Figure 16. ASCI Transmit Data Register (Ch. 1)
TSR0 Read Only
Addr 08H
xxxxxxxx
Received Data
Figure 17. ASCI Receive Data Register (Ch. 0)
BRK0 Read/Write
Addr 12H
76543210
Break generate bit 0 = no break 1 = break
Break detect bit 0 = no break 1 = break
Break feature bit 0 = dissolve 1 = enable
Figure 19. ASCI Break Control Register (Ch. 0)
BRK1 Read/Write
Addr 13H
76543210
Break generate bit 0 = no break 1 = break
Break detect bit 0 = no break 1 = break
Break feature enable bit 0 = disable 1 = enable
Figure 20. ASCI Break Control Register (Ch. 1)
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Zilog
PRELIM INARY
CSI/O REGISTERS
CNTR
Bit EF EIE RE TE –
Upon Reset 0
0
0
0
1
R/W R R/W R/W R/W
Addr 0AH
SS2 SS1 SS0 1 11
R/W R/W R/W
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Speed Select
Transmit Enable Receive Enable End Interrupt Enable End Flag
SS2, 1, 0
000 001 010 011
Baud Rate
Ø ÷ 20 Ø ÷ 40 Ø ÷ 80 Ø ÷ 100
SS2, 1, 0
100 101 110 111
Figure 21. CSI/O Control Register
Baud Rate
Ø ÷ 320 Ø ÷ 640 Ø ÷ 1280 External Clock (Frequency < Ø ÷ 20)
TRDR Read/Write
Addr 0BH
7 6 54 3 21 0
Read – Received Data Write – Transmit Data
Figure 22. CSI/O Transmit/Receive Data Register
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Zilog TIMER DATA REGISTERS
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
TMDR0L Read/Write
Addr 0CH
7 6 54 3 21 0
Figure 23. Timer 0 Data Register L
TMDR0H Read/Write
Addr 0DH
15 14 13 12 11 10 9 8
When Read, read Data Register L before reading Data Register H.
TMDR1L Read/Write
Addr 14H
7 6 54 3 21 0
Figure 24. Timer 1 Data Register L
Figure 25. Timer 0 Data Register H
TMDR1H Read/Write
Addr 15H
15 14 13 12 11 10 9 8
When Read, read Data Register L before reading Data Register H.
Figure 26. Timer 1 Data Register H
TIMER RELOAD REGISTERS
RLDR0L Read/Write
Addr 0EH
7 6 54 3 21 0
Figure 27. Timer 0 Reload Register L
RLDR1L Read/Write
Addr 16H
7 6 54 3 21 0
Figure 28. Timer 1 Reload Register L
RLDR0H Read/Write
Addr 0FH
15 14 13 12 11 10 9 8
Figure 29. Timer 0 Reload Register H
RLDR1H Read/Write
Addr 17H
15 14 13 12 11 10 9 8
Figure 30. Timer 1 Reload Register H
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Zilog TIMER CONTROL REGISTER
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Bit Upon Reset
R/W
TCR TIF1
0 R
TIF0 0 R
Addr 10H TIE1 TIE0 TOC1 TOC0 TDE1 TDE0
0 0 0 00 0 R/W R/W R/W R/W R/W R/W
Timer Down Count Enable 1,0 Timer Output Control 1,0 Timer Interrupt Enable 1,0 Timer Interrupt Flag 1,0
TOC1,0
00 01 10 11
A15/TOUT
Inhibited Toggle
0 1
Figure 31. Timer Control Register
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Zilog FREE RUNNING COUNTER
PRELIM INARY
FRC Read Only
Addr 18H
76 543 210
Figure 32. Free Running Counter
CPU CONTROL REGISTER
CPU Control Register (CCR) Addr 1FH D7 D6 D5 D4 D3 D2 D1 D0 000 00 000
Figure 33. CPU Note: See Figure 49 for full description.
DMA REGISTERS
SAR0L Read/Write
SA7
Addr 20H SA0
SAR0H Read/Write
SA15
Addr 21H SA8
SAR0B
Read/Write
Addr 22H
SA19 SA16
– —
Bits 0-2 (3) are used for SAR0B
A19, A18, A17, A16 DMA Transfer Request
x x 0 0 /DREQ0 (external) x x 0 1 RDR0 (ASCI0) x x 1 0 RDR1 (ASCI1) x x 1 1
Not Used
Figure 34. DMA 0 Source Address Registers
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
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DMA REGISTERS
DAR0L Read/Write
DA7
Addr 23H DA0
PRELIM INARY
MAR1L Read/Write MA7
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Addr 28H MA0
DAR0H Read/Write
DA15
Addr 24H DA8
DAR0B Read/Write
Addr 25H DA19 DA16
– —
Bits 0-2 (3) are used for DAR0B
A19, A18, A17, A16 DMA Transfer Request
x x 0 0 /DREQ0 (external) x x 0 1 TDR0 (ASCI0) x x 1 0 TDR1 (ASCI1) x x 1 1
Not Used
Figure 35. DMA 0 Destination Address Registers
BCR0L Read/Write
BC7
Addr 26H BC0
BCR0H Read/Write
BC15
Addr 27H BC8
Figure 36. DMA 0 Byte Counter Registers
MAR1H Read/Write
MA15
Addr 29H MA8
MAR1B Read/Write
Addr 2AH MA19 MA16
—-
Figure 37. DMA 1 Memory Address Registers
IAR1L Read/Write
IA7
Addr 2BH IA0
IAR1H Read/Write
IA15
Addr 2CH IA8
Figure 38. DMA I/O Address Registers
BCR1L Read/Write
BC7
Addr 2EH BC0
BCR1H Read/Write
BC15
Addr 2FH BC8
Figure 39. DMA 1 Byte Count Registers
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Zilog DMA REGISTERS (Continued)
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
DSTAT
Bit DE1 DE0 /DWE1 /DWE0 DIE1 DIE0
Upon Reset 0
0
1
1
0
0
R/W R/W R/W W W R/W R/W
Addr 30H – DIME 10
R
DMA Master Enable DMA Interrupt Enable 1, 0 DMA Enable Bit Write Enable 1, 0 DMA Enable Ch 1, 0
Figure 40. DMA Status Register
Bit Upon Reset
R/W
DMODE
–
–
1
1
Addr 31H
DM1 DM0 SM1 SM0 MMOD –
0
0
0
0
0
1
R/W R/W R/W R/W R/W
Memory MODE Select Ch 0 Source Mode 1, 0 Ch 0 Destination Mode 1, 0
DM1, 0 00 01 10 11
Destination M M M I/O
Address DAR0+1 DAR0-1 DAR0 Fixed DAR0 Fixed
MMOD
0 1
Mode
Cycle Steal Mode Burst Mode
SM1, 0 00 01 10 11
Source M M M I/O
Address SAR0+1 SAR0-1 SAR0 Fixed SAR0 Fixed
Figure 41. DMA Mode Registers
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Bit Upon Reset
R/W
DCNTL
MWI1 MWI0
1
1
R/W R/W
IWI1 1
R/W
IWI0 1
R/W
Addr 32H DMS1 DMS0 DIM1 DIM0
0
0
0
0
R/W R/W R/W R/W
DMA Ch 1 I/O Memory Mode Select /DREQi Select, i = 1, 0
I/0 Wait Insertion
Memory Wait Insertion
- MWI1, 0 No. of Wait States
00
0
01
1
10
2
11
3
IWI1, 0
00 01 10 11
No. of Wait States
1 2 3 4
DMSi
1 0
Sense
Edge Sense Level Sense
DM1, 0
Transfer Mode
Address Increment/Decrement
00
M – I/O
MAR1+1
IAR1 Fixed
01
M – I/O
MAR1-1
IAR1 Fixed
10
I/O – M
IAR1 Fixed
MAR1+1
11
I/O – M
IAR1 Fixed
MAR1-1
Note: * If using ROM/RAM Chip Select wait state generators,
the Z180 wait state generator should be set to 0.
Figure 42. DMA/WAIT Control Register
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PRELIM INARY
MMU REGISTERS
CBR
Addr 38H
Bit CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
Upon Reset
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
MMU Common Base Register
Figure 43. MMU Common Base Register
BBR
Addr 39H
Bit BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0
Upon Reset
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
MMU Bank Base Register
Figure 44. MMU Bank Base Register
CBAR
Addr 3AH
Bit CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0
Upon Reset
1
1
1
1
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
MMU Bank Area Register MMU Common Area Register
Figure 45. MMU Common/Bank Area Register
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Zilog
PRELIM INARY
SYSTEM CONTROL REGISTERS
IL
Addr 33H
Bit
IL7 IL6 IL5 –
–
–
–
–
Upon Reset
00000000
R/W
R/W R/W R/W
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL Interrupt Vector Low
Figure 46. Interrupt Vector Low Register
ITC
Bit
TRAP UFO –
–
Upon Reset
0
0
1
1
R/W
R/W R
Addr 34H – ITE2 ITE1 ITE0 1001
R/W R/W R/W
Figure 47. INT/TRAP Control Register
/INT Enable 2, 1, 0 Undefined Fetch Object TRAP
RCR
Addr 36H
Bit
REFE REFW –
–
–
– CYC1 CYC0
Upon Reset
1
1
1
1
1
1
0
0
R/W
R/W R/W
R/W R/W
Cycle Select Refresh Wait State Refresh Enable
CYC1, 0
00 01 10 11
Interval of Refresh Cycle
10 states 20 states 40 states 80 states
Figure 48. Refresh Control Register
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PRELIM INARY
SYSTEM CONTROL REGISTERS (Continued)
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
OMCR
Addr 3EH
Bit M1E /M1TE /IOC –
–
–
–
–
Upon Reset 1
1
1
11 111
R/W R/W W R/W
Note: This register should be programmed to 0x0xxxxxb (x = don’t care) as a part of Initialization.
I/O Compatibility /M1 Temporary Enable /M1 Enable
Figure 49. Operation Mode Control Register
ICR
Bit IOA7 IOA6 IOSTP –
Upon Reset 0
0
0
1
R/W R/W R/W R/W
–
–
11
Addr 3FH
–
–
11
I/O Stop
I/O Address Combination of 11 is reserved
Figure 50. I/O Control Register
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
ADDITIONAL FEATURES ON THE Z182 MPU
The following is a detailed description of the enhancements to the Z8S180 from
the standard Z80180 in the areas of STANDBY, IDLE, and STANDBY-QUICK RECOVERY
modes.
Add-On Features
There are five different power-down modes. SLEEP and SYSTEM STOP are inherited
from the Z80180. In SLEEP mode, the CPU is in a stopped state while the on-
chip
I/Os are still operating. In I/O STOP mode, the on-chip I/Os are in a stopped state while leaving the CPU running. In SYSTEM STOP mode, both the CPU and the on-chip I/Os are in the stopped state to reduce the current consumption. The Z8S180 has added two additional power-down modes, STANDBY and IDLE, to reduce the current consumption even further. The differences among these power-down modes are summarized in Table 10.
Power-Down Modes
SLEEP I/O STOP SYSTEM STOP IDLE STANDBY
CPU Core
Stop Running Stop Stop Stop
On-Chip I/O
Running Stop Stop Stop Stop
Table 10. Power Down Modes
Recovery
OSC.
CLKOUT Source
Running Running Running Running Stop
Running Running Running Stop Stop
RESET, Interrupts By Programming RESET, Interrupts RESET, Interrupts, BUSREQ RESET, Interrupts, BUSREQ
Notes: IDLE and STANDBY modes are only offered in Z8S180. Note that the minimum recovery time can be achieved if INTERRUPT is used as the Recovery Source.
Recovery Time (Minimum)
1.5 Clock 1.5 Clock 8 +1.5 Clock 217 +1.5 Clock (Normal Recovery) 26 +1.5
Clock (Quick Recovery)
STANDBY Mode
The Z8S180 has been designed to save power. Two lowpower programmable power-
down modes have been added; STANDBY mode and IDLE mode. The STANDBY/IDLE mode
is selected by multiplexing D6 and D3 of the CPU Control Register (CCR, I/O
Address = 1FH). To enter STANDBY mode:
1. Set D6 and D3 to 1 and 0, respectively.
2. Set the I/O STOP bit (D5 of ICR, I/O Address = 3FH) to 1.
3. Execute the SLEEP instruction.
When the part is in STANDBY mode, it behaves similar to the SYSTEM STOP mode
which currently exists on the Z80180, except that the STANDBY mode stops the
external oscillator, internal clocks and reduces power consumption to
typically 50 µA..
Since the clock oscillator has been stopped, a restart of the oscillator
requires a period of time for stabilization. An
18-bit counter has been added in the Z8S180 to allow for oscillator
stabilization. When the part receives an external IRQ or BUSREQ during STANDBY
mode, the oscillator is restarted and the timer counts down 217 counts before
acknowledgment is sent to the interrupt source.
The recovery source needs to remain asserted for duration of the 217 count,
otherwise standby will be resumed.
The following is a description of how the part exits STANDBY for different
interrupts and modes of operation.
STANDBY Mode Exit with /RESET
The /RESET input needs to be asserted for a duration long enough for the
crystal oscillator to stabilize and then exit from the STANDBY mode. When
/RESET is de-asserted, it goes through the normal reset timing to start
instruction execution at address (logical and physical) 0000H.
The clocking is resumed within the Z8S180 and at the system clock output after
/RESET is asserted when the crystal oscillator is restarted, but not yet
stabilized.
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
STANDBY Mode Exit with BUS REQUEST
Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the
Z8S180 exits STANDBY mode when the /BUSREQ input is asserted; the crystal
oscillator is then restarted. An internal counter automatically provides time
for the oscillator to stabilize, before the internal clocking and the system
clock output of the Z8S180 are resumed.
The Z8S180 relinquishes the system bus after the clocking is resumed by:
If an External Maskable Interrupt input is asserted, the CPU responds
according to the status of the Global Interrupt Enable Flag IEF1 (determined
by the ITE1 bit) and the settings of the corresponding interrupt enable bit in
the Interrupt/Trap Control Register (ITC: I/O Address = 34H):
a. If an interrupt source is disabled in the ITC, asserting the corresponding
interrupt input would not cause the Z8S180 to exit STANDBY mode. This is true
regardless of the state of the Global Interrupt Enable Flag IEF1.
– Tri-State the address outputs A19 through A0.
– Tri-State the bus control outputs /MREQ, /IORQ, /RD and /WR.
– Asserting /BUSACK
b. If the Global Interrupt Flag IEF1 is set to 1, and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input causes the Z8S180 to exit STANDBY mode. The CPU performs an interrupt acknowledge sequence appropriate to the input being asserted when clocking is resumed if:
The Z8S180 regains the system bus when /BUSREQ is deactivated. The address
outputs and the bus control outputs are then driven High; the STANDBY mode is
exited.
If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting the
/BUSREQ would not cause the Z8S180 to exit STANDBY mode.
If STANDBY mode is exited due to a reset or an external interrupt, the Z8S180
remains relinquished from the system bus as long as /BUSREQ is active.
STANDBY Mode Exit with External Interrupts
STANDBY mode can be exited by asserting input /NMI. The STANDBY mode may also
exit by asserting /INT0, /INT1 or /INT2, depending on the conditions specified
in the following paragraphs.
/INT0 wake-up requires assertion throughout duration of clock stabilization
time (217 clocks).
If exit conditions are met, the internal counter provides time for the crystal
oscillator to stabilize, before the internal clocking and the system clock
output within the Z8S180 are resumed.
1. Exit with Non-Maskable Interrupts
– The interrupt input follows the normal interrupt daisy chain protocol.
– The interrupt source is active until the acknowledge cycle is completed.
c. If the Global Interrupt Flag IEF1 is disabled, i.e., reset to 0, and if an
interrupt source is enabled in the ITC, asserting the corresponding interrupt
input will still cause the Z8S180 to exit STANDBY mode. The CPU will proceed
to fetch and execute instructions that follow the SLEEP instruction when
clocking is resumed.
If the External Maskable Interrupt input is not active until clocking resumes,
the Z8S180 will not exit STANDBY mode. If the Non-Maskable Interrupt (/NMI) is
not active until clocking resumes, the Z8S180 still exits the STANDBY mode
even if the interrupt sources go away before the timer times out, because /NMI
is edge-triggered. The condition is latched internally once /NMI is asserted
Low.
IDLE Mode
IDLE mode is another power-down mode offered by the Z8S180. To enter IDLE
mode:
1. Set D6 and D3 to 0 and 1, respectively.
2. Set the I/O STOP bit (D5 of ICR, I/O Address = 3FH) to 1.
If /NMI is asserted, the CPU begins a normal NMI interrupt acknowledge sequence after clocking resumes.
3. Execute the SLEEP instruction.
2. Exit with External Maskable Interrupts
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
When the part is in IDLE mode, the clock oscillator is kept oscillating, but
the clock to the rest of the internal circuit, including the CLKOUT, is
stopped completely. IDLE mode is exited in a similar way as STANDBY mode,
i.e., RESET, BUS REQUEST or EXTERNAL INTERRUPTS, except that the 217 bit wake-
up timer is bypassed; all control signals are asserted eight clock cycles
after the exit conditions are gathered.
STANDBY-QUICK RECOVERY Mode
STANDBY-QUICK RECOVERY mode is an option offered in STANDBY mode to reduce the
clock recovery time in STANDBY mode from 217 clock cycles (6.5 ms at 20 MHz)
to 26 clock cycles (3.2 µs at 20 MHz). This feature can only be used when
providing an oscillator as clock source.
To enter STANDBY-QUICK RECOVERY mode:
1. Set D6 and D3 to 1 and 1, respectively.
2. Set the I/O STOP bit (D5 of ICR, I/O Address = 3FH) to 1.
When the part is in STANDBY-QUICK RECOVERY mode, the operation is identical to
STANDBY mode except when exit conditions are gathered, i.e., RESET, BUS
REQUEST or EXTERNAL INTERRUPTS; the clock and other control signals are
recovered sooner than the STANDBY mode.
Note: If STANDBY-QUICK RECOVERY is enabled, the user must make sure stable
oscillation is obtained within 64 clock cycles.
CPU Control Register
The Z8S180 has an additional register which allows the programmer to select
options that directly affect the CPU performance as well as controlling the
STANDBY operating mode of the chip. The CPU Control Register (CCR) allows the
programmer to change the divide-by-two internal clock to divide-by-one. In
addition, applications where EMI noise is a problem, the Z8S180 can reduce the
output drivers on selected groups of pins to 25% of normal pad driver
capability which minimizes the EMI noise generated by the part.
3. Execute the SLEEP instruction.
CPU Control Register (CCR) Addr 1FH D7 D6 D5 D4 D3 D2 D1 D0
00000000
Clock Divide 0 = XTAL/2 1 = XTAL/1
Standby/Idle Enable 00 = No Standby 01 = Idle After Sleep 10 = Standby After
Sleep 11 = Standby After Sleep 64 Cycle Exit (Quick Recovery)
BREXT 0 = Ignore BUSREQ In Standby/Idle 1 = Standby/Idle Exit on BUSREQ
LNAD/DATA 0 = Standard Drive 1 = 25% Drive On A19-A0, D7-D0
LNCPUCTL 0 = Standard Drive 1 = 25% Drive On CPU Control Signals
Reserved
LNPHI 0 = Standard Drive 1 = 25% Drive On EXT.PHI Clock
Figure 51. CPU Control Register
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
CPU Control Register
Bit 7. Clock Divide Select. Bit 7 of the CCR allows the programmer to set the internal clock to divide the external clock by 2 if the bit is 0 and divide- by-one if the bit is 1. Upon reset, this bit is set to 0 and the part is in divide-by-two mode. Since the on-board oscillator is not guaranteed to operate above 20 MHz, an external source must be used to achieve the maximum 33 MHz operation of the part, i.e., an external clock at 66 MHz with 50% duty cycle.
recovery is reduced to 64 clock cycles after the exit conditions are gathered.
Similarly, in STANDBY mode, the Z8S180 enters STANDBY after fetching the
second opcode of a SLEEP instruction, if the I/O STOP bit is set.
Bit 5. BREXT. This bit controls the ability of the Z8S180 to honor a bus
request during STANDBY mode. If this bit is set to 1 and the part is in
STANDBY mode, a BUSREQ is honored after the clock stabilization timer is timed
out.
If an external oscillator is used in divide-by-one mode, the minimum pulse
width requirement must be satisfied.
Bits 6 and 3. STANDBY/IDLE Enable. These two bits are used for
enabling/disabling the IDLE and STANDBY mode.
Bit 4. LNPHI. This bit controls the drive capability on the PHI Clock output.
If this bit is set to 1, the PHI Clock output is reduced to 25% of its drive
capability.
Bit 2. Reserved
Setting D6, D3 to 0 and 1, respectively, enables the IDLE mode. In the IDLE
mode, the clock oscillator is kept oscillating but the clock to the rest of
the internal circuit, including the CLKOUT, is stopped. The Z8S180 enters IDLE
mode after fetching the second opcode of a SLEEP instruction, if the I/O STOP
bit is set.
Setting D6, D3 to 1 and 0, respectively, enables the STANDBY mode. In the
STANDBY mode, the clock oscillator is stopped completely. The Z8S180 enters
STANDBY after fetching the second opcode of a SLEEP instruction, if the I/O
STOP bit is set.
Setting D6, D3 to 1 and 1, respectively, enables the STANDBY-QUICK RECOVERY
mode. In this mode, its operations are identical to STANDBY except that the
clock
Bit 1. LNCPUCTL. This bit controls the drive capability of the CPU Control pins. When this bit is set to 1, the output drive capability of the following pins is reduced to 25% of the original drive capability:
– /BUSACK – /RD – /WR – /M1 – E
– /MREQ – /IORQ – /RFSH – /HALT – /TEND1
Bit 0. LNAD/DATA. This bit controls the drive capability of the Address/Data bus output drivers. If this bit is set to 1, the output drive capability of the Address and Data bus output is reduced to 25% of its original drive capability.
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z85230 ESCCTM CONTROL REGISTERS
See Figures 52 and 53 for the ESCC Control registers. For additional
information, refer to the ESCC Product Specification /Technical Manual.
The Z80182/Z8L182 has two ESCC channels. They can be accessed in any page of
I/O space since only the lowest eight address lines are decoded for access.
Their Z180TM MPU Address locations are shown in Table 11.
When the 16550 MIMIC interface is enabled, ESCC channel B is disconnected from the output pins. The channel B /TRxCB clock is connected to the Transmit and Receive timers of the 16550 MIMIC interface. It is recommended that /TRxCB be programmed as an output with proper baud rate values to timeout the transmitter and receiver of the 16550 MIMIC interface.
ESCC Channel A ESCC Channel B
Table 11. ESCC Control and Data Map
Control Data
Z180 MPU Address xxE0H Z180 MPU Address xxE1H
Control Data
Z180 MPU Address xxE2H Z180 MPU Address xxE3H
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
PROGRAMMING THE ESCCTM
The ESCC contains write registers in each channel that are programmed by the
system separately to configure the functional uniqueness of the channels.
In the ESCC, the data registers are directly addressed by selecting a High on
the D//C pin. With all other registers (with the exception of WR0 and RR0),
programming the write registers requires two write operations and reading the
read registers, both a write and a read operation. The first write is to WR0
and contains three bits that point to the selected register. The second write
is the actual control word for the selected read register accessed. All of the
ESCC registers, including the data registers, may be accessed in this fashion.
The pointer bits are automatically cleared after the read or write operation
so that WR0 (or RR0) is addressed again.
Divide-by-two should be programmed when running the Z182 beyond:
– 20 MHz, 5V – 10 MHz, 3V
Note: Upon power-up or reset the system clock is equal to the ESCC clock.
Initialization. The system program first issues a series of commands to
initialize the basic mode of operation. This is followed by other commands to
qualify conditions within the selected mode. For example, in the Asynchronous
mode, character length, clock rate, number of stop bits, and even or odd
parity should be set first. Then the interrupt mode is set, and finally, the
receiver and transmitter are enabled.
With the Z80182/Z8L182, a new feature is implemented in the ESCC. The
Transmitter and Receiver is now capable of sending and comparing a 32-bit
CRC-32 (Ethernet Polynomial):
x32 + x26 +x23 +x22 + x16 + x12 + x11 +x10 + x8 + x7 + x5 + x4 + x2 + x + 1
This feature is enabled by access to WR7′ Bit 7, which selects the 32-bit CRC
polynomial for the transmitter and receiver and overrides any selection of
SDLC/CRC-16 CRCs. When the 32-bit CRC override feature is enabled, the
transmitter will only send 32-bit CRC when CRC is to be sent. On the receive
side, the CRC comparison/calculation will be done only on 32-bit CRC values.
The result of the 32-bit CRC comparison will be maintained in RR1 bit D6 in
place of the 16-bit CRC comparison result. The 32-bit CRC compare result will
also be maintained in the 10×19 FIFO for frames in which 32-bit CRC is
enabled. The CRC still can be preset to all 0s or all 1s. 32-bit CRC is
disabled upon power-up or reset.
Note: The ESCC cannot do simultaneous calculation/ comparison using both
16-bit and 32-bit CRC.
Also, for the Z80182/Z8L182 only, the clock provided to the ESCC core is equal
to the system clock divided by 1 or 2. The divider is programmed in the Z80182
Enhancement Register bit 3.
Write Registers. The ESCC contains 16 write registers (17 counting the
transmit buffer) in each channel. These write registers are programmed
separately to configure the functional “personality” of the channels. There
are two registers (WR2 and WR9) shared by the two channels that are accessed
through either of them. WR2 contains the interrupt vector for both channels,
while WR9 contains the interrupt control bits and reset commands. A new
register, WR7′, was added to the ESCC and may be written to if WR15, D0 is
set. Figure 50 shows the format of each write register.
Read Registers. The ESCC contains ten read registers (eleven, counting the
receive buffer (RR8) in each channel). Four of these may be read to obtain
status information (RR0, RR1, RR10, and RR15). Two registers (RR12 and RR13)
are read to learn the baud rate generator time constant. RR2 contains either
the unmodified interrupt vector (channel A) or the vector modified by status
information (channel B). RR3 contains the Interrupt Pending (IP) bits (channel
A only). RR6 and RR7 contain the information in the SDLC Frame Status FIFO,
but is only read when WR15, D2 is set. If WR7′ D6 is set, Write Registers WR3,
WR4, WR5, WR7, and WR10 can be read as RR9, RR4, RR5, and RR14, respectively.
Figure 51 shows the format of each Read register.
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Zilog CONTROL REGISTERS
Write Register 0 (non-multiplexed bus mode) D7 D6 D5 D4 D3 D2 D1 D0
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Write Register 2 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 Register 0
0 0 1 Register 1
0 1 0 Register 2
0 1 1 Register 3
1 0 0 Register 4
1 0 1 Register 5
1 1 0 Register 6
1 1 1 Register 7
0 0 0 Register 8
0 0 1 Register 9
0 1 0 Register 10
0 1 1 Register 11 1 0 0 Register 12
1 0 1 Register 13
1 1 0 Register 14
1 1 1 Register 15
0 0 0 Null Code 0 0 1 Point High 0 1 0 Reset Ext/Status Interrupts 0 1 1 Send Abort (SDLC) 1 0 0 Enable Int on Next Rx Character 1 0 1 Reset Tx Int Pending 1 1 0 Error Reset 1 1 1 Reset Highest IUS
0 0 Null Code 0 1 Reset Rx CRC Checker 1 0 Reset Tx CRC Generator 1 1 Reset Tx Underrun/EOM Latch
- With Point High Command
Write Register 1 D7 D6 D5 D4 D3 D2 D1 D0
Ext Int Enable Tx Int Enable Parity is Special Condition
0 0 Rx Int Disable 0 1 Rx Int On First Character or Special Condition 1 0 Int
On All Rx Characters or Special Condition 1 1 Rx Int On Special Condition Only
WAIT/DMA Request On Receive//Transmit /WAIT/DMA Request Function WAIT/DMA
Request Enable
V0
V1
V2
V3
Interrupt
V4
Vector
V5
V6
V7
Write Register 3 D7 D6 D5 D4 D3 D2 D1 D0
0 0 Rx 5 Bits/Character 0 1 Rx 7 Bits/Character 1 0 Rx 6 Bits/Character 1 1 Rx
8 Bits/Character
Rx Enable Sync Character Load Inhibit Address Search Mode (SDLC) Rx CRC Enable Enter Hunt Mode Auto Enables
Write Register 4 D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable Parity EVEN//ODD
0 0 Sync Modes Enable 0 1 1 Stop Bit/Character 1 0 1 1/2 Stop Bits/Character 1
1 2 Stop Bits/Character
0 0 8-Bit Sync Character 0 1 16-Bit Sync Character 1 0 SDLC Mode (01111110
Flag) 1 1 External Sync Mode
0 0 X1 Clock Mode 0 1 X16 Clock Mode 1 0 X32 Clock Mode 1 1 X64 Clock Mode
Figure 52. Write Register Bit Functions
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PRELIM INARY
CONTROL REGISTERS (Continued)
Write Register 5 D7 D6 D5 D4 D3 D2 D1 D0
Tx CRC Enable RTS /SDLC/CRC-16 Tx Enable Send Break
0 0 Tx 5 Bits(Or Less)/Character 0 1 Tx 7 Bits/Character 1 0 Tx 6
Bits/Character 1 1 Tx 8 Bits/Character
DTR
Write Register 6 D7 D6 D5 D4 D3 D2 D1 D0
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Sync7 Sync1 Sync7 Sync3 ADR7 ADR7
Sync6 Sync0 Sync6 Sync2 ADR6 ADR6
Sync5 Sync5 Sync5 Sync1 ADR5 ADR5
Sync4 Sync4 Sync4 Sync0 ADR4 ADR4
Sync3 Sync3 Sync3
1 ADR3
x
Sync2 Sync2 Sync2
1 ADR2
x
Sync1 Sync1 Sync1
1 ADR1
x
Sync0 Sync0 Sync0
1 ADR0
x
Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC SDLC (Address Range)
Write Register 7 D7 D6 D5 D4 D3 D2 D1 D0
Sync7 Sync6 Sync5 Sync4
Sync5 Sync4 Sync3 Sync2
Sync15 Sync14 Sync13 Sync12
Sync11 Sync10 Sync9 Sync8
0
1
1
1
Sync3 Sync2 Sync1
Sync1 Sync0 x
Sync11 Sync10 Sync9
Sync7 Sync6 Sync5
1
1
1
Sync0 x
Sync8 Sync4
0
Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC
Figure 52. Write Register Bit Functions (Continued)
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Zilog
WR 7′ Prime D7 D6 D5 D4 D3 D2 D1 D0
PRELIM INARY
Write Register 10 D7 D6 D5 D4 D3 D2 D1 D0
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Auto Tx Flag Auto EOM Reset Auto RTS Deactivation Rx FIFO Int Level DTR/REQ Timing Mode Tx FIFO Int Level Extended Read Enable 32-bit CRC Enable
Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0
0 0 No Reset 0 1 Not used 1 0 Channel Reset 1 1 Force Hardware Reset
VIS NV DLC MIE Status High//Status Low Software INTACK Enable
0 0 NRZ 0 1 NRZI 1 0 FM1 (Transition = 1) 1 1 FM0 (Transition = 0)
6-Bit//8-Bit Sync Loop Mode Abort//Flag On Underrun Mark//Flag Idle Go Active
On Poll
CRC Preset I//O
Write Register 11
D7 D6 D5 D4 D3 D2 D1 D0
0 0 /TRxC Out = Xtal Output 0 1 /TRxC Out = Transmit Clock 1 0 /TRxC Out = BR
Generator Output 1 1 /TRxC Out = DPLL Output
/TRxC O/I
0 0 Transmit Clock = /RTxC Pin 0 1 Transmit Clock = /TRxC Pin 1 0 Transmit
Clock = BR Generator Output 1 1 Transmit Clock = DPLL Output
0 0 Receive Clock = /RTxC Pin 0 1 Receive Clock = /TRxC Pin 1 0 Receive Clock
= BR Generator Output 1 1 Receive Clock = DPLL Output
/RTxC Xtal//No Xtal
Figure 52. Write Register Bit Functions (Continued)
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PRELIM INARY
CONTROL REGISTERS (Continued)
Write Register 12 D7 D6 D5 D4 D3 D2 D1 D0
Write Register 14 D7 D6 D5 D4 D3 D2 D1 D0
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Write Register 13 D7 D6 D5 D4 D3 D2 D1 D0
TC0
TC1
TC2
TC3
Lower Byte of
TC4
Time Constant
TC5
TC6
TC7
TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15
Upper Byte of Time Constant
0 0 0 Null Command 0 0 1 Enter Search Mode 0 1 0 Reset Missing Clock 0 1 1 Disable DPLL 1 0 0 Set Source = BR Generator 1 0 1 Set Source = /RTxC 1 1 0 Set FM Mode 1 1 1 Set NRZI Mode
BR Generator Enable BR Generator Source /DTR/Request Function Auto Echo Local Loopback
Write Register 15 D7 D6 D5 D4 D3 D2 D1 D0
WR7′ SDLC Feature Enable Zero Count IE SDLC FIFO Enable DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE
Figure 52. Write Register Bit Functions (Continued)
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Zilog
Read Register 0 D7 D6 D5 D4 D3 D2 D1 D0
PRELIM INARY
Read Register 3 D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available Zero Count Tx Buffer Empty DCD Sync/Hunt CTS Tx
Underrun/EOM Break/Abort
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
0 0 0 Ext/Status IP Tx IP Rx IP 0 0
Read Register 1 D7 D6 D5 D4 D3 D2 D1 D0
All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error Rx Overrun Error CRC/Framing Error End of Frame (SDLC)
Read Register 2 D7 D6 D5 D4 D3 D2 D1 D0
V0
V1
V2
V3
Interrupt
Vector
V4
V5
V6
V7
Read Register 6 D7 D6 D5 D4 D3 D2 D1 D0
BC0 BC1 BC2 BC3 BC4 BC5 BC6 BC7 Can only be accessed if the SDLC FIFO
enhancement is enabled (WR15 bit D2 set to 1)
SDLC FIFO Status and Byte Count (LSB)
Read Register 7 D7 D6 D5 D4 D3 D2 D1 D0
BC8 BC9 BC10 BC11 BC12 BC13 FDA: FIFO Data Available 1 = Status Reads from
FIFO 0 = Status Reads from EMSCC FOS: FIFO Overflow Status 1 = FIFO Overflowed
0 = Normal Can only be accessed if the SDLC FIFO enhancement is enabled (WR15
bit D2 set to 1)
SDLC FIFO Status and Byte Count (LSB)
Figure 52. Write Register Bit Functions (Continued)
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PRELIM INARY
CONTROL REGISTERS (Continued)
Read Register 10 D7 D6 D5 D4 D3 D2 D1 D0
Read Register 13 D7 D6 D5 D4 D3 D2 D1 D0
0 On Loop 0 0 Loop Sending 0 Two Clocks Missing One Clock Missing
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15
Upper Byte of Time Constant
Read Register 12 D7 D6 D5 D4 D3 D2 D1 D0
Read Register 15 D7 D6 D5 D4 D3 D2 D1 D0
TC0
TC1
TC2
TC3
Lower Byte
TC4
of Time Constant
TC5
TC6
TC7
0 Zero Count IE SDLC Status FIFO Enable DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE
Figure 53. Read Register Bit Functions
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS
Figures 54 through 65 describe miscellaneous registers that control the Z182
configuration, RAM/ROM chip select, interrupt and various status and timers.
D7 D6 D5 D4 D3 D2 D1 D0 0000000 0
System Configuration Register
Bit 7 Port C Select When this bit is set to 1, bit 8 parallel Port C is
selected on the multiplexed pins. When this bit is reset to 0 then these
multiplexed pins take ESCCTM Channel A functions.
Daisy Chain 0=ESCC > 16550 MIMIC 1=16550 MIMIC> ESCC
ESCC/MIMIC 0=ESCC Channel B 1=16550 MIMIC Interface
Tri-Muxed Pins 0=Z80180 1=ESCC Channel/16550 MIMIC
Disable ROMs 0=ROM Sel Enabled 1=ROM Sel Disabled
DOUT 0=No Data Out 1=Data Out
Port PB4-PB0 Select 0=ASCI Channel 0 Func 1=PB4-PB0 Selected
Port PB7-PB5 Select 0=RXA1, TXA1, (RXS,/CTS1) 1=PB7-PB5 Selected
Port C Select 0=ESCC Channel A Func 1=Port C Selected
Figure 54. System Configuration Register (Z180 MPU Read/Write, Address xxEFH)
Bit 6 PB7-PB5 Select When this bit is set to 1, parallel Port B bits 7 through
5 are selected on the multiplexed pins. When this bit is reset to 0, these
multiplexed pins become RxA1, TxA1 and RxS/ CTS1.
Bit 5 PB4-PB0 Select When this bit is set to 1, parallel Port B bits 4 through
0 are selected on the multiplexed pins. When this bit is reset to 0, these
multiplexed pins take ASCI channel 0 functions.
Bit 4 DDOUT ROM Emulator Mode Enable When this bit is set to 1, the Z182 is in
“ROM emulator mode”. In this mode, bus direction for certain transaction
periods are set to the opposite direction to export internal bus transactions
outside the Z80182/Z8L182. This allows the use of ROM emulators/logic
analyzers for application development (see Tables 12a and 12b).
Note: The word “Out” means that the Z182 data bus direction is in output mode,
“In” means input mode, and “Z” means high impedance. DD stands for Data
Direction
OUT
Out and is the status of the D4 bit in the System Configuration Register
(SCR).
Table 12a. Data Bus Direction (Z182 Bus Master) I/O And Memory Transactions
I/O Write
I/O Read
I/O Write
I/O Read
Write
to On-Chip From On-Chip to Off-Chip From Off-Chip To
Peripherals Peripherals Peripherals Peripherals Memory
Read From Mode
Z80182 /Z8L182 Refresh Idle Mode
Z80182
Out
/Z8L182
Data Bus
(DD =0) OUT
Z80182
Out
/Z8L182
Data Bus
(DD =1) OUT
Z
Out
Out
Out
In
Out
In
Z
Z
In
Out
In
Z
Z
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PRELIM INARY
Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS
Table 12b. Data Bus Direction (Z182 Bus Master) Interrupt Acknowledge Transaction
Intack For On-Chip Peripheral (IEI=1)
Intack For Off-Chip Peripheral (IEI=0)
Z80182/Z8L182
Data Bus
Z
In
(DDOUT=0)
Z80182/Z8L182
Data Bus
Out
In
(DDOUT=1)
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Table 13a. Data Bus Direction (Z80182/Z8L182 is not Bus Master) I/O And Memory Transactions
I/O Write
I/O Read
I/O Write
I/O Read
Write Read
to On-Chip From On-Chip to Off-Chip From Off-Chip To
From
Peripherals Peripherals Peripherals Peripherals Memory Mode
Refresh
Z80182 Idle Mode
Z80182
In
Out
Z
/Z8L182
Data Bus
DD =0) OUT
Z80182
In
Out
Z
/Z8L182
Data Bus
(DD =1) OUT
Z
Z
In
Z
Z
Z
Z
In
Z
Z
Table 13b. Data Bus Direction (Z80182/Z8L182 is not Bus Master) Interrupt Acknowledge Transaction
Intack For On-Chip Peripheral
Intack For Off-Chip Peripheral
Z80182/Z8L182
Data Bus
Out
In
(DDOUT=0)
Z80182/Z8L182
Data Bus
Out
In
(DD =1) OUT
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS
Bit 3 Disable ROMs If this bit is 1, it disables the ROMCS pin. If it is 0,
addresses below the ROM boundary set by the ROMBR register will cause the
ROMCS pin to go Low.
Bit 2 Tri-Muxed Pins Select The Z80182/Z8L182 has three pins that are triple
multiplexed and controlled by bit 2 and bit 1. Table 14 shows the different
modes.
Bit 1 ESCCTM Channel B/MIMIC If this bit is 0, Mode 0 is selected. If this bit
is 1, Mode 1 is selected.
Mode 0: Channel A ESCC Enabled Channel B ESCC Enabled PIA Port Enabled 16550
MIMIC Interface Disabled
Table 14. SCR Control for Triple Multiplexed Pins
Bit 2 Bit 1 System Configuration Register
0
0
/TEND1,TxS,CKS
0
1
/TEND1,TxS,CKS
1
0
/RTSB,(/DTR//REQB),(/W//REQB)
1
1
/HRxRDY,//HTxRDY,HINTR
Mode 1: Channel A ESCC enabled Channel B outputs disabled PIA disabled 16550
MIMIC Interface Enabled
Bit 0 Daisy Chain This bit is used to set interrupt priority of the ESCC and
16550 MIMIC interface. If it is 0, the ESCC is higher up in the daisy chain
than the 16550 MIMIC interface. If it is 1, the 16550 interface is higher up
than the ESCC. Note that /INT0 is used for both MIMIC and ESCC Interrupts.
/RAMCS AND /ROMCS REGISTERS
To assist decoding of ROM and RAM blocks of memory, three more registers and
two pins have been added to the
Z80182/Z8L182. The two pins are /ROMCS and /RAMCS. The three registers are RAMUBR, RAMLBR and ROMBR.
D7 D6 D5 D4 D3 D2 D1 D0 Upon reset 1 1 1 1 1 1 1 1
D7 D6 D5 D4 D3 D2 D1 D0 Upon reset 1 1 1 1 1 1 1 1
A19-A12
Figure 55. RAMUBR (Z180 MPU Read/Write, Address xxE6H)
A19-A12
Figure 56. RAMLBR (Z180 MPU Read/Write, Address xxE7H)
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PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
/RAMCS AND /ROMCS REGISTERS (Continued)
RAMUBR, RAMLBR RAM Upper Boundary Range, RAM Lower Boundary Range These two
registers specify the address range for the /RAMCS signal. When accessed
memory addresses are less than or equal to the value programmed in the RAMUBR
and greater than or equal to the value programmed in the RAMLBR, /RAMCS is
asserted. The A18 signal from the CPU is taken before it is multiplexed with
TOUT. In the case that these registers are programmed to overlap, /ROMCS takes
priority over /RAMCS (/ROMCS is asserted and /RAMCS is inactive).
Chip Select signals are going active for the address range:
Because /ROMCS takes priority over /RAMCS, the latter will never be asserted
until the value in the ROMBR and RAMLBR registers are re-initialized to lower
values.
D7 D6 D5 D4 D3 D2 D1 D0 Upon reset 1 1 1 1 1 1 1 1
A19-A12
Figure 57. ROMBR (Z180 MPU Read/Write, Address xxE8H)
/ROMCS: (ROMBR) >= A19-A12 >= 0 /RAMCS: (RAMUBR) >= A19-A12 >= (RAMLBR)
These registers are set to FFH at POR, and the boundary addresses of ROM and
RAM are as follows:
ROM lower boundary address (fixed) = 00000H
ROM upper boundary address (ROMBR register) = 0FFFFFH
RAM lower boundary address (RAMLBR register) = 0FFFFFH
ROMBR ROM Address Boundary Register This register specifies the address range
for the /ROMCS signal. When accessed, memory addresses are less than or equal
to the value programmed in this register, the /ROMCS signal is asserted.
The A18 signal from the CPU is obtained before it is multiplexed with T . This
signal can be forced to a “1”
OUT
(inactive state) by setting bit 3 in the System Configuration Register, to
allow the user to overlay the RAM area over the ROM area.
RAM upper boundary address (RAMUBR register) = 0FFFFFH
Z80182 Improvement to the Wait State Generator
A separate Wait State Generator is provided for access memory using /ROMCS and
/RAMCS. A single 8-bit register is added to enable/disable this feature as
well as provide two 3-bit fields that provide 1 to 8 waits for each chip
select.
WSG Chip Select Register (Z80182 address D8H)
There are two wait state generators in the Z182. The actual number of wait states inserted is the greatest number of both the Z180 WSG and the chip select WSG. In order to use the Chip Select WSG, the Z180 WSG should be programmed to 0 wait states.
Bit 7
/RAMCS Wait State Generator Enable. Disable on power-up or reset.
D7 D6 D5 D4 D3 D2 D1 D0
0
0
Bits 6-4 /RAMCS Wait States 1 to 8. Eight wait states on power-up or reset.
Bit 3
/ROMCS Wait State Generator Enable. Disable on power-up or reset.
Bits 2-0 /ROMCS Wait States 1 to 8. Eight wait states on power-up or reset.
/ROMCS Wait States 1-8
/ROMCS Wait State Generator Enable
/RAMCS Wait States 1-8
/RAMCS Wait State Generator Enable
Figure 58. WSG Chip Select Register (Z180 MPU Read/Write, Address xxD8H)
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Zilog
PRELIM INARY
INTERRUPT EDGE/PIN MUX REGISTER
D7 D6 D5 D4 D3 D2 D1 D0 0101110 0
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Halt Recovery Select 1 16 Cycle delay on Halt recovery 0 No wait delay on Halt
recovery
Low Noise Select 1 Select low noise for Z182(not Z180) 0 Select normal drive
for Z182 pins
IEO,/IOCS Select 1 Select/IOCS Function 0 Select IEO Function
/MREQ, /MRD, PC2, /RTSA, /MWR Select 1 Select /MRD, /MWR 0 Select /MREQ, PC2,
/RTSA
/INT1 Mode Select 0X Normal Level Detect 10 Falling (Neg) Edge Det 11 Rising
(Pos) Edge Det
/INT2 Mode Select 0X Normal Level Detect 10 Falling (Neg) Edge Det 11 Rising
(Pos) Edge Det
Figure 59. Interrupt Edge/Pin MUX Register (Z180 MPU Read/Write, Address xxDFH)
Bits 7-6. These bits control the interrupt capture logic for the external
/INT2 PIN. When programmed as 0X’, the /INT2 pin performs as the normal level detecting interrupt pin. When programmed as 10 the negative edge detection is enabled. Any falling edge latches an active Low on the internal /INT2 of the Z180. This interrupt must be cleared by writing a 1 to bit 7 of the Port C Data Register. Programming these control bits to 11 enables rising edge interrupts to be latched. The latch is cleared in the same fashion as the falling edge. Bits 5-4. These bits control the interrupt capture logic for the external /INT1 PIN. When programmed as0X’, the /INT1 pin performs as the normal level
detecting interrupt pin. When programmed as 10, the negative edge detection is
enabled. Any falling edge latches an active Low on the internal /INT1 of the
Z180. This interrupt must be cleared by writing a 1 to bit 6 of the Port C
Data Register. Programming these control bits to 11 enables rising edge
interrupts to be latched. The latch is cleared in the same fashion as the
falling edge. Edge detect logic cannot be used in Emulation Adaptor EV mode 1.
Bit 3. Programming this bit to 1 selects the /MRD and the /MWR functions. The
default for power up and /RESET conditions is 1, i.e., the /MRD and /MWR. By
programming
this bit to 0 the /MREQ Z180 function is enabled, as well as the PC2//RTSA function on the PC2//RTSA//MWR pin. If the /MREQ Z180 function is enabled, any external bus master must be prevented from asserting Z182’s IRD signal unless accessing Z182’s IO.
Bit 2. This bit selects the /IOCS function which is the default for power up and /RESET conditions. By programming this bit to 0 the IEO function is enabled for this multiplexed pin.
Bit 1. This bit selects the low noise or normal drive feature for the Z182 pins . The default at power up is normal drive for Z182 pins. By programming this bit to 1, low noise for the Z182 pins is chosen and the output drive capability of the following pins is reduced to 25% of the original drive capability:
– CKS – RxS/CTS1 – TxS
– CKA1/TEND0 – TxA1
– CKA0/DREQ0 – TxA0
Programming this bit to 0 selects normal drive for the Z182 pins. Refer to the Z8S180 Product Specification for Low noise control of Z180 pins.
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Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
INTERRUPT EDGE/PIN MUX REGISTER (Continued)
Bit 0. Programming this bit to 1 selects a 16 cycle wait delay on recovery from HALT. Halt Recovery is disabled if bit 5 of the enhancement register is set to 1. A 0 selects no wait delay on Halt recovery.
If Halt Recovery is selected, the following pins assume the following states during halt and during the recovery, whether it is in HALT, SLP, IDLE or STBY Modes:
Address Data Bus
RD WR MREQ/MRD M1 ST IORQ BUSACK RFSH
E IOCS MWR
=Z =Z =Z =Z =Z =1 =1 =1 =1 =1 = Note 3 =Z = 1 (Note 4)
Notes: 1. This assumes that BUSREQ is not activated during the
halt.
2. This assumes that the refresh is not enabled. This would not be a logical
case since the address bus is tri-stated during the Halt mode.
3. There is no control on the E line during the halt recovery so transitions
on the pin are possible.
4. This is only true if MWR function is enabled.
The Halt recovery mode is implemented by applying wait states to the next CPU
operation following the exit from halt. All signals listed above are forced to
their specified state (unless otherwise noted) during halt and also during the
recovery state. Sixteen cycles after the halt pin goes High the signals are
released to their normal state, then eight wait states are inserted to allow
proper access to accommodate slow memories.
After the first memory access, the wait states will be inserted as programmed
in the wait state generators.
In addition, if bit 4 of the Z80182 Enhancement Register is set, the TxDA pin will be tri-stated during Halt and Recovery modes.
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
16550 MIMIC INTERFACE REGISTERS
MIMIC Master Control Register (MMC)
The 16550 MIMIC interface is controlled by the MMC register. Setting it allows
for different modes of operation such as using the 8-bit counters, DMA
accesses, and which IRQ structure is used with the PC/XT/AT.
D7 D6 D5 D4 D3 D2 D1 D0 0000000 0
Both counters are single pass and stop on a count of Zero. Their purpose is to delay data transfer just as if the 16550 UART had to shift the data in and out. This is provided to alleviate any software problems a high speed continuous data transfer might cause to existing software. If this is not a concern, then data can be read and written as fast as the two machines can access the devices. In FIFO mode of operation , the timers are used to delay the status to the PC interface by the time required to actually shift the characters out, or in, if an actual UART were present.
VIS Vector Include Status 0 Mode 0 Interrupts 1 Mode 2 Interrupts
HINTR 00 Normal 01 Wire And 10 Out 2 Control 11 Reserved
Rx DMA Tx DMA
0=Chan 0 Z180 1=Chan 1 Z180 0=Chan 1 Z180 1=Chan 0 Z180
Rx DMA Enable
Tx DMA Enable
Rx Timer Enable
Tx Timer Enable
Bit 5 Transmit DMA Enable (Read/Write) If this bit is set to 1, it enables the
Transmit DMA function.
Bit 4 Receive DMA Enable (Read/Write) If this bit is set to 1, it enables the
Receive DMA function.
Bit 3 Receive DMA Channel Select (Read/Write) If bit 3 is set to 0, then
Receive DMA transfer is done through Z180 DMA channel 0 and the Transmit DMA
is done through DMA channel 1. If bit 3 is set to 1, then Receive DMA transfer
is done through Z180 DMA channel 1 and the Transmit DMA is done through DMA
channel 0.
Bits 2,1 Interrupt Select (Read/Write). See Table 15.
Figure 60. MIMIC Master Control Register (Z180 MPU Read/Write, Address xxFFH)
Bit 7 Transmit Emulation Delay Counter Enable (Read/Write) If bit 7 is set to
1, it enables the transmit delay timer. When the Z180 reads the Transmit
Register, it loads the transmit delay timer from the Transmit Time Constant
Register and enables the timer to count down to zero. This timer delays
setting the Transmit Holding Register Empty (THRE) bit until the timer times
out. If this bit is 0, then THRE is set immediately on a Z180 read of the
Transmit Register. This bit also enables the emulation timer used in
Transmitter Double Buffering.
Bit 6 Receive Emulation Delay Counter Enable (Read/Write) If bit 6 is set to
1, it enables the receive delay timer. When the Z180 writes to the Receive
Buffer, it loads the receive delay timer from the Receive Time Constant
Register and enables the timer to count down to zero. This timer delays
setting the Data Ready (DR) bit in the LSR until the timer times out. If this
bit is 0 then DR is set immediately on a Z180 write to the Receive Buffer.
Bit 0 Vector Include Status (Read/Write) This bit is used to select the interrupt response mode of the Z180. A 0 in this bit enables Mode 0 interrupts; a 1 enables Mode 2 response.
Table 15. MIMIC Master Control Register Interrupt Select
Bit 2 Bit 1 HINTR Function
0
0
HINTR is set to normal 16550 MIMIC mode.
A fully driven output is required when
external priority arbiters are used.
0
1
A wired AND condition on the HINTR pin is
possible to the PC/XT/AT. The interrupt
is active High with only the pull-up
of the HINTR pin driving; otherwise this
pin is tri-state. Wired AND is needed when
an external arbiter is not available.
1
0
HINTR is driven when out 2 of the Modem
Control Register is 1. HINTR is tri-state
when MCR out 2 is 0.
1
1
RESERVED
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Zilog
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
IUS/IP Register
The IUS/IP Register is used by the Z180TM MPU to determine the source of the
interrupt. This register will have the appropriate bit set when an interrupt
occurs.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 000000
Interrupt Pending 6 THR Write 5 TTO Transmitter Timeout 4 RBR Read 3 MCR Write
2 LCR Write 1 DLL Write 1 DLM Write 0 FCR Write or Tx Overrun
Interrupt Under Service (RD) Reset Highest IUS (WR)
Figure 61. IUS/IP Register (Z180 MPU, Address xxFEH)
Bit 7 Interrupt Under Service (Read/Write) This bit represents a logical OR of
each individual IUS bit for the internal MIMIC interrupt daisy chain. An IUS
bit is set when an interrupt is registered (IP set) and enabled (IE set), the
incoming IEI daisy chain is active (chain enabled) and an interrupt
acknowledge cycle is entered. By writing a 1 to this bit the highest priority
IUS bit that is set will be reset. Writing a 0 to this bit has no effect.
This should be done at the end of every MIMIC Interrupt Service routine.
Bit 6 Transmit Holding Register Written (Read Only) This bit is set when the
PC/XT/AT writes to the Transmit Holding Register. It is reset when the Z180
MPU reads the Transmit Holding Register. In FIFO mode, this bit is set when
the trigger level is reached (4,8,14 bytes available). Note: The THR bit is
set (interrupts) when the transmitter FIFO reaches the data available trigger
level set in the MPU FCR control register. The bit and interrupt source is
cleared when the number of data bytes falls below the set trigger level.
Bit 5 Transmitter Timeout with Data in FIFO (Read Only) This bit is set when
the transmitter FIFO has been idle (no read or write and timer decrements to
zero) with data bytes below the trigger level. It is cleared when the FIFO is
read or written.
Bit 4 Receive Buffer Read (Read Only) This bit is set when the PC/XT/AT reads
the Receive Buffer Register. It is reset when the Z180 MPU writes to the
Receive Buffer Register. In FIFO mode, this bit is set upon the PC reading all
the data in the receive FIFO. Note: RBR is set and interrupts when the receive
FIFO has been emptied by the PC. This bit and interrupt are cleared when one
or more bytes are written into the receive FIFO by the MPU.
Bit 3 Modem Control Register Write (Read Only) This bit is set when the
PC/XT/AT writes to the Modem Control Register. It is reset when the Z180TM MPU
reads the Modem Control Register.
Bit 2 Line Control Register Write (Read Only) This bit is set when the
PC/XT/AT writes to the Line Control Register. It is reset when the Z180 MPU
reads the Line Control Register.
Bit 1 Divisor Latch LS/MS Write (Read Only) This bit is set when the PC/XT/AT
writes to the Divisor Latch Least Significant or Most Significant bytes. It is
reset when the PC reads the LS/MS register(s). To determine which byte(s) have
been written, the Z180 must read either LS or MS locations and then repoll
this bit. If only one location is interrupting, the interrupt is cleared when
that location is read by the Z180.
Bit 0 FIFO Control Register Write (Read Only) This bit is set when the
PC/XT/AT writes to the FCR. This bit is also set when Transmit occurs. It is
reset when the Z180 MPU reads this register.
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DS971820600
Zilog Interrupt Enable Register
PRELIM INARY
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
The IE Register allows each of the 16550/8250 interrupts to the Z180TM MPU to
be masked off individually or globally.
D7 D6 D5 D4 D3 D2 D1 D0
00 0 0 0 0 0 0
Interrupt Enable 6 Enable THR IRQ 5 Enable TTO IRQ 4 RBR IRQ 3 Enable LCR IRQ
2 Enable MCR IRQ 1 Enable DLL/DLM IRQ 0 Enable FCR IRQ MIE
Figure 62. IE Register (Z180 MPU, Address xxFDH)
Bit 7 Master Interrupt Enable (Read/Write) If bit 7 is 0, all interrupts from
the 16550 MIMIC are masked off. If this bit is 1, then interrupts are enabled
individually by setting the appropriate bit.
Bit 6 Enable THR Interrupt (Read/Write) If this bit is 1, it enables the
Transmit Holding Register Interrupt.
Bit 5 Enable TTO Interrupt (Read/Write) If this bit is 1, it enables the
Transmitter Timeout Interrupt. This interrupts the CPU when characters remain
in the FIFO below the trigger level and the FIFO is not read or written for
the length of time in the transmitter timeout register.
Priority of interrupts are in this order:
(Highest) 6 THR IRQ 5 TTO IRQ 4 RBR IRQ 3 MCR IRQ 2 LCR IRQ 1 DLL IRQ 1 DLM
IRQ
(Lowest) 0 FCR or Tx OVERRUN IRQ
Interrupt Vector Register
The Interrupt Vector Register contains either the opcode (Z180 Interrupt Mode
0) or the modified vector used as the lower address for a Z180 interrupt
service routine (Z180 Interrupt Mode 2), depending upon the VIS bit in the MMC
Register (MIMIC Master Control Register). If the VIS bit is 0, then Z180 Mode
0 interrupt is selected; if VIS is 1, then Z180 Mode 2 is selected. Note that
in Z180 Interrupt Mode 0, the data input to the MPU during the interrupt
acknowledge cycle is an instruction opcode; in Z180 Interrupt Mode 2, this
data (modified depending on the source of the interrupt) becomes part of an
address from which to get the starting address of the interrupt service
routine.
D7 D6 D5 D4 D3 D2 D1 D0
0 0000000
0/Opcode Status/Opcode Upper Nibble IVEC
Bit 4 Enable RBR Interrupt (Read/Write) If this bit is 1, it enables the
Receive Buffer Register Interrupt.
Bit 3 Enable LCR Interrupt (Read/Write) If this bit is 1, it enables the Line
Control Register interrupt.
Bit 2 Enable MCR Interrupt (Read/Write) If this bit is 1, it enables the Modem
Control Register Interrupt.
Bit 1 Enable DLL/DLM Interrupt (Read/Write) If this bit is 1, it enables the
Divisor Latch Least and Most Significant Byte interrupts.
Bit 0 Enable FCR Interrupt (Read/Write) If this bit is 1 , then interrupts are
enabled for a PC write to the FIFO control register (FCR) or for occurrence of
Tx Overrun.
Figure 63. IVEC Register (Z180 MPU, Address xxFCH)
Bits 7-4 Upper Nibble IVEC (Read/Write) These four bits generate either an
opcode for Z180 Interrupt Mode 0, or the upper four bits of the interrupt
modified vector used as an 8-bit address to support the Z180 Interrupt Mode 2.
These bits are read/write and always read back what was last written to them.
Bits 3-1 Interrupt Modified Vector/Opcode (Read/Write Table 16) These three
bits are the Interrupt Status bits when VIS in the MMC register is 1 (Z180
Interrupt Mode 2). If VIS bit is 0, then this field contains bit 3-bit 1 of
the opcode. If the VIS bit is 0, then these bits contain what was last written
to them.
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Zilog
PRELIM INARY
Interrupt Vector Register (Continued)
Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL
Table 16. Interrupt Status Bits
Bits 3, 2, 1
Interrupt Request
000
NO IRQ
001
FCR or Tx OVRN IRQ
010
DLL/DLM IRQ
011
LCR IRQ*
100
MCR IRQ*
101
RBR IRQ
110
TTO IRQ
111
THR IRQ
Note: * The order of LCR and MCR does not follow that of the IE Register.
Bit 7 and Bit 6 XMIT Trigger MSB,LSB This field determines the number of bytes available to read in the transmitter FIFO before an interrupt occurs to the MPU (Table 17).
Table 17. Transmitter Trigger Level
b7
b6
Level (# bytes)
0
0
1
0
1
4
1
0
8
1
1
14
Bit 0 0/Opcode (Read/Write) This bit is always 0 when the VIS bit is 1. If the
VIS bit is 0, this bit reads back what was last written to it.
The Interrupt Vector Register serves both interrupt modes. When the VIS bit is
0, the last value written to the register can be read back. If the VIS bit is
1, and an interrupt is pending, the value read is the last value written to
the upper nibble plus the status for the interrupt that is pending. If no
interrupt is pending, then the last value written to the upper nibble plus the
lower nibble is read from the register.
If the vector includes the status, then the lower four bits of the vector
change asynchronously depending on the interrupting source. Since this vector
changes asynchronously, then the interrupt service routine to read the IVEC
register might read the source of the most recent IRQ/INTACK cycle if that IRQ
does not have its IUS set.
Bit 5 Receive Timeout Enable This bit enables the Z80182/Z8L182 Receive
Timeout Timer that is used to emulate the four character timeout delay that is
specified by the 16550. If no read or write to the RCVR FIFO has taken place
and data bytes are available, but are below the PC trigger level. If this
timer reaches zero, an interrupt is sent to the PC.
Bit 4 Transmitter Timeout Enable This bit enables the Z80182/Z8L182 timer that
is used to interrupt the Z180 MPU if characters are available, but are below
the trigger level. The timer is enabled to count down if this bit is 1 and the
number of bytes is below the set transmitter trigger level. The timer will
timeout and interrupt the MPU if no read or write to the XMIT FIFO takes place
within the timer interval.
Bit 3 Reserved. Program to zero.
D7 D6 D5 D4 D3 D2 D1 D0 0 00 00000
16450 MIMIC mode Enable RTO Timeout Enhancement TEMT Enable Reserved for
Future Use Always write and read as 0 XMIT Timeout Enable RCVR Timeout Enable
XMIT Trigger LSB XMIT Trigger MSB
Figure 64. FIFO Status and Control Register (Z180 MPU Read/Write, Address
xxECH)
Bit 2 (Reset value = 0) TEMT/Double Buffer When enabled the Tx buffer can hold
one extra byte (2 bytes total in 16450 mode). (Do not enable in 16550 mode.)
TEMT Emulation If character delay emulation is not used the TEMT bit is
automated. (Refer to page 26 for TEMT/Double