TE0712 CPLD with Xilinx Artix 7 Trenz Electronic Instruction Manual

: June 15, 2024
: TRENZ

Table of Contents

Overview
Feature Summary
Product Specification
Appx. A: Change History
Appx. B: Legal Notices
References
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TE0712 CPLD with Xilinx Artix 7 Trenz Electronic Instruction Manual

Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TE0712+CPLD

Overview

Firmware for PCB CPLD with designator U3: LCMX02-256HC

Feature Summary

JTAG Multiplexer
Module Power sequencing
FPGA Configuration sequencing
LED Status and User access
FPGA IO User access

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD Name| Direct ion| Pi n| Description
---|---|---|---
JTAGEN| in| 26| Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA)
TMS / M_TMS| IN| 29| JTAG from B2B connector
TCK / M_TCK| IN| 30| JTAG from B2B connector
TDI / M_TDI| IN| 32| JTAG from B2B connector
TDO / M_TDO| OUT| 1| JTAG from B2B connector
F_TMS / C_TMS| OUT| 21| JTAG to FPGA
F_TCK / C_TCK| OUT| 17| JTAG to FPGA
F_TDI / C_TDI| OUT| 23| JTAG to FPGA
F_TDO / C_TDO| IN| 20| JTAG to FPGA
ULI_SYSTEM / XIO| IN| 4| FPGA access W22 PIN
FPGA_IO| INOUT| 10| FPGA access U22 PIN (PUDC)
RESIN| IN| 16| RESETIN from B2B connector (Negative Reset)
DONE| IN| 28| FPGA Configuration DONE_0 Pin
PROG_B| OUT| 27| FPGA Configuration PROGRAM_B_0 Pin
PGOOD| OUT| 12| PGOOD to B2B connector
3.3V / PG_SENSE| IN| 25| from module generated 3.3V Voltage
EN1| IN| 11| Power Enable from B2B Connector (Positive Enable)
SYSLED2 / LED1| OUT| 8| Module LED D2 (Red)
SYSLED1/ LED2| OUT| 9| Module LED D1 (Green)
MODE| | 13| / currently_not_used
NOSEQ| | 14| / currently_not_used
ULI_CPLD| | 5| / currently_not_used

Functional Description

JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via
JTAGEN (logical one for CPLD, logical zero for FPGA).
Power
PGOOD is zero, if EN1 or PG_SENSE is zero else high impedance state.
PUDC is high during FPGA power up.
FPGA Configuration
FPGA configuration process will be stared, if RESIN, PG_SENSE and EN1 is ONE.
LED

LED	STATUS	Condition	User defined
LED1 (Red)	ON	RSIN=0	—
LED1 (Red)	Blink	RSIN=1, DONE=0	—
LED1 (Red)	X	RSIN=1, DONE=1	FPGA_IO Pin
LED2 (Green)	ON	RSIN=0	—
LED2 (Green)	Blink	RSIN=1, DONE=0	—
LED2 (Green)	X	RSIN=1, DONE=1	XIO Pin

Appx. A: Change History

Revision Changes
To get content of older revision got to “Change History” of this page and select older document revision number.

Date| Document Revision| CPLD Firmware Revision| Supported PCB Revision| Authors| Description
---|---|---|---|---|---

2018-05-15

| v.24

Appx. B: Legal Notices

Data Privacy

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Technology Licenses
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